Re: [PATCH v4 5/8] riscv/runtime-const: Introduce runtime_const_mask_32()

From: Charlie Jenkins <thecharlesjenkins@gmail.com>
To: K Prateek Nayak <kprateek.nayak@amd.com>
Cc: "Thomas Gleixner" <tglx@kernel.org>,
	"Ingo Molnar" <mingo@redhat.com>,
	"Peter Zijlstra" <peterz@infradead.org>,
	"Sebastian Andrzej Siewior" <bigeasy@linutronix.de>,
	"Paul Walmsley" <pjw@kernel.org>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Guo Ren" <guoren@kernel.org>,
	"Darren Hart" <dvhart@infradead.org>,
	"Davidlohr Bueso" <dave@stgolabs.net>,
	"André Almeida" <andrealmeid@igalia.com>,
	linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-s390@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	"Alexandre Ghiti" <alex@ghiti.fr>,
	"Charlie Jenkins" <charlie@rivosinc.com>,
	"Jisheng Zhang" <jszhang@kernel.org>,
	"Charles Mirabile" <cmirabil@redhat.com>
Subject: Re: [PATCH v4 5/8] riscv/runtime-const: Introduce runtime_const_mask_32()
Date: Tue, 23 Jun 2026 00:01:08 -0700	[thread overview]
Message-ID: <ajovNDH2uo6V4NJx@blinky> (raw)
In-Reply-To: <ff9678fb-4cca-4849-8ffb-7cb76db60e1a@amd.com>

On Tue, Jun 23, 2026 at 11:43:39AM +0530, K Prateek Nayak wrote:
> Hello Charlie,
> 
> On 6/23/2026 10:54 AM, Charlie Jenkins wrote:
> > On Thu, 30 Apr 2026 09:47:27 +0000, K Prateek Nayak <kprateek.nayak@amd.com> wrote:
> >> Futex hash computation requires a mask operation with read-only after
> >> init data that will be converted to a runtime constant in the subsequent
> >> commit.
> >>
> >> Introduce runtime_const_mask_32 to further optimize the mask operation
> >> in the futex hash computation hot path. GCC generates a:
> >>
> >>   lui   a0, 0x12346       # upper; +0x800 then >>12 for correct rounding
> >>   addi  a0, a0, 0x678     # lower 12 bits
> >>   and   a1, a1, a0        # a1 = a1 & a0
> >>
> >> pattern to tackle arbitrary 32-bit masks and the same was also suggested
> >> by Claude which is implemented here. The final (__ret & val) operation
> >> is intentionally placed outside of asm block to allow compilers to
> >> further optimize it if possible.
> > 
> > If the mask fits in 12 bits, we can nop the lui and the addi and just
> > patch an "andi" instruction with the 12 bits of the mask. We already do
> > this with the lui+addi block and nop the lui if val fits in 12 bits. I
> > would be happy to help draft that optimization.
> > 
> > But I think the better solution would be to take the power of 2
> > assumption since that will also benefit arm. We should still only emit
> > an andi if val fits in 12 bits, but if it doesn't we can patch in
> > shifts:
> > 
> > slli    a0,a0,x
> > srli    a0,a0,x
> > 
> > Where x is the constant (arch_size - _futex_shift - 1)
> 
> I can do that for the next version and use ubfx for ARM. I can just put
> in a BUG_ON() at the arch/ specific __runtime_fixup_mask() and if a
> new use case arises which hits that, we can perhaps move on the dynamic
> nop patching scheme that you mentioned earlier.
> 
> Let me know if that works and I can pivot to that scheme in v5 and send
> it out post -rc1 after some testing.

That sounds like a great plan :)

- Charlie

> 
> -- 
> Thanks and Regards,
> Prateek
> 

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