All of lore.kernel.org
 help / color / mirror / Atom feed
From: Mostafa Saleh <smostafa@google.com>
To: Jason Gunthorpe <jgg@nvidia.com>
Cc: iommu@lists.linux.dev, "Joerg Roedel (AMD)" <joro@8bytes.org>,
	Jean-Philippe Brucker <jpb@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	Robin Murphy <robin.murphy@arm.com>,
	Will Deacon <will@kernel.org>,
	David Matlack <dmatlack@google.com>,
	Pasha Tatashin <pasha.tatashin@soleen.com>,
	patches@lists.linux.dev, Pranjal Shrivastava <praan@google.com>,
	Samiullah Khawaja <skhawaja@google.com>
Subject: Re: [PATCH v2 5/8] iommu/arm-smmu-v3: Precompute the invalidation commands
Date: Wed, 8 Jul 2026 09:00:50 +0000	[thread overview]
Message-ID: <ak4Rwnr39HuP053s@google.com> (raw)
In-Reply-To: <20260707145812.GK220801@nvidia.com>

On Tue, Jul 07, 2026 at 11:58:12AM -0300, Jason Gunthorpe wrote:
> On Tue, Jul 07, 2026 at 11:52:25AM +0000, Mostafa Saleh wrote:
> > On Mon, Jul 06, 2026 at 01:26:42PM -0300, Jason Gunthorpe wrote:
> > > Store the required cmd data in the tlbi and just copy it out when
> > > processing each item in the invs list. The cmd form only depends on
> > > if the instance supports RIL or not, otherwise it is always the same.
> > > 
> > > This avoids redundant calculations for each invs entry.
> > 
> > I do not understand how does this avoids redundant calculation?
> > This would be the case if the domain shares multiple SMMUs,
> > otherwise, a range TLB invalidation should be unique and can not be
> > reused.
> 
> Right, if there are multiple SMMUs for the domain then currently it
> recomputes the range for every one.
> 
> At the moment I think we can't have multiple SMMUs per domain but
> Nioclin has a patch series changing that

Yes, it is not possible at the moment, I think it makes sense to have
it in this series, but a comment would be helpful as it is not clear
from just reading the code.

However, as I mentioned I am not sure if that actually helps on a real
system, is that something that you noticed during perf or based on the
code?

Thanks,
Mostafa

> 
> Jason

  reply	other threads:[~2026-07-08  9:00 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-06 16:26 [PATCH v2 0/8] Organize the SMMUv3 invalidation flow so iommupt can use it Jason Gunthorpe
2026-07-06 16:26 ` [PATCH v2 1/8] iommu/arm-smmu-v3: Pass the parameters for the invalidation in a struct Jason Gunthorpe
2026-07-07  3:04   ` Nicolin Chen
2026-07-07 11:18   ` Mostafa Saleh
2026-07-06 16:26 ` [PATCH v2 2/8] iommu/arm-smmu-v3: Move pgsize out of arm_smmu_inv Jason Gunthorpe
2026-07-07  3:57   ` Nicolin Chen
2026-07-07 16:15     ` Jason Gunthorpe
2026-07-07 17:21       ` Nicolin Chen
2026-07-08 18:43         ` Jason Gunthorpe
2026-07-07 11:24   ` Mostafa Saleh
2026-07-07 18:08     ` Jason Gunthorpe
2026-07-11 17:38       ` Daniel Mentz
2026-07-14 18:41         ` Jason Gunthorpe
2026-07-10  4:06   ` Daniel Mentz
2026-07-10 14:28     ` Jason Gunthorpe
2026-07-06 16:26 ` [PATCH v2 3/8] iommu/arm-smmu-v3: Optimize range invalidation for latency Jason Gunthorpe
2026-07-07  7:27   ` Nicolin Chen
2026-07-07 19:13     ` Jason Gunthorpe
2026-07-07 21:07       ` Nicolin Chen
2026-07-07 11:45   ` Mostafa Saleh
2026-07-08  0:10     ` Jason Gunthorpe
2026-07-06 16:26 ` [PATCH v2 4/8] iommu/arm-smmu-v3: Keep track in the arm_smmu_invs if RIL is used Jason Gunthorpe
2026-07-07  7:27   ` Nicolin Chen
2026-07-07 11:46   ` Mostafa Saleh
2026-07-06 16:26 ` [PATCH v2 5/8] iommu/arm-smmu-v3: Precompute the invalidation commands Jason Gunthorpe
2026-07-07 11:52   ` Mostafa Saleh
2026-07-07 14:58     ` Jason Gunthorpe
2026-07-08  9:00       ` Mostafa Saleh [this message]
2026-07-08 13:15         ` Jason Gunthorpe
2026-07-07 20:31   ` Nicolin Chen
2026-07-09 12:07     ` Jason Gunthorpe
2026-07-09 19:10       ` Nicolin Chen
2026-07-06 16:26 ` [PATCH v2 6/8] iommu/arm-smmu-v3: Populate the tlbi at the top of the call chain Jason Gunthorpe
2026-07-07 11:57   ` Mostafa Saleh
2026-07-08 18:09     ` Jason Gunthorpe
2026-07-07 21:51   ` Nicolin Chen
2026-07-08 18:40     ` Jason Gunthorpe
2026-07-06 16:26 ` [PATCH v2 7/8] iommu/arm-smmu-v3: Change how the tlbi describes the invalidation Jason Gunthorpe
2026-07-06 18:00   ` Robin Murphy
2026-07-06 19:45     ` Jason Gunthorpe
2026-07-08  1:41   ` Nicolin Chen
2026-07-08 18:27     ` Jason Gunthorpe
2026-07-08  5:29   ` Nicolin Chen
2026-07-09 18:25     ` Jason Gunthorpe
2026-07-09 21:32       ` Nicolin Chen
2026-07-06 16:26 ` [PATCH v2 8/8] iommu/arm-smmu-v3: Support the DS expansion of RIL's SCALE Jason Gunthorpe
2026-07-07 23:20   ` Nicolin Chen
2026-07-08  0:02     ` Jason Gunthorpe
2026-07-08  2:10       ` Nicolin Chen
2026-07-08 13:05         ` Jason Gunthorpe
2026-07-07 12:25 ` [PATCH v2 0/8] Organize the SMMUv3 invalidation flow so iommupt can use it Mostafa Saleh
2026-07-07 15:00   ` Jason Gunthorpe

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=ak4Rwnr39HuP053s@google.com \
    --to=smostafa@google.com \
    --cc=dmatlack@google.com \
    --cc=iommu@lists.linux.dev \
    --cc=jgg@nvidia.com \
    --cc=joro@8bytes.org \
    --cc=jpb@kernel.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=pasha.tatashin@soleen.com \
    --cc=patches@lists.linux.dev \
    --cc=praan@google.com \
    --cc=robin.murphy@arm.com \
    --cc=skhawaja@google.com \
    --cc=will@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.