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From: Zhao Liu <zhao1.liu@intel.com>
To: "Chang S. Bae" <chang.seok.bae@intel.com>
Cc: qemu-devel@nongnu.org, pbonzini@redhat.com, berrange@redhat.com,
	seanjc@google.com, qemu-stable@nongnu.org
Subject: Re: [PATCH] i386/cpu: Remove AMX-TF32 CPUID bit
Date: Thu, 9 Jul 2026 18:56:37 +0800	[thread overview]
Message-ID: <ak9+ZaWdzxr4eCju@intel.com> (raw)
In-Reply-To: <20260708210326.402054-1-chang.seok.bae@intel.com>

On Wed, Jul 08, 2026 at 09:03:26PM +0000, Chang S. Bae wrote:
> Date: Wed, 8 Jul 2026 21:03:26 +0000
> From: "Chang S. Bae" <chang.seok.bae@intel.com>
> Subject: [PATCH] i386/cpu: Remove AMX-TF32 CPUID bit
> X-Mailer: git-send-email 2.51.0
> 
> A recent revision of the Intel document [1] removed AMX-TF32, confirming
> that the feature will not be implemented in future processors. Remove the
> feature bit definition and its enumeration from the Diamond Rapids CPU
> model.
> 
> [1] Intel Architecture Instruction Set Extensions and Future Features
>     (Rev.062)
> 
> Cc: Zhao Liu <zhao1.liu@intel.com>
> Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
> ---
> KVM side posting: 
> https://lore.kernel.org/all/20260708210118.402005-1-chang.seok.bae@intel.com
> ---
>  target/i386/cpu.c | 5 ++---
>  target/i386/cpu.h | 2 --
>  2 files changed, 2 insertions(+), 5 deletions(-)> 

(Cc stable list)

At present, there's no user for DMR CPU model, so I think it's safe to
drop this feature flag from DMR CPU model driectly.

But to avoid unnecessary warning on older QEMU, IMO this patch should
be backported to the stable QEMU as well.

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

Regards,
Zhao



  reply	other threads:[~2026-07-09 10:28 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-08 21:03 [PATCH] i386/cpu: Remove AMX-TF32 CPUID bit Chang S. Bae
2026-07-09 10:56 ` Zhao Liu [this message]
2026-07-09 17:27   ` Chang S. Bae

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