[PATCH] i386/cpu: Remove AMX-TF32 CPUID bit

[PATCH] i386/cpu: Remove AMX-TF32 CPUID bit

[Chang S. Bae]

A recent revision of the Intel document [1] removed AMX-TF32, confirming
that the feature will not be implemented in future processors. Remove the
feature bit definition and its enumeration from the Diamond Rapids CPU
model.

[1] Intel Architecture Instruction Set Extensions and Future Features
    (Rev.062)

Cc: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
---
KVM side posting: 
https://lore.kernel.org/all/20260708210118.402005-1-chang.seok.bae@intel.com
---
 target/i386/cpu.c | 5 ++---
 target/i386/cpu.h | 2 --
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 5805d33ab92d..bde501ad8f7b 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1319,7 +1319,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
         .type = CPUID_FEATURE_WORD,
         .feat_names = {
             "amx-int8-alias", "amx-bf16-alias", "amx-complex-alias", "amx-fp16-alias",
-            "amx-fp8", NULL, "amx-tf32", "amx-avx512",
+            "amx-fp8", NULL, NULL, "amx-avx512",
             "amx-movrs", NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,
@@ -5726,8 +5726,7 @@ static const X86CPUDefinition builtin_x86_defs[] = {
             CPUID_1E_1_EAX_AMX_INT8_ALIAS | CPUID_1E_1_EAX_AMX_BF16_ALIAS |
             CPUID_1E_1_EAX_AMX_COMPLEX_ALIAS |
             CPUID_1E_1_EAX_AMX_FP16_ALIAS | CPUID_1E_1_EAX_AMX_FP8 |
-            CPUID_1E_1_EAX_AMX_TF32 | CPUID_1E_1_EAX_AMX_AVX512 |
-            CPUID_1E_1_EAX_AMX_MOVRS,
+            CPUID_1E_1_EAX_AMX_AVX512 | CPUID_1E_1_EAX_AMX_MOVRS,
         .features[FEAT_29_0_EBX] = CPUID_29_0_EBX_APX_NCI_NDD_NF,
         /*
          * Though this bit will be set by avx_version=2, it's better to
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index e6a197602d87..8354c0753f0d 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1111,8 +1111,6 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
 #define CPUID_1E_1_EAX_AMX_FP16_ALIAS      (1U << 3)
 /* AMX_FP8 instruction */
 #define CPUID_1E_1_EAX_AMX_FP8              (1U << 4)
-/* AMX_TF32 instruction */
-#define CPUID_1E_1_EAX_AMX_TF32             (1U << 6)
 /* AMX_AVX512 instruction */
 #define CPUID_1E_1_EAX_AMX_AVX512           (1U << 7)
 /* AMX_MOVRS instruction */
-- 
2.53.0

Re: [PATCH] i386/cpu: Remove AMX-TF32 CPUID bit

[Zhao Liu]

On Wed, Jul 08, 2026 at 09:03:26PM +0000, Chang S. Bae wrote:
> Date: Wed, 8 Jul 2026 21:03:26 +0000
> From: "Chang S. Bae" <chang.seok.bae@intel.com>
> Subject: [PATCH] i386/cpu: Remove AMX-TF32 CPUID bit
> X-Mailer: git-send-email 2.51.0
> 
> A recent revision of the Intel document [1] removed AMX-TF32, confirming
> that the feature will not be implemented in future processors. Remove the
> feature bit definition and its enumeration from the Diamond Rapids CPU
> model.
> 
> [1] Intel Architecture Instruction Set Extensions and Future Features
>     (Rev.062)
> 
> Cc: Zhao Liu <zhao1.liu@intel.com>
> Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
> ---
> KVM side posting: 
> https://lore.kernel.org/all/20260708210118.402005-1-chang.seok.bae@intel.com
> ---
>  target/i386/cpu.c | 5 ++---
>  target/i386/cpu.h | 2 --
>  2 files changed, 2 insertions(+), 5 deletions(-)> 

(Cc stable list)

At present, there's no user for DMR CPU model, so I think it's safe to
drop this feature flag from DMR CPU model driectly.

But to avoid unnecessary warning on older QEMU, IMO this patch should
be backported to the stable QEMU as well.

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

Regards,
Zhao

Re: [PATCH] i386/cpu: Remove AMX-TF32 CPUID bit

[Chang S. Bae]

On 7/9/2026 3:56 AM, Zhao Liu wrote:
> 
> (Cc stable list)
> 
> At present, there's no user for DMR CPU model, so I think it's safe to
> drop this feature flag from DMR CPU model driectly.
> 
> But to avoid unnecessary warning on older QEMU, IMO this patch should
> be backported to the stable QEMU as well.

Yes, I think so.

> 
> Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Thanks!