[PATCH v2 0/1] hw/riscv/riscv-iommu.c: check for misaligned IOHGATP_PPN

[PATCH v2 0/1] hw/riscv/riscv-iommu.c: check for misaligned IOHGATP_PPN

[Daniel Henrique Barboza]

Hi,

This new version fixes a blunder I made in v1 pointed by Chao and
Nutty - I was using the PPN value, instead of the page table base
address, to check for the 16kb alignment. 

We no longer need to change qos-riscv-iommu.h because now we're doing
the right thing.

Changes from v1:
- use PPN_PHYS(iohgatp_ppn), i.e. the page table base address, to 
  check for the 16kb alignment
- v1 link: https://lore.kernel.org/qemu-devel/20260630203155.2103084-1-daniel.barboza@oss.qualcomm.com/


Daniel Henrique Barboza (1):
  hw/riscv/riscv-iommu.c: check for misaligned IOHGATP_PPN

 hw/riscv/riscv-iommu.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

-- 
2.43.0

[PATCH v2 1/1] hw/riscv/riscv-iommu.c: check for misaligned IOHGATP_PPN

[Daniel Henrique Barboza]

We must check if IOHGATP_PPN is 16kb aligned for non-bare GATP modes.

Fixes: 69a9ae4836 ("hw/riscv/riscv-iommu: add ATS support")
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3550
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
 hw/riscv/riscv-iommu.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index 974042d017..ad8e108a23 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -813,6 +813,21 @@ static bool riscv_iommu_validate_device_ctx(RISCVIOMMUState *s,
         return false;
     }
 
+    if (gatp != RISCV_IOMMU_DC_IOHGATP_MODE_BARE) {
+        uint64_t iohgatp_ppn = get_field(ctx->gatp,
+                                         RISCV_IOMMU_DC_IOHGATP_PPN);
+
+        /*
+         * One of the conditions for a misconfigured DDT entry
+         * according to the riscv-spec: "DC.iohgatp.MODE is not
+         * Bare and the root page table (address) determined by
+         * DC.iohgatp.PPN is not aligned to a 16-KiB boundary."
+         */
+        if (PPN_PHYS(iohgatp_ppn) & ((1ULL << 14) - 1)) {
+            return false;
+        }
+    }
+
     fsc_mode = get_field(ctx->satp, RISCV_IOMMU_DC_FSC_MODE);
 
     if (ctx->tc & RISCV_IOMMU_DC_TC_PDTV) {
-- 
2.43.0

Re: [PATCH v2 1/1] hw/riscv/riscv-iommu.c: check for misaligned IOHGATP_PPN

[Chao Liu]

On Thu, Jul 02, 2026 at 05:36:16PM +0800, Daniel Henrique Barboza wrote:
> We must check if IOHGATP_PPN is 16kb aligned for non-bare GATP modes.
> 
> Fixes: 69a9ae4836 ("hw/riscv/riscv-iommu: add ATS support")
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3550
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>

> ---
>  hw/riscv/riscv-iommu.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index 974042d017..ad8e108a23 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -813,6 +813,21 @@ static bool riscv_iommu_validate_device_ctx(RISCVIOMMUState *s,
>          return false;
>      }
>  
> +    if (gatp != RISCV_IOMMU_DC_IOHGATP_MODE_BARE) {
> +        uint64_t iohgatp_ppn = get_field(ctx->gatp,
> +                                         RISCV_IOMMU_DC_IOHGATP_PPN);
> +
> +        /*
> +         * One of the conditions for a misconfigured DDT entry
> +         * according to the riscv-spec: "DC.iohgatp.MODE is not
> +         * Bare and the root page table (address) determined by
> +         * DC.iohgatp.PPN is not aligned to a 16-KiB boundary."
> +         */
> +        if (PPN_PHYS(iohgatp_ppn) & ((1ULL << 14) - 1)) {
> +            return false;
> +        }
> +    }
> +
>      fsc_mode = get_field(ctx->satp, RISCV_IOMMU_DC_FSC_MODE);
>  
>      if (ctx->tc & RISCV_IOMMU_DC_TC_PDTV) {
> -- 
> 2.43.0
> 

Re: [PATCH v2 1/1] hw/riscv/riscv-iommu.c: check for misaligned IOHGATP_PPN

[Nutty.Liu]

On 7/3/2026 4:36 AM, Daniel Henrique Barboza wrote:
> We must check if IOHGATP_PPN is 16kb aligned for non-bare GATP modes.
>
> Fixes: 69a9ae4836 ("hw/riscv/riscv-iommu: add ATS support")
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3550
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>

Thanks,
Nutty
> ---
>   hw/riscv/riscv-iommu.c | 15 +++++++++++++++
>   1 file changed, 15 insertions(+)
>
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index 974042d017..ad8e108a23 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -813,6 +813,21 @@ static bool riscv_iommu_validate_device_ctx(RISCVIOMMUState *s,
>           return false;
>       }
>   
> +    if (gatp != RISCV_IOMMU_DC_IOHGATP_MODE_BARE) {
> +        uint64_t iohgatp_ppn = get_field(ctx->gatp,
> +                                         RISCV_IOMMU_DC_IOHGATP_PPN);
> +
> +        /*
> +         * One of the conditions for a misconfigured DDT entry
> +         * according to the riscv-spec: "DC.iohgatp.MODE is not
> +         * Bare and the root page table (address) determined by
> +         * DC.iohgatp.PPN is not aligned to a 16-KiB boundary."
> +         */
> +        if (PPN_PHYS(iohgatp_ppn) & ((1ULL << 14) - 1)) {
> +            return false;
> +        }
> +    }
> +
>       fsc_mode = get_field(ctx->satp, RISCV_IOMMU_DC_FSC_MODE);
>   
>       if (ctx->tc & RISCV_IOMMU_DC_TC_PDTV) {

Re: [PATCH v2 0/1] hw/riscv/riscv-iommu.c: check for misaligned IOHGATP_PPN

[Alistair Francis]

On Fri, Jul 3, 2026 at 6:37 AM Daniel Henrique Barboza
<daniel.barboza@oss.qualcomm.com> wrote:
>
> Hi,
>
> This new version fixes a blunder I made in v1 pointed by Chao and
> Nutty - I was using the PPN value, instead of the page table base
> address, to check for the 16kb alignment.
>
> We no longer need to change qos-riscv-iommu.h because now we're doing
> the right thing.
>
> Changes from v1:
> - use PPN_PHYS(iohgatp_ppn), i.e. the page table base address, to
>   check for the 16kb alignment
> - v1 link: https://lore.kernel.org/qemu-devel/20260630203155.2103084-1-daniel.barboza@oss.qualcomm.com/

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>
> Daniel Henrique Barboza (1):
>   hw/riscv/riscv-iommu.c: check for misaligned IOHGATP_PPN
>
>  hw/riscv/riscv-iommu.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> --
> 2.43.0
>
>