[PATCH v4 0/5] pinctrl: renesas: rzg2l: Add support for RZ/G3S I3C

[PATCH v4 0/5] pinctrl: renesas: rzg2l: Add support for RZ/G3S I3C

[Claudiu Beznea]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Hi,

Series adds pinctrl support for the I3C on Renesas RZ/G3S SoC. For a
clean I3C support, cleanup patches for the pinctrl driver were also
included.

Thank you,
Claudiu

Changes in v4:
- dropped patch 1 from v3 as it was already applied

Changes in v3:
- collected tags
- added a fixes patch (patch 1/6)
- dropped already applied patches

Changes in v2:
- collected tags
- dropped patches for configuring I3C standby

Claudiu Beznea (5):
  pinctrl: renesas: rzg2l: Generalize the power source code
  pinctrl: renesas: rzg2l: Drop defines present in struct rzg2l_hwcfg
  dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document the missing I3C
    power source option
  pinctrl: renesas: rzg2l: Add RZ/G3S support for selecting the I3C
    power source
  arm64: dts: renesas: rzg3s-smarc-som: Enable I3C

 .../pinctrl/renesas,rzg2l-pinctrl.yaml        |   2 +-
 .../boot/dts/renesas/rzg3s-smarc-som.dtsi     |  18 ++
 .../boot/dts/renesas/rzg3s-smarc-switches.h   |   4 +
 drivers/pinctrl/renesas/pinctrl-rzg2l.c       | 254 +++++++++++++-----
 4 files changed, 204 insertions(+), 74 deletions(-)

-- 
2.43.0

[PATCH v4 1/5] pinctrl: renesas: rzg2l: Generalize the power source code

[Claudiu Beznea]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

The current functions used to get/set the pin power source check the
OTHER_POC register, which is specific to the RZ/G3L SoC only. To allow the
code to be extended for other power source functionalities (e.g. I3C on
RZ/G3S), generalize the functions used to get/set the pin power source.

For this, introduce the struct rzg2l_register_masks data structure whose
purpose is to store SoC specific register bit masks. The members of this
structure are then used in rzg2l_caps_to_pwr_reg() to retrieve the bitmask
corresponding to a SoC specific power source capability.

The conversion between HW specific power source values and SW specific
power source values is now handled through rzg2l_pwr_reg_val_to_ps() and
rzg2l_ps_to_pwr_reg_val().

Finally, to keep the code generic, the register update in
rzg2l_set_power_source() was changed to a read-modify-write approach to
cover all cases.

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---

Changes in v4:
- none

Changes in v3:
- collected tags

Changes in v2:
- none

 drivers/pinctrl/renesas/pinctrl-rzg2l.c | 177 +++++++++++++++---------
 1 file changed, 112 insertions(+), 65 deletions(-)

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index be52d47d77ae..6f3760851460 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -186,6 +186,7 @@
 #define PVDD_2500		2	/* I/O domain voltage 2.5V */
 #define PVDD_1800		1	/* I/O domain voltage <= 1.8V */
 #define PVDD_3300		0	/* I/O domain voltage >= 3.3V */
+#define PVDD_MASK		0x3
 
 #define PWPR_B0WI		BIT(7)	/* Bit Write Disable */
 #define PWPR_PFCWE		BIT(6)	/* PFC Register Write Enable */
@@ -268,6 +269,23 @@ struct rzg2l_register_offsets {
 	u16 other_poc;
 };
 
+/**
+ * struct rzg2l_register_masks - Masks for different RZ/G2L pinctrl functionalities
+ * @other_poc_pvdd1833_oth_awo_poc: PVDD1833_OTH_AWO_POC mask
+ * @other_poc_pvdd1833_oth_iso_poc: PVDD1833_OTH_ISO_POC mask
+ * @other_poc_wdtovf_n_poc: WDTOVF_N_POC mask
+ */
+struct rzg2l_register_masks {
+	union {
+		/* RZ/G3L masks */
+		struct {
+			u8 other_poc_pvdd1833_oth_awo_poc;
+			u8 other_poc_pvdd1833_oth_iso_poc;
+			u8 other_poc_wdtovf_n_poc;
+		};
+	};
+};
+
 /**
  * enum rzg2l_iolh_index - starting indices in IOLH specific arrays
  * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source
@@ -288,6 +306,8 @@ enum rzg2l_iolh_index {
 /**
  * struct rzg2l_hwcfg - hardware configuration data structure
  * @regs: hardware specific register offsets
+ * @masks: hardware specific masks for various functionalities available in
+ * the registers described by regs
  * @iolh_groupa_ua: IOLH group A uA specific values
  * @iolh_groupb_ua: IOLH group B uA specific values
  * @iolh_groupc_ua: IOLH group C uA specific values
@@ -301,6 +321,7 @@ enum rzg2l_iolh_index {
  */
 struct rzg2l_hwcfg {
 	const struct rzg2l_register_offsets regs;
+	const struct rzg2l_register_masks masks;
 	u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX];
 	u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX];
 	u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX];
@@ -1047,27 +1068,73 @@ static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
 }
 
 static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs,
-				 u32 caps, u8 *mask)
+				 const struct rzg2l_register_masks *masks,
+				 u32 caps, u16 *offset, u8 *mask)
 {
-	if (caps & PIN_CFG_IO_VMC_SD0)
-		return SD_CH(regs->sd_ch, 0);
-	if (caps & PIN_CFG_IO_VMC_SD1)
-		return SD_CH(regs->sd_ch, 1);
-	if (caps & PIN_CFG_IO_VMC_ETH0)
-		return ETH_POC(regs->eth_poc, 0);
-	if (caps & PIN_CFG_IO_VMC_ETH1)
-		return ETH_POC(regs->eth_poc, 1);
-	if (caps & PIN_CFG_IO_VMC_QSPI)
-		return QSPI;
+	*mask = PVDD_MASK;
+
+	if (caps & PIN_CFG_IO_VMC_SD0) {
+		*offset = SD_CH(regs->sd_ch, 0);
+		return 0;
+	}
+	if (caps & PIN_CFG_IO_VMC_SD1) {
+		*offset = SD_CH(regs->sd_ch, 1);
+		return 0;
+	}
+	if (caps & PIN_CFG_IO_VMC_ETH0) {
+		*offset = ETH_POC(regs->eth_poc, 0);
+		return 0;
+	}
+	if (caps & PIN_CFG_IO_VMC_ETH1) {
+		*offset = ETH_POC(regs->eth_poc, 1);
+		return 0;
+	}
+	if (caps & PIN_CFG_IO_VMC_QSPI) {
+		*offset = regs->qspi;
+		return 0;
+	}
 	if (caps & PIN_CFG_OTHER_POC_MASK) {
+		*offset = regs->other_poc;
 		if (caps & PIN_CFG_PVDD1833_OTH_AWO_POC)
-			*mask = BIT(0);
+			*mask = masks->other_poc_pvdd1833_oth_awo_poc;
 		else if (caps & PIN_CFG_PVDD1833_OTH_ISO_POC)
-			*mask = BIT(1);
+			*mask = masks->other_poc_pvdd1833_oth_iso_poc;
 		else
-			*mask = BIT(2);
+			*mask = masks->other_poc_wdtovf_n_poc;
+		return 0;
+	}
 
-		return OTHER_POC;
+	return -EINVAL;
+}
+
+static int rzg2l_pwr_reg_val_to_ps(u8 val, u32 caps)
+{
+	switch (val) {
+	case PVDD_1800:
+		return 1800;
+	case PVDD_2500:
+		return 2500;
+	case PVDD_3300:
+		return 3300;
+	}
+
+	return -EINVAL;
+}
+
+static int rzg2l_ps_to_pwr_reg_val(u8 *val, u32 ps, u32 caps)
+{
+	switch (ps) {
+	case 1800:
+		*val = PVDD_1800;
+		return 0;
+	case 2500:
+		if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1)))
+			return -EINVAL;
+		*val = PVDD_2500;
+		return 0;
+	case 3300:
+		*val = PVDD_3300;
+		return 0;
 	}
 
 	return -EINVAL;
@@ -1077,76 +1144,51 @@ static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps
 {
 	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
 	const struct rzg2l_register_offsets *regs = &hwcfg->regs;
-	u8 val, mask;
-	int pwr_reg;
+	const struct rzg2l_register_masks *masks = &hwcfg->masks;
+	u8 mask, val;
+	u16 offset;
+	int ret;
 
 	if (caps & PIN_CFG_SOFT_PS)
 		return pctrl->settings[pin].power_source;
 
-	pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps, &mask);
-	if (pwr_reg < 0)
-		return pwr_reg;
+	ret = rzg2l_caps_to_pwr_reg(regs, masks, caps, &offset, &mask);
+	if (ret)
+		return ret;
 
-	val = readb(pctrl->base + pwr_reg);
-	if (pwr_reg == OTHER_POC)
-		val = field_get(mask, val);
+	val = readb(pctrl->base + offset);
 
-	switch (val) {
-	case PVDD_1800:
-		return 1800;
-	case PVDD_2500:
-		return 2500;
-	case PVDD_3300:
-		return 3300;
-	default:
-		/* Should not happen. */
-		return -EINVAL;
-	}
+	return rzg2l_pwr_reg_val_to_ps(field_get(mask, val), caps);
 }
 
 static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps)
 {
 	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
 	const struct rzg2l_register_offsets *regs = &hwcfg->regs;
-	u8 poc_val, val, mask;
-	int pwr_reg;
+	const struct rzg2l_register_masks *masks = &hwcfg->masks;
+	u8 mask, val;
+	u16 offset;
+	int ret;
 
 	if (caps & PIN_CFG_SOFT_PS) {
 		pctrl->settings[pin].power_source = ps;
 		return 0;
 	}
 
-	switch (ps) {
-	case 1800:
-		poc_val = PVDD_1800;
-		break;
-	case 2500:
-		if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1)))
-			return -EINVAL;
-		poc_val = PVDD_2500;
-		break;
-	case 3300:
-		poc_val = PVDD_3300;
-		break;
-	default:
-		return -EINVAL;
-	}
+	ret = rzg2l_ps_to_pwr_reg_val(&val, ps, caps);
+	if (ret)
+		return ret;
+
+	ret = rzg2l_caps_to_pwr_reg(regs, masks, caps, &offset, &mask);
+	if (ret)
+		return ret;
 
-	pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps, &mask);
-	if (pwr_reg < 0)
-		return pwr_reg;
+	scoped_guard(raw_spinlock_irqsave, &pctrl->lock) {
+		u8 tmp = readb(pctrl->base + offset);
 
-	if (pwr_reg == OTHER_POC) {
-		scoped_guard(raw_spinlock_irqsave, &pctrl->lock) {
-			val = readb(pctrl->base + pwr_reg);
-			if (poc_val)
-				val |= mask;
-			else
-				val &= ~mask;
-			writeb(val, pctrl->base + pwr_reg);
-		}
-	} else {
-		writeb(poc_val, pctrl->base + pwr_reg);
+		tmp &= ~mask;
+		tmp |= field_prep(mask, val);
+		writeb(tmp, pctrl->base + offset);
 	}
 
 	pctrl->settings[pin].power_source = ps;
@@ -3795,6 +3837,11 @@ static const struct rzg2l_hwcfg rzg3l_hwcfg = {
 		.oen = 0x3018,
 		.other_poc = OTHER_POC,
 	},
+	.masks = {
+		.other_poc_pvdd1833_oth_awo_poc = BIT(0),
+		.other_poc_pvdd1833_oth_iso_poc = BIT(1),
+		.other_poc_wdtovf_n_poc = BIT(2),
+	},
 	.iolh_groupa_ua = {
 		/* 1v8 power source */
 		[RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000,
-- 
2.43.0

[PATCH v4 2/5] pinctrl: renesas: rzg2l: Drop defines present in struct rzg2l_hwcfg

[Claudiu Beznea]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Drop the QSPI and OTHER_POC register defines, which are SoC specific and
accessible through struct rzg2l_hwcfg::{qspi, other_poc}. While at it
move the assignement of rzg2l_hwcfg->regs->qspi upper to have the
initializations as sorted (by offsets) as possible.

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---

Changes in v4:
- none

Changes in v3:
- updated patch description
- collected tags

Changes in v2:
- none

 drivers/pinctrl/renesas/pinctrl-rzg2l.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 6f3760851460..b52a85066f63 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -180,8 +180,6 @@
 #define SMT(off)		(0x3400 + (off) * 8)
 #define SD_CH(off, ch)		((off) + (ch) * 4)
 #define ETH_POC(off, ch)	((off) + (ch) * 4)
-#define QSPI			(0x3008) /* known on RZ/{G2L,G2LC,G2UL,Five} only */
-#define OTHER_POC		(0x3028) /* known on RZ/G3L only */
 
 #define PVDD_2500		2	/* I/O domain voltage 2.5V */
 #define PVDD_1800		1	/* I/O domain voltage <= 1.8V */
@@ -3816,9 +3814,9 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = {
 	.regs = {
 		.pwpr = 0x3014,
 		.sd_ch = 0x3000,
+		.qspi = 0x3008,
 		.eth_poc = 0x300c,
 		.oen = 0x3018,
-		.qspi = QSPI,
 	},
 	.iolh_groupa_ua = {
 		/* 3v3 power source */
@@ -3835,7 +3833,7 @@ static const struct rzg2l_hwcfg rzg3l_hwcfg = {
 		.sd_ch = 0x3004,
 		.eth_poc = 0x3010,
 		.oen = 0x3018,
-		.other_poc = OTHER_POC,
+		.other_poc = 0x3028,
 	},
 	.masks = {
 		.other_poc_pvdd1833_oth_awo_poc = BIT(0),
-- 
2.43.0

[PATCH v4 3/5] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document the missing I3C power source option

[Claudiu Beznea]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

The I3C pins on the Renesas RZ/G3S SoC can be powered at either 1.2V or
1.8V. Document the missing 1.2V power source option.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---

Changes in v4:
- none

Changes in v3:
- collected tags

Changes in v2:
- collected tags

 .../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml      | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index fb1fe1ea759f..32864c9add4a 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -129,7 +129,7 @@ additionalProperties:
           enum: [ 33, 50, 66, 100 ]
         power-source:
           description: I/O voltage in millivolt.
-          enum: [ 1800, 2500, 3300 ]
+          enum: [ 1200, 1800, 2500, 3300 ]
         slew-rate: true
         gpio-hog: true
         gpios: true
-- 
2.43.0

[PATCH v4 4/5] pinctrl: renesas: rzg2l: Add RZ/G3S support for selecting the I3C power source

[Claudiu Beznea]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

The Renesas RZ/G3S I3C pins can be powered at either 1.8V or 1.2V. The
pin controller provides a register to select between these two options.
Update the Renesas RZ/G2L pin controller driver to allow selecting the
I3C power source on RZ/G3S SoC.

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---

Changes in v4:
- none

Changes in v3:
- collected tags

Changes in v2:
- none

 drivers/pinctrl/renesas/pinctrl-rzg2l.c | 73 +++++++++++++++++++++++--
 1 file changed, 68 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index b52a85066f63..9a0706fea220 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -69,6 +69,7 @@
 #define PIN_CFG_PVDD1833_OTH_AWO_POC	BIT(19) /* known on RZ/G3L only */
 #define PIN_CFG_PVDD1833_OTH_ISO_POC	BIT(20) /* known on RZ/G3L only */
 #define PIN_CFG_WDTOVF_N_POC		BIT(21) /* known on RZ/G3L only */
+#define PIN_CFG_IO_VMC_I3C		BIT(22)
 
 #define RZG2L_SINGLE_PIN		BIT_ULL(63)	/* Dedicated pin */
 #define RZG2L_VARIABLE_CFG		BIT_ULL(62)	/* Variable cfg for port pins */
@@ -186,6 +187,9 @@
 #define PVDD_3300		0	/* I/O domain voltage >= 3.3V */
 #define PVDD_MASK		0x3
 
+#define PVDD_I3C_1200		1	/* I3C I/O domain voltage 1.2V */
+#define PVDD_I3C_1800		0	/* I3C I/O domain voltage 1.8V */
+
 #define PWPR_B0WI		BIT(7)	/* Bit Write Disable */
 #define PWPR_PFCWE		BIT(6)	/* PFC Register Write Enable */
 #define PWPR_REGWE_A		BIT(6)	/* PFC and PMC Register Write Enable on RZ/V2H(P) */
@@ -257,6 +261,7 @@ static const struct pin_config_item renesas_rzv2h_conf_items[] = {
  * @oen: OEN register offset
  * @qspi: QSPI register offset
  * @other_poc: OTHER_POC register offset
+ * @i3c_set: I3C_SET register offset
  */
 struct rzg2l_register_offsets {
 	u16 pwpr;
@@ -265,6 +270,7 @@ struct rzg2l_register_offsets {
 	u16 oen;
 	u16 qspi;
 	u16 other_poc;
+	u16 i3c_set;
 };
 
 /**
@@ -272,6 +278,7 @@ struct rzg2l_register_offsets {
  * @other_poc_pvdd1833_oth_awo_poc: PVDD1833_OTH_AWO_POC mask
  * @other_poc_pvdd1833_oth_iso_poc: PVDD1833_OTH_ISO_POC mask
  * @other_poc_wdtovf_n_poc: WDTOVF_N_POC mask
+ * @i3c_set_poc: I3C_SET_POC mask
  */
 struct rzg2l_register_masks {
 	union {
@@ -281,6 +288,11 @@ struct rzg2l_register_masks {
 			u8 other_poc_pvdd1833_oth_iso_poc;
 			u8 other_poc_wdtovf_n_poc;
 		};
+
+		/* RZ/G3S masks */
+		struct {
+			u8 i3c_set_poc;
+		};
 	};
 };
 
@@ -391,6 +403,7 @@ struct rzg2l_pinctrl_pin_settings {
  * @oen: Output Enable register cache
  * @other_poc: OTHER_POC register cache
  * @qspi: QSPI registers cache
+ * @i3c_set: I3C_SET register cache
  */
 struct rzg2l_pinctrl_reg_cache {
 	u8	*p;
@@ -409,6 +422,7 @@ struct rzg2l_pinctrl_reg_cache {
 	u8	oen;
 	u8	other_poc;
 	u8	qspi;
+	u8	i3c_set;
 };
 
 struct rzg2l_pinctrl {
@@ -441,6 +455,7 @@ struct rzg2l_pinctrl {
 };
 
 static const u16 available_ps[] = { 1800, 2500, 3300 };
+static const u16 available_i3c_ps[] = { 1200, 1800 };
 
 static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
 					      u64 pincfg,
@@ -1101,12 +1116,28 @@ static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs,
 			*mask = masks->other_poc_wdtovf_n_poc;
 		return 0;
 	}
+	if (caps & PIN_CFG_IO_VMC_I3C) {
+		*offset = regs->i3c_set;
+		*mask = masks->i3c_set_poc;
+		return 0;
+	}
 
 	return -EINVAL;
 }
 
 static int rzg2l_pwr_reg_val_to_ps(u8 val, u32 caps)
 {
+	if (caps & PIN_CFG_IO_VMC_I3C) {
+		switch (val) {
+		case PVDD_I3C_1200:
+			return 1200;
+		case PVDD_I3C_1800:
+			return 1800;
+		}
+
+		return -EINVAL;
+	}
+
 	switch (val) {
 	case PVDD_1800:
 		return 1800;
@@ -1121,6 +1152,19 @@ static int rzg2l_pwr_reg_val_to_ps(u8 val, u32 caps)
 
 static int rzg2l_ps_to_pwr_reg_val(u8 *val, u32 ps, u32 caps)
 {
+	if (caps & PIN_CFG_IO_VMC_I3C) {
+		switch (ps) {
+		case 1200:
+			*val = PVDD_I3C_1200;
+			return 0;
+		case 1800:
+			*val = PVDD_I3C_1800;
+			return 0;
+		}
+
+		return -EINVAL;
+	}
+
 	switch (ps) {
 	case 1800:
 		*val = PVDD_1800;
@@ -1194,12 +1238,21 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps
 	return 0;
 }
 
-static bool rzg2l_ps_is_supported(u16 ps)
+static bool rzg2l_ps_is_supported(u16 ps, u32 caps)
 {
-	unsigned int i;
+	unsigned int i, len;
+	const u16 *array;
 
-	for (i = 0; i < ARRAY_SIZE(available_ps); i++) {
-		if (available_ps[i] == ps)
+	if (caps & PIN_CFG_IO_VMC_I3C) {
+		array = available_i3c_ps;
+		len = ARRAY_SIZE(available_i3c_ps);
+	} else {
+		array = available_ps;
+		len = ARRAY_SIZE(available_ps);
+	}
+
+	for (i = 0; i < len; i++) {
+		if (array[i] == ps)
 			return true;
 	}
 
@@ -1800,7 +1853,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
 
 	/* Apply power source. */
 	if (settings.power_source != pctrl->settings[_pin].power_source) {
-		ret = rzg2l_ps_is_supported(settings.power_source);
+		ret = rzg2l_ps_is_supported(settings.power_source, cfg);
 		if (!ret)
 			return -EINVAL;
 
@@ -2498,6 +2551,8 @@ static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
 	{ "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x2, 0, PIN_CFG_IEN) },
 	{ "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x2, 1, PIN_CFG_IEN) },
 	{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) },
+	{ "I3C_SDA", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IEN | PIN_CFG_IO_VMC_I3C)) },
+	{ "I3C_SCL", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IEN | PIN_CFG_IO_VMC_I3C)) },
 	{ "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
 	{ "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
 						     PIN_CFG_IO_VMC_SD0)) },
@@ -3717,6 +3772,8 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev)
 	cache->oen = readb(pctrl->base + pctrl->data->hwcfg->regs.oen);
 	if (regs->other_poc)
 		cache->other_poc = readb(pctrl->base + regs->other_poc);
+	if (regs->i3c_set)
+		cache->i3c_set = readb(pctrl->base + regs->i3c_set);
 
 	if (pctrl->syscon) {
 		int ret;
@@ -3759,6 +3816,8 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev)
 		writeb(cache->qspi, pctrl->base + regs->qspi);
 	if (regs->other_poc)
 		writeb(cache->other_poc, pctrl->base + regs->other_poc);
+	if (regs->i3c_set)
+		writeb(cache->i3c_set, pctrl->base + regs->i3c_set);
 
 	raw_spin_lock_irqsave(&pctrl->lock, flags);
 	rzg2l_oen_write_with_pwpr(pctrl, cache->oen);
@@ -3871,8 +3930,12 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = {
 		.pwpr = 0x3000,
 		.sd_ch = 0x3004,
 		.eth_poc = 0x3010,
+		.i3c_set = 0x301c,
 		.oen = 0x3018,
 	},
+	.masks = {
+		.i3c_set_poc = BIT(2),
+	},
 	.iolh_groupa_ua = {
 		/* 1v8 power source */
 		[RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000,
-- 
2.43.0

[PATCH v4 5/5] arm64: dts: renesas: rzg3s-smarc-som: Enable I3C

[Claudiu Beznea]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

The Renesas RZ/G3S SMARC SoM board has a connector for I3C interface.
Enable I3C.

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---

Changes in v4:
- none

Changes in v3:
- collected tags

Changes in v2:
- dropped pinctrl sleep state

 .../boot/dts/renesas/rzg3s-smarc-som.dtsi      | 18 ++++++++++++++++++
 .../boot/dts/renesas/rzg3s-smarc-switches.h    |  4 ++++
 2 files changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
index b45acfe6288a..af7357fe4655 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
@@ -168,6 +168,14 @@ a0 80 30 30 9c
 	};
 };
 
+&i3c {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i3c_pins>;
+	i2c-scl-hz = <400000>;
+	i3c-scl-hz = <12500000>;
+	status = "okay";
+};
+
 &pcie_port0 {
 	clocks = <&versa3 5>;
 	clock-names = "ref";
@@ -302,6 +310,16 @@ mux {
 		};
 	};
 
+	i3c_pins: i3c {
+		pins = "I3C_SDA", "I3C_SCL";
+#if SW_CONFIG4 == SW_ON
+		power-source = <1200>;
+#else
+		power-source = <1800>;
+#endif
+		input-enable;
+	};
+
 	sdhi0_pins: sd0 {
 		data {
 			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
index bbf908a5322c..9cccc87da057 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
@@ -25,9 +25,13 @@
  * @SW_CONFIG3:
  *	SW_OFF - SD2 is connected to SoC
  *	SW_ON  - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC
+ * @SW_CONFIG4:
+ *	SW_OFF - I3C voltage is 1.8V
+ *	SW_ON  - I3C voltage is 1.2V
  */
 #define SW_CONFIG2	SW_OFF
 #define SW_CONFIG3	SW_ON
+#define SW_CONFIG4	SW_OFF
 
 /*
  * SW_OPT_MUX[x] switches' states:
-- 
2.43.0

Re: [PATCH v4 0/5] pinctrl: renesas: rzg2l: Add support for RZ/G3S I3C

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 132 bytes --]


> Changes in v4:
> - dropped patch 1 from v3 as it was already applied

All still works on top of linux-next as of today. Thanks!


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

RE: [PATCH v4 4/5] pinctrl: renesas: rzg2l: Add RZ/G3S support for selecting the I3C power source

[Biju Das]

Hi Claudiu,

Thanks for the patch.

> -----Original Message-----
> From: Claudiu Beznea <claudiu.beznea+renesas@tuxon.dev>
> Sent: 10 July 2026 12:37
> Subject: [PATCH v4 4/5] pinctrl: renesas: rzg2l: Add RZ/G3S support for selecting the I3C power source
> 
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> The Renesas RZ/G3S I3C pins can be powered at either 1.8V or 1.2V. The pin controller provides a register
> to select between these two options.
> Update the Renesas RZ/G2L pin controller driver to allow selecting the I3C power source on RZ/G3S SoC.
> 
> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
> 
> Changes in v4:
> - none
> 
> Changes in v3:
> - collected tags
> 
> Changes in v2:
> - none
> 
>  drivers/pinctrl/renesas/pinctrl-rzg2l.c | 73 +++++++++++++++++++++++--
>  1 file changed, 68 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> index b52a85066f63..9a0706fea220 100644
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -69,6 +69,7 @@
>  #define PIN_CFG_PVDD1833_OTH_AWO_POC	BIT(19) /* known on RZ/G3L only */
>  #define PIN_CFG_PVDD1833_OTH_ISO_POC	BIT(20) /* known on RZ/G3L only */
>  #define PIN_CFG_WDTOVF_N_POC		BIT(21) /* known on RZ/G3L only */
> +#define PIN_CFG_IO_VMC_I3C		BIT(22)
> 
>  #define RZG2L_SINGLE_PIN		BIT_ULL(63)	/* Dedicated pin */
>  #define RZG2L_VARIABLE_CFG		BIT_ULL(62)	/* Variable cfg for port pins */
> @@ -186,6 +187,9 @@
>  #define PVDD_3300		0	/* I/O domain voltage >= 3.3V */
>  #define PVDD_MASK		0x3
> 
> +#define PVDD_I3C_1200		1	/* I3C I/O domain voltage 1.2V */
> +#define PVDD_I3C_1800		0	/* I3C I/O domain voltage 1.8V */
> +
>  #define PWPR_B0WI		BIT(7)	/* Bit Write Disable */
>  #define PWPR_PFCWE		BIT(6)	/* PFC Register Write Enable */
>  #define PWPR_REGWE_A		BIT(6)	/* PFC and PMC Register Write Enable on RZ/V2H(P) */
> @@ -257,6 +261,7 @@ static const struct pin_config_item renesas_rzv2h_conf_items[] = {
>   * @oen: OEN register offset
>   * @qspi: QSPI register offset
>   * @other_poc: OTHER_POC register offset
> + * @i3c_set: I3C_SET register offset
>   */
>  struct rzg2l_register_offsets {
>  	u16 pwpr;
> @@ -265,6 +270,7 @@ struct rzg2l_register_offsets {
>  	u16 oen;
>  	u16 qspi;
>  	u16 other_poc;
> +	u16 i3c_set;


>  };
> 
>  /**
> @@ -272,6 +278,7 @@ struct rzg2l_register_offsets {
>   * @other_poc_pvdd1833_oth_awo_poc: PVDD1833_OTH_AWO_POC mask
>   * @other_poc_pvdd1833_oth_iso_poc: PVDD1833_OTH_ISO_POC mask
>   * @other_poc_wdtovf_n_poc: WDTOVF_N_POC mask
> + * @i3c_set_poc: I3C_SET_POC mask
>   */
>  struct rzg2l_register_masks {
>  	union {
> @@ -281,6 +288,11 @@ struct rzg2l_register_masks {
>  			u8 other_poc_pvdd1833_oth_iso_poc;
>  			u8 other_poc_wdtovf_n_poc;
>  		};
> +
> +		/* RZ/G3S masks */
> +		struct {
> +			u8 i3c_set_poc;

How this POC is different from Ethernet, SDHI and XSPI POC?
For consistency, can't we handle like others?

Cheers,
Biju

> +		};
>  	};
>  };
> 
> @@ -391,6 +403,7 @@ struct rzg2l_pinctrl_pin_settings {
>   * @oen: Output Enable register cache
>   * @other_poc: OTHER_POC register cache
>   * @qspi: QSPI registers cache
> + * @i3c_set: I3C_SET register cache
>   */
>  struct rzg2l_pinctrl_reg_cache {
>  	u8	*p;
> @@ -409,6 +422,7 @@ struct rzg2l_pinctrl_reg_cache {
>  	u8	oen;
>  	u8	other_poc;
>  	u8	qspi;
> +	u8	i3c_set;
>  };
> 
>  struct rzg2l_pinctrl {
> @@ -441,6 +455,7 @@ struct rzg2l_pinctrl {  };
> 
>  static const u16 available_ps[] = { 1800, 2500, 3300 };
> +static const u16 available_i3c_ps[] = { 1200, 1800 };
> 
>  static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
>  					      u64 pincfg,
> @@ -1101,12 +1116,28 @@ static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs,
>  			*mask = masks->other_poc_wdtovf_n_poc;
>  		return 0;
>  	}
> +	if (caps & PIN_CFG_IO_VMC_I3C) {
> +		*offset = regs->i3c_set;
> +		*mask = masks->i3c_set_poc;
> +		return 0;
> +	}
> 
>  	return -EINVAL;
>  }
> 
>  static int rzg2l_pwr_reg_val_to_ps(u8 val, u32 caps)  {
> +	if (caps & PIN_CFG_IO_VMC_I3C) {
> +		switch (val) {
> +		case PVDD_I3C_1200:
> +			return 1200;
> +		case PVDD_I3C_1800:
> +			return 1800;
> +		}
> +
> +		return -EINVAL;
> +	}
> +
>  	switch (val) {
>  	case PVDD_1800:
>  		return 1800;
> @@ -1121,6 +1152,19 @@ static int rzg2l_pwr_reg_val_to_ps(u8 val, u32 caps)
> 
>  static int rzg2l_ps_to_pwr_reg_val(u8 *val, u32 ps, u32 caps)  {
> +	if (caps & PIN_CFG_IO_VMC_I3C) {
> +		switch (ps) {
> +		case 1200:
> +			*val = PVDD_I3C_1200;
> +			return 0;
> +		case 1800:
> +			*val = PVDD_I3C_1800;
> +			return 0;
> +		}
> +
> +		return -EINVAL;
> +	}
> +
>  	switch (ps) {
>  	case 1800:
>  		*val = PVDD_1800;
> @@ -1194,12 +1238,21 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps
>  	return 0;
>  }
> 
> -static bool rzg2l_ps_is_supported(u16 ps)
> +static bool rzg2l_ps_is_supported(u16 ps, u32 caps)
>  {
> -	unsigned int i;
> +	unsigned int i, len;
> +	const u16 *array;
> 
> -	for (i = 0; i < ARRAY_SIZE(available_ps); i++) {
> -		if (available_ps[i] == ps)
> +	if (caps & PIN_CFG_IO_VMC_I3C) {
> +		array = available_i3c_ps;
> +		len = ARRAY_SIZE(available_i3c_ps);
> +	} else {
> +		array = available_ps;
> +		len = ARRAY_SIZE(available_ps);
> +	}
> +
> +	for (i = 0; i < len; i++) {
> +		if (array[i] == ps)
>  			return true;
>  	}
> 
> @@ -1800,7 +1853,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
> 
>  	/* Apply power source. */
>  	if (settings.power_source != pctrl->settings[_pin].power_source) {
> -		ret = rzg2l_ps_is_supported(settings.power_source);
> +		ret = rzg2l_ps_is_supported(settings.power_source, cfg);
>  		if (!ret)
>  			return -EINVAL;
> 
> @@ -2498,6 +2551,8 @@ static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
>  	{ "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x2, 0, PIN_CFG_IEN) },
>  	{ "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x2, 1, PIN_CFG_IEN) },
>  	{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) },
> +	{ "I3C_SDA", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IEN | PIN_CFG_IO_VMC_I3C)) },
> +	{ "I3C_SCL", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IEN |
> +PIN_CFG_IO_VMC_I3C)) },
>  	{ "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
>  	{ "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
>  						     PIN_CFG_IO_VMC_SD0)) },
> @@ -3717,6 +3772,8 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev)
>  	cache->oen = readb(pctrl->base + pctrl->data->hwcfg->regs.oen);
>  	if (regs->other_poc)
>  		cache->other_poc = readb(pctrl->base + regs->other_poc);
> +	if (regs->i3c_set)
> +		cache->i3c_set = readb(pctrl->base + regs->i3c_set);
> 
>  	if (pctrl->syscon) {
>  		int ret;
> @@ -3759,6 +3816,8 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev)
>  		writeb(cache->qspi, pctrl->base + regs->qspi);
>  	if (regs->other_poc)
>  		writeb(cache->other_poc, pctrl->base + regs->other_poc);
> +	if (regs->i3c_set)
> +		writeb(cache->i3c_set, pctrl->base + regs->i3c_set);
> 
>  	raw_spin_lock_irqsave(&pctrl->lock, flags);
>  	rzg2l_oen_write_with_pwpr(pctrl, cache->oen); @@ -3871,8 +3930,12 @@ static const struct
> rzg2l_hwcfg rzg3s_hwcfg = {
>  		.pwpr = 0x3000,
>  		.sd_ch = 0x3004,
>  		.eth_poc = 0x3010,
> +		.i3c_set = 0x301c,
>  		.oen = 0x3018,
>  	},
> +	.masks = {
> +		.i3c_set_poc = BIT(2),
> +	},
>  	.iolh_groupa_ua = {
>  		/* 1v8 power source */
>  		[RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000,
> --
> 2.43.0
> 

Re: [PATCH v4 4/5] pinctrl: renesas: rzg2l: Add RZ/G3S support for selecting the I3C power source

[claudiu beznea]

Hi, Biju,

On 7/12/26 17:55, Biju Das wrote:
> Hi Claudiu,
> 
> Thanks for the patch.
> 
>> -----Original Message-----
>> From: Claudiu Beznea <claudiu.beznea+renesas@tuxon.dev>
>> Sent: 10 July 2026 12:37
>> Subject: [PATCH v4 4/5] pinctrl: renesas: rzg2l: Add RZ/G3S support for selecting the I3C power source
>>
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> The Renesas RZ/G3S I3C pins can be powered at either 1.8V or 1.2V. The pin controller provides a register
>> to select between these two options.
>> Update the Renesas RZ/G2L pin controller driver to allow selecting the I3C power source on RZ/G3S SoC.
>>
>> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
>> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>> ---
>>
>> Changes in v4:
>> - none
>>
>> Changes in v3:
>> - collected tags
>>
>> Changes in v2:
>> - none
>>
>>   drivers/pinctrl/renesas/pinctrl-rzg2l.c | 73 +++++++++++++++++++++++--
>>   1 file changed, 68 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>> index b52a85066f63..9a0706fea220 100644
>> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>> @@ -69,6 +69,7 @@
>>   #define PIN_CFG_PVDD1833_OTH_AWO_POC	BIT(19) /* known on RZ/G3L only */
>>   #define PIN_CFG_PVDD1833_OTH_ISO_POC	BIT(20) /* known on RZ/G3L only */
>>   #define PIN_CFG_WDTOVF_N_POC		BIT(21) /* known on RZ/G3L only */
>> +#define PIN_CFG_IO_VMC_I3C		BIT(22)
>>
>>   #define RZG2L_SINGLE_PIN		BIT_ULL(63)	/* Dedicated pin */
>>   #define RZG2L_VARIABLE_CFG		BIT_ULL(62)	/* Variable cfg for port pins */
>> @@ -186,6 +187,9 @@
>>   #define PVDD_3300		0	/* I/O domain voltage >= 3.3V */
>>   #define PVDD_MASK		0x3
>>
>> +#define PVDD_I3C_1200		1	/* I3C I/O domain voltage 1.2V */
>> +#define PVDD_I3C_1800		0	/* I3C I/O domain voltage 1.8V */
>> +
>>   #define PWPR_B0WI		BIT(7)	/* Bit Write Disable */
>>   #define PWPR_PFCWE		BIT(6)	/* PFC Register Write Enable */
>>   #define PWPR_REGWE_A		BIT(6)	/* PFC and PMC Register Write Enable on RZ/V2H(P) */
>> @@ -257,6 +261,7 @@ static const struct pin_config_item renesas_rzv2h_conf_items[] = {
>>    * @oen: OEN register offset
>>    * @qspi: QSPI register offset
>>    * @other_poc: OTHER_POC register offset
>> + * @i3c_set: I3C_SET register offset
>>    */
>>   struct rzg2l_register_offsets {
>>   	u16 pwpr;
>> @@ -265,6 +270,7 @@ struct rzg2l_register_offsets {
>>   	u16 oen;
>>   	u16 qspi;
>>   	u16 other_poc;
>> +	u16 i3c_set;
> 
> 
>>   };
>>
>>   /**
>> @@ -272,6 +278,7 @@ struct rzg2l_register_offsets {
>>    * @other_poc_pvdd1833_oth_awo_poc: PVDD1833_OTH_AWO_POC mask
>>    * @other_poc_pvdd1833_oth_iso_poc: PVDD1833_OTH_ISO_POC mask
>>    * @other_poc_wdtovf_n_poc: WDTOVF_N_POC mask
>> + * @i3c_set_poc: I3C_SET_POC mask
>>    */
>>   struct rzg2l_register_masks {
>>   	union {
>> @@ -281,6 +288,11 @@ struct rzg2l_register_masks {
>>   			u8 other_poc_pvdd1833_oth_iso_poc;
>>   			u8 other_poc_wdtovf_n_poc;
>>   		};
>> +
>> +		/* RZ/G3S masks */
>> +		struct {
>> +			u8 i3c_set_poc;
> 
> How this POC is different from Ethernet, SDHI and XSPI POC?

Different bit mask and offset for I3C SET_POC compared with ETH, SDHI, XSPI.

> For consistency, can't we handle like others?
Everything is handled the same way for all functionalities in 
rzg2l_caps_to_pwr_reg() from patch 1.

Thank you,
Claudiu

RE: [PATCH v4 4/5] pinctrl: renesas: rzg2l: Add RZ/G3S support for selecting the I3C power source

[Biju Das]

Hi Claudiu,

> -----Original Message-----
> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> Sent: 13 July 2026 14:19
> Subject: Re: [PATCH v4 4/5] pinctrl: renesas: rzg2l: Add RZ/G3S support for selecting the I3C power
> source
> 
> Hi, Biju,
> 
> On 7/12/26 17:55, Biju Das wrote:
> > Hi Claudiu,
> >
> > Thanks for the patch.
> >
> >> -----Original Message-----
> >> From: Claudiu Beznea <claudiu.beznea+renesas@tuxon.dev>
> >> Sent: 10 July 2026 12:37
> >> Subject: [PATCH v4 4/5] pinctrl: renesas: rzg2l: Add RZ/G3S support
> >> for selecting the I3C power source
> >>
> >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>
> >> The Renesas RZ/G3S I3C pins can be powered at either 1.8V or 1.2V.
> >> The pin controller provides a register to select between these two options.
> >> Update the Renesas RZ/G2L pin controller driver to allow selecting the I3C power source on RZ/G3S SoC.
> >>
> >> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> >> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >> ---
> >>
> >> Changes in v4:
> >> - none
> >>
> >> Changes in v3:
> >> - collected tags
> >>
> >> Changes in v2:
> >> - none
> >>
> >>   drivers/pinctrl/renesas/pinctrl-rzg2l.c | 73 +++++++++++++++++++++++--
> >>   1 file changed, 68 insertions(+), 5 deletions(-)
> >>
> >> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> >> b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> >> index b52a85066f63..9a0706fea220 100644
> >> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> >> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> >> @@ -69,6 +69,7 @@
> >>   #define PIN_CFG_PVDD1833_OTH_AWO_POC	BIT(19) /* known on RZ/G3L only */
> >>   #define PIN_CFG_PVDD1833_OTH_ISO_POC	BIT(20) /* known on RZ/G3L only */
> >>   #define PIN_CFG_WDTOVF_N_POC		BIT(21) /* known on RZ/G3L only */
> >> +#define PIN_CFG_IO_VMC_I3C		BIT(22)
> >>
> >>   #define RZG2L_SINGLE_PIN		BIT_ULL(63)	/* Dedicated pin */
> >>   #define RZG2L_VARIABLE_CFG		BIT_ULL(62)	/* Variable cfg for port pins */
> >> @@ -186,6 +187,9 @@
> >>   #define PVDD_3300		0	/* I/O domain voltage >= 3.3V */
> >>   #define PVDD_MASK		0x3
> >>
> >> +#define PVDD_I3C_1200		1	/* I3C I/O domain voltage 1.2V */
> >> +#define PVDD_I3C_1800		0	/* I3C I/O domain voltage 1.8V */
> >> +
> >>   #define PWPR_B0WI		BIT(7)	/* Bit Write Disable */
> >>   #define PWPR_PFCWE		BIT(6)	/* PFC Register Write Enable */
> >>   #define PWPR_REGWE_A		BIT(6)	/* PFC and PMC Register Write Enable on RZ/V2H(P) */
> >> @@ -257,6 +261,7 @@ static const struct pin_config_item renesas_rzv2h_conf_items[] = {
> >>    * @oen: OEN register offset
> >>    * @qspi: QSPI register offset
> >>    * @other_poc: OTHER_POC register offset
> >> + * @i3c_set: I3C_SET register offset
> >>    */
> >>   struct rzg2l_register_offsets {
> >>   	u16 pwpr;
> >> @@ -265,6 +270,7 @@ struct rzg2l_register_offsets {
> >>   	u16 oen;
> >>   	u16 qspi;
> >>   	u16 other_poc;
> >> +	u16 i3c_set;
> >
> >
> >>   };
> >>
> >>   /**
> >> @@ -272,6 +278,7 @@ struct rzg2l_register_offsets {
> >>    * @other_poc_pvdd1833_oth_awo_poc: PVDD1833_OTH_AWO_POC mask
> >>    * @other_poc_pvdd1833_oth_iso_poc: PVDD1833_OTH_ISO_POC mask
> >>    * @other_poc_wdtovf_n_poc: WDTOVF_N_POC mask
> >> + * @i3c_set_poc: I3C_SET_POC mask
> >>    */
> >>   struct rzg2l_register_masks {
> >>   	union {
> >> @@ -281,6 +288,11 @@ struct rzg2l_register_masks {
> >>   			u8 other_poc_pvdd1833_oth_iso_poc;
> >>   			u8 other_poc_wdtovf_n_poc;
> >>   		};
> >> +
> >> +		/* RZ/G3S masks */
> >> +		struct {
> >> +			u8 i3c_set_poc;
> >
> > How this POC is different from Ethernet, SDHI and XSPI POC?
> 
> Different bit mask and offset for I3C SET_POC compared with ETH, SDHI, XSPI.

RZ/G3L has i3c_set_poc, which has same bitmask as other_poc_wdtovf_n_poc.
Maybe create register specific masks??

struct other_poc and struct i3c_set instead of union. So that both RZ/G3L and
RZ/G3S can share the same struct for i3c.

Cheers,
Biju

Re: [PATCH v4 4/5] pinctrl: renesas: rzg2l: Add RZ/G3S support for selecting the I3C power source

[claudiu beznea]

On 7/13/26 16:56, Biju Das wrote:
> Hi Claudiu,
> 
>> -----Original Message-----
>> From: claudiu beznea <claudiu.beznea@tuxon.dev>
>> Sent: 13 July 2026 14:19
>> Subject: Re: [PATCH v4 4/5] pinctrl: renesas: rzg2l: Add RZ/G3S support for selecting the I3C power
>> source
>>
>> Hi, Biju,
>>
>> On 7/12/26 17:55, Biju Das wrote:
>>> Hi Claudiu,
>>>
>>> Thanks for the patch.
>>>
>>>> -----Original Message-----
>>>> From: Claudiu Beznea <claudiu.beznea+renesas@tuxon.dev>
>>>> Sent: 10 July 2026 12:37
>>>> Subject: [PATCH v4 4/5] pinctrl: renesas: rzg2l: Add RZ/G3S support
>>>> for selecting the I3C power source
>>>>
>>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>>
>>>> The Renesas RZ/G3S I3C pins can be powered at either 1.8V or 1.2V.
>>>> The pin controller provides a register to select between these two options.
>>>> Update the Renesas RZ/G2L pin controller driver to allow selecting the I3C power source on RZ/G3S SoC.
>>>>
>>>> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
>>>> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
>>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>> ---
>>>>
>>>> Changes in v4:
>>>> - none
>>>>
>>>> Changes in v3:
>>>> - collected tags
>>>>
>>>> Changes in v2:
>>>> - none
>>>>
>>>>    drivers/pinctrl/renesas/pinctrl-rzg2l.c | 73 +++++++++++++++++++++++--
>>>>    1 file changed, 68 insertions(+), 5 deletions(-)
>>>>
>>>> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>>>> b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>>>> index b52a85066f63..9a0706fea220 100644
>>>> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>>>> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>>>> @@ -69,6 +69,7 @@
>>>>    #define PIN_CFG_PVDD1833_OTH_AWO_POC	BIT(19) /* known on RZ/G3L only */
>>>>    #define PIN_CFG_PVDD1833_OTH_ISO_POC	BIT(20) /* known on RZ/G3L only */
>>>>    #define PIN_CFG_WDTOVF_N_POC		BIT(21) /* known on RZ/G3L only */
>>>> +#define PIN_CFG_IO_VMC_I3C		BIT(22)
>>>>
>>>>    #define RZG2L_SINGLE_PIN		BIT_ULL(63)	/* Dedicated pin */
>>>>    #define RZG2L_VARIABLE_CFG		BIT_ULL(62)	/* Variable cfg for port pins */
>>>> @@ -186,6 +187,9 @@
>>>>    #define PVDD_3300		0	/* I/O domain voltage >= 3.3V */
>>>>    #define PVDD_MASK		0x3
>>>>
>>>> +#define PVDD_I3C_1200		1	/* I3C I/O domain voltage 1.2V */
>>>> +#define PVDD_I3C_1800		0	/* I3C I/O domain voltage 1.8V */
>>>> +
>>>>    #define PWPR_B0WI		BIT(7)	/* Bit Write Disable */
>>>>    #define PWPR_PFCWE		BIT(6)	/* PFC Register Write Enable */
>>>>    #define PWPR_REGWE_A		BIT(6)	/* PFC and PMC Register Write Enable on RZ/V2H(P) */
>>>> @@ -257,6 +261,7 @@ static const struct pin_config_item renesas_rzv2h_conf_items[] = {
>>>>     * @oen: OEN register offset
>>>>     * @qspi: QSPI register offset
>>>>     * @other_poc: OTHER_POC register offset
>>>> + * @i3c_set: I3C_SET register offset
>>>>     */
>>>>    struct rzg2l_register_offsets {
>>>>    	u16 pwpr;
>>>> @@ -265,6 +270,7 @@ struct rzg2l_register_offsets {
>>>>    	u16 oen;
>>>>    	u16 qspi;
>>>>    	u16 other_poc;
>>>> +	u16 i3c_set;
>>>
>>>
>>>>    };
>>>>
>>>>    /**
>>>> @@ -272,6 +278,7 @@ struct rzg2l_register_offsets {
>>>>     * @other_poc_pvdd1833_oth_awo_poc: PVDD1833_OTH_AWO_POC mask
>>>>     * @other_poc_pvdd1833_oth_iso_poc: PVDD1833_OTH_ISO_POC mask
>>>>     * @other_poc_wdtovf_n_poc: WDTOVF_N_POC mask
>>>> + * @i3c_set_poc: I3C_SET_POC mask
>>>>     */
>>>>    struct rzg2l_register_masks {
>>>>    	union {
>>>> @@ -281,6 +288,11 @@ struct rzg2l_register_masks {
>>>>    			u8 other_poc_pvdd1833_oth_iso_poc;
>>>>    			u8 other_poc_wdtovf_n_poc;
>>>>    		};
>>>> +
>>>> +		/* RZ/G3S masks */
>>>> +		struct {
>>>> +			u8 i3c_set_poc;
>>>
>>> How this POC is different from Ethernet, SDHI and XSPI POC?
>>
>> Different bit mask and offset for I3C SET_POC compared with ETH, SDHI, XSPI.
> 
> RZ/G3L has i3c_set_poc, which has same bitmask as other_poc_wdtovf_n_poc.
> Maybe create register specific masks??
> 
> struct other_poc and struct i3c_set instead of union. So that both RZ/G3L and
> RZ/G3S can share the same struct for i3c.

When RZ/G3L I3C POC support will be added the i3c_set_poc member of struct 
rzg2l_register_masks could be moved as common member:

Current code base allows for this extension. You can have:

struct rzg2l_register_masks {
+       /* Common masks. */
+       u8 i3c_set_poc;
         union {
                 /* RZ/G3L masks */
                 struct {
                         u8 other_poc_pvdd1833_oth_awo_poc;
                         u8 other_poc_pvdd1833_oth_iso_poc;
                         u8 other_poc_wdtovf_n_poc;
                 };
-               /* RZ/G3S masks */
-               struct {
-                       u8 i3c_set_poc;
-               };
         };
};

// ...

const struct rzg2l_hwcfg rzg3l_hwcfg = {
         // ...

         .masks = {
                 .other_poc_pvdd1833_oth_awo_poc = BIT(0),
                 .other_poc_pvdd1833_oth_iso_poc = BIT(1),
                 .other_poc_wdtovf_n_poc = BIT(2),
+               .i3c_set_poc = BIT(x),
         },

         // ...
};

The rest of configuration and initialization code remains the same.

Thank you,
Claudiu

RE: [PATCH v4 4/5] pinctrl: renesas: rzg2l: Add RZ/G3S support for selecting the I3C power source

[Biju Das]

Hi Claudiu,

> -----Original Message-----
> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> Sent: 13 July 2026 15:57
> Subject: Re: [PATCH v4 4/5] pinctrl: renesas: rzg2l: Add RZ/G3S support for selecting the I3C power
> source
> 
> 
> 
> On 7/13/26 16:56, Biju Das wrote:
> > Hi Claudiu,
> >
> >> -----Original Message-----
> >> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> >> Sent: 13 July 2026 14:19
> >> Subject: Re: [PATCH v4 4/5] pinctrl: renesas: rzg2l: Add RZ/G3S
> >> support for selecting the I3C power source
> >>
> >> Hi, Biju,
> >>
> >> On 7/12/26 17:55, Biju Das wrote:
> >>> Hi Claudiu,
> >>>
> >>> Thanks for the patch.
> >>>
> >>>> -----Original Message-----
> >>>> From: Claudiu Beznea <claudiu.beznea+renesas@tuxon.dev>
> >>>> Sent: 10 July 2026 12:37
> >>>> Subject: [PATCH v4 4/5] pinctrl: renesas: rzg2l: Add RZ/G3S support
> >>>> for selecting the I3C power source
> >>>>
> >>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>>>
> >>>> The Renesas RZ/G3S I3C pins can be powered at either 1.8V or 1.2V.
> >>>> The pin controller provides a register to select between these two options.
> >>>> Update the Renesas RZ/G2L pin controller driver to allow selecting the I3C power source on RZ/G3S
> SoC.
> >>>>
> >>>> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> >>>> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> >>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>>> ---
> >>>>
> >>>> Changes in v4:
> >>>> - none
> >>>>
> >>>> Changes in v3:
> >>>> - collected tags
> >>>>
> >>>> Changes in v2:
> >>>> - none
> >>>>
> >>>>    drivers/pinctrl/renesas/pinctrl-rzg2l.c | 73 +++++++++++++++++++++++--
> >>>>    1 file changed, 68 insertions(+), 5 deletions(-)
> >>>>
> >>>> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> >>>> b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> >>>> index b52a85066f63..9a0706fea220 100644
> >>>> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> >>>> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> >>>> @@ -69,6 +69,7 @@
> >>>>    #define PIN_CFG_PVDD1833_OTH_AWO_POC	BIT(19) /* known on RZ/G3L only */
> >>>>    #define PIN_CFG_PVDD1833_OTH_ISO_POC	BIT(20) /* known on RZ/G3L only */
> >>>>    #define PIN_CFG_WDTOVF_N_POC		BIT(21) /* known on RZ/G3L only */
> >>>> +#define PIN_CFG_IO_VMC_I3C		BIT(22)
> >>>>
> >>>>    #define RZG2L_SINGLE_PIN		BIT_ULL(63)	/* Dedicated pin */
> >>>>    #define RZG2L_VARIABLE_CFG		BIT_ULL(62)	/* Variable cfg for port pins */
> >>>> @@ -186,6 +187,9 @@
> >>>>    #define PVDD_3300		0	/* I/O domain voltage >= 3.3V */
> >>>>    #define PVDD_MASK		0x3
> >>>>
> >>>> +#define PVDD_I3C_1200		1	/* I3C I/O domain voltage 1.2V */
> >>>> +#define PVDD_I3C_1800		0	/* I3C I/O domain voltage 1.8V */
> >>>> +
> >>>>    #define PWPR_B0WI		BIT(7)	/* Bit Write Disable */
> >>>>    #define PWPR_PFCWE		BIT(6)	/* PFC Register Write Enable */
> >>>>    #define PWPR_REGWE_A		BIT(6)	/* PFC and PMC Register Write Enable on RZ/V2H(P) */
> >>>> @@ -257,6 +261,7 @@ static const struct pin_config_item renesas_rzv2h_conf_items[] = {
> >>>>     * @oen: OEN register offset
> >>>>     * @qspi: QSPI register offset
> >>>>     * @other_poc: OTHER_POC register offset
> >>>> + * @i3c_set: I3C_SET register offset
> >>>>     */
> >>>>    struct rzg2l_register_offsets {
> >>>>    	u16 pwpr;
> >>>> @@ -265,6 +270,7 @@ struct rzg2l_register_offsets {
> >>>>    	u16 oen;
> >>>>    	u16 qspi;
> >>>>    	u16 other_poc;
> >>>> +	u16 i3c_set;
> >>>
> >>>
> >>>>    };
> >>>>
> >>>>    /**
> >>>> @@ -272,6 +278,7 @@ struct rzg2l_register_offsets {
> >>>>     * @other_poc_pvdd1833_oth_awo_poc: PVDD1833_OTH_AWO_POC mask
> >>>>     * @other_poc_pvdd1833_oth_iso_poc: PVDD1833_OTH_ISO_POC mask
> >>>>     * @other_poc_wdtovf_n_poc: WDTOVF_N_POC mask
> >>>> + * @i3c_set_poc: I3C_SET_POC mask
> >>>>     */
> >>>>    struct rzg2l_register_masks {
> >>>>    	union {
> >>>> @@ -281,6 +288,11 @@ struct rzg2l_register_masks {
> >>>>    			u8 other_poc_pvdd1833_oth_iso_poc;
> >>>>    			u8 other_poc_wdtovf_n_poc;
> >>>>    		};
> >>>> +
> >>>> +		/* RZ/G3S masks */
> >>>> +		struct {
> >>>> +			u8 i3c_set_poc;
> >>>
> >>> How this POC is different from Ethernet, SDHI and XSPI POC?
> >>
> >> Different bit mask and offset for I3C SET_POC compared with ETH, SDHI, XSPI.
> >
> > RZ/G3L has i3c_set_poc, which has same bitmask as other_poc_wdtovf_n_poc.
> > Maybe create register specific masks??
> >
> > struct other_poc and struct i3c_set instead of union. So that both
> > RZ/G3L and RZ/G3S can share the same struct for i3c.
> 
> When RZ/G3L I3C POC support will be added the i3c_set_poc member of struct rzg2l_register_masks could be
> moved as common member:
> 
> Current code base allows for this extension. You can have:

> 
> struct rzg2l_register_masks {
> +       /* Common masks. */
> +       u8 i3c_set_poc;
>          union {

OK, This union will go when we add RZ/G3L.

>                  /* RZ/G3L masks */
>                  struct {
>                          u8 other_poc_pvdd1833_oth_awo_poc;
>                          u8 other_poc_pvdd1833_oth_iso_poc;
>                          u8 other_poc_wdtovf_n_poc;
>                  };
> -               /* RZ/G3S masks */
> -               struct {

Looks, this struct not needed now. struct with single member
has no value at all.

> -                       u8 i3c_set_poc;
> -               };
>          };
> };
> 
> // ...
> 
> const struct rzg2l_hwcfg rzg3l_hwcfg = {
>          // ...
> 
>          .masks = {
>                  .other_poc_pvdd1833_oth_awo_poc = BIT(0),
>                  .other_poc_pvdd1833_oth_iso_poc = BIT(1),
>                  .other_poc_wdtovf_n_poc = BIT(2),
> +               .i3c_set_poc = BIT(x),
			.i3c_set_poc = BIT(2),

Cheers,
Biju

>          },
> 
>          // ...
> };
> 
> The rest of configuration and initialization code remains the same.
> 
> Thank you,
> Claudiu

Re: [PATCH v4 4/5] pinctrl: renesas: rzg2l: Add RZ/G3S support for selecting the I3C power source

[Claudiu Beznea]

On 7/13/26 18:15, Biju Das wrote:
> Hi Claudiu,
> 
>> -----Original Message-----
>> From: claudiu beznea<claudiu.beznea@tuxon.dev>
>> Sent: 13 July 2026 15:57
>> Subject: Re: [PATCH v4 4/5] pinctrl: renesas: rzg2l: Add RZ/G3S support for selecting the I3C power
>> source
>>
>>
>>
>> On 7/13/26 16:56, Biju Das wrote:
>>> Hi Claudiu,
>>>
>>>> -----Original Message-----
>>>> From: claudiu beznea<claudiu.beznea@tuxon.dev>
>>>> Sent: 13 July 2026 14:19
>>>> Subject: Re: [PATCH v4 4/5] pinctrl: renesas: rzg2l: Add RZ/G3S
>>>> support for selecting the I3C power source
>>>>
>>>> Hi, Biju,
>>>>
>>>> On 7/12/26 17:55, Biju Das wrote:
>>>>> Hi Claudiu,
>>>>>
>>>>> Thanks for the patch.
>>>>>
>>>>>> -----Original Message-----
>>>>>> From: Claudiu Beznea<claudiu.beznea+renesas@tuxon.dev>
>>>>>> Sent: 10 July 2026 12:37
>>>>>> Subject: [PATCH v4 4/5] pinctrl: renesas: rzg2l: Add RZ/G3S support
>>>>>> for selecting the I3C power source
>>>>>>
>>>>>> From: Claudiu Beznea<claudiu.beznea.uj@bp.renesas.com>
>>>>>>
>>>>>> The Renesas RZ/G3S I3C pins can be powered at either 1.8V or 1.2V.
>>>>>> The pin controller provides a register to select between these two options.
>>>>>> Update the Renesas RZ/G2L pin controller driver to allow selecting the I3C power source on RZ/G3S
>> SoC.
>>>>>> Reviewed-by: Wolfram Sang<wsa+renesas@sang-engineering.com>
>>>>>> Tested-by: Wolfram Sang<wsa+renesas@sang-engineering.com>
>>>>>> Signed-off-by: Claudiu Beznea<claudiu.beznea.uj@bp.renesas.com>
>>>>>> ---
>>>>>>
>>>>>> Changes in v4:
>>>>>> - none
>>>>>>
>>>>>> Changes in v3:
>>>>>> - collected tags
>>>>>>
>>>>>> Changes in v2:
>>>>>> - none
>>>>>>
>>>>>>     drivers/pinctrl/renesas/pinctrl-rzg2l.c | 73 +++++++++++++++++++++++--
>>>>>>     1 file changed, 68 insertions(+), 5 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>>>>>> b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>>>>>> index b52a85066f63..9a0706fea220 100644
>>>>>> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>>>>>> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>>>>>> @@ -69,6 +69,7 @@
>>>>>>     #define PIN_CFG_PVDD1833_OTH_AWO_POC	BIT(19) /* known on RZ/G3L only */
>>>>>>     #define PIN_CFG_PVDD1833_OTH_ISO_POC	BIT(20) /* known on RZ/G3L only */
>>>>>>     #define PIN_CFG_WDTOVF_N_POC		BIT(21) /* known on RZ/G3L only */
>>>>>> +#define PIN_CFG_IO_VMC_I3C		BIT(22)
>>>>>>
>>>>>>     #define RZG2L_SINGLE_PIN		BIT_ULL(63)	/* Dedicated pin */
>>>>>>     #define RZG2L_VARIABLE_CFG		BIT_ULL(62)	/* Variable cfg for port pins */
>>>>>> @@ -186,6 +187,9 @@
>>>>>>     #define PVDD_3300		0	/* I/O domain voltage >= 3.3V */
>>>>>>     #define PVDD_MASK		0x3
>>>>>>
>>>>>> +#define PVDD_I3C_1200		1	/* I3C I/O domain voltage 1.2V */
>>>>>> +#define PVDD_I3C_1800		0	/* I3C I/O domain voltage 1.8V */
>>>>>> +
>>>>>>     #define PWPR_B0WI		BIT(7)	/* Bit Write Disable */
>>>>>>     #define PWPR_PFCWE		BIT(6)	/* PFC Register Write Enable */
>>>>>>     #define PWPR_REGWE_A		BIT(6)	/* PFC and PMC Register Write Enable on RZ/V2H(P) */
>>>>>> @@ -257,6 +261,7 @@ static const struct pin_config_item renesas_rzv2h_conf_items[] = {
>>>>>>      * @oen: OEN register offset
>>>>>>      * @qspi: QSPI register offset
>>>>>>      * @other_poc: OTHER_POC register offset
>>>>>> + * @i3c_set: I3C_SET register offset
>>>>>>      */
>>>>>>     struct rzg2l_register_offsets {
>>>>>>     	u16 pwpr;
>>>>>> @@ -265,6 +270,7 @@ struct rzg2l_register_offsets {
>>>>>>     	u16 oen;
>>>>>>     	u16 qspi;
>>>>>>     	u16 other_poc;
>>>>>> +	u16 i3c_set;
>>>>>
>>>>>>     };
>>>>>>
>>>>>>     /**
>>>>>> @@ -272,6 +278,7 @@ struct rzg2l_register_offsets {
>>>>>>      * @other_poc_pvdd1833_oth_awo_poc: PVDD1833_OTH_AWO_POC mask
>>>>>>      * @other_poc_pvdd1833_oth_iso_poc: PVDD1833_OTH_ISO_POC mask
>>>>>>      * @other_poc_wdtovf_n_poc: WDTOVF_N_POC mask
>>>>>> + * @i3c_set_poc: I3C_SET_POC mask
>>>>>>      */
>>>>>>     struct rzg2l_register_masks {
>>>>>>     	union {
>>>>>> @@ -281,6 +288,11 @@ struct rzg2l_register_masks {
>>>>>>     			u8 other_poc_pvdd1833_oth_iso_poc;
>>>>>>     			u8 other_poc_wdtovf_n_poc;
>>>>>>     		};
>>>>>> +
>>>>>> +		/* RZ/G3S masks */
>>>>>> +		struct {
>>>>>> +			u8 i3c_set_poc;
>>>>> How this POC is different from Ethernet, SDHI and XSPI POC?
>>>> Different bit mask and offset for I3C SET_POC compared with ETH, SDHI, XSPI.
>>> RZ/G3L has i3c_set_poc, which has same bitmask as other_poc_wdtovf_n_poc.
>>> Maybe create register specific masks??
>>>
>>> struct other_poc and struct i3c_set instead of union. So that both
>>> RZ/G3L and RZ/G3S can share the same struct for i3c.
>> When RZ/G3L I3C POC support will be added the i3c_set_poc member of struct rzg2l_register_masks could be
>> moved as common member:
>>
>> Current code base allows for this extension. You can have:
>> struct rzg2l_register_masks {
>> +       /* Common masks. */
>> +       u8 i3c_set_poc;
>>           union {
> OK, This union will go when we add RZ/G3L.
> 
>>                   /* RZ/G3L masks */
>>                   struct {
>>                           u8 other_poc_pvdd1833_oth_awo_poc;
>>                           u8 other_poc_pvdd1833_oth_iso_poc;
>>                           u8 other_poc_wdtovf_n_poc;
>>                   };
>> -               /* RZ/G3S masks */
>> -               struct {
> Looks, this struct not needed now. struct with single member
> has no value at all.

I'll let Geert decide if he wants me to drop it.

Thank you,
Claudiu