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From: Inochi Amaoto <inochiama@gmail.com>
To: Chen-Yu Yeh <chenyou910331@gmail.com>,
	 Chen Wang <unicorn_wang@outlook.com>,
	Inochi Amaoto <inochiama@gmail.com>
Cc: Inochi Amaoto <inochiama@outlook.com>,
	Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	 Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 Albert Ou <aou@eecs.berkeley.edu>,
	devicetree@vger.kernel.org, sophgo@lists.linux.dev,
	 linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 2/3] riscv: dts: sophgo: cv180x: Add PWR_GPIO controller
Date: Mon, 13 Jul 2026 08:56:41 +0800	[thread overview]
Message-ID: <alQ3mqUPItCP2CVT@inochi.infowork> (raw)
In-Reply-To: <20260710075917.159969-3-chenyou910331@gmail.com>

On Fri, Jul 10, 2026 at 03:59:16PM +0800, Chen-Yu Yeh wrote:
> The CV180x/CV181x family has an additional DesignWare APB GPIO
> controller (PWR_GPIO) located in the always-on power domain at
> 0x5021000. Add the node so that boards can reference GPIOs in this
> bank, such as status LEDs.
> 
> Signed-off-by: Chen-Yu Yeh <chenyou910331@gmail.com>
> ---
> The base address and interrupt number match the vendor SDK device
> tree (cv181x_base_riscv.dtsi: gpio@05021000, PLIC interrupt 70,
> i.e. SOC_PERIPHERAL_IRQ(54)). Verified on Milk-V Duo 256M hardware
> via the onboard status LED on porte 2.
> 
>  arch/riscv/boot/dts/sophgo/cv180x.dtsi | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> index 06b0ce5a2db7..25ad2bd265d7 100644
> --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> @@ -160,6 +160,24 @@ portd: gpio-controller@0 {
>  			};
>  		};
>  
> +		gpio4: gpio@5021000 {
> +			compatible = "snps,dw-apb-gpio";
> +			reg = <0x5021000 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			porte: gpio-controller@0 {
> +				compatible = "snps,dw-apb-gpio-port";
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				ngpios = <32>;
> +				reg = <0>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				interrupts = <SOC_PERIPHERAL_IRQ(54) IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +

You should follow the device address order. not by the device name.

>  		saradc: adc@30f0000 {
>  			compatible = "sophgo,cv1800b-saradc";
>  			reg = <0x030f0000 0x1000>;
> -- 
> 2.43.0
> 

_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Inochi Amaoto <inochiama@gmail.com>
To: Chen-Yu Yeh <chenyou910331@gmail.com>,
	 Chen Wang <unicorn_wang@outlook.com>,
	Inochi Amaoto <inochiama@gmail.com>
Cc: Inochi Amaoto <inochiama@outlook.com>,
	Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	 Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 Albert Ou <aou@eecs.berkeley.edu>,
	devicetree@vger.kernel.org, sophgo@lists.linux.dev,
	 linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 2/3] riscv: dts: sophgo: cv180x: Add PWR_GPIO controller
Date: Mon, 13 Jul 2026 08:56:41 +0800	[thread overview]
Message-ID: <alQ3mqUPItCP2CVT@inochi.infowork> (raw)
In-Reply-To: <20260710075917.159969-3-chenyou910331@gmail.com>

On Fri, Jul 10, 2026 at 03:59:16PM +0800, Chen-Yu Yeh wrote:
> The CV180x/CV181x family has an additional DesignWare APB GPIO
> controller (PWR_GPIO) located in the always-on power domain at
> 0x5021000. Add the node so that boards can reference GPIOs in this
> bank, such as status LEDs.
> 
> Signed-off-by: Chen-Yu Yeh <chenyou910331@gmail.com>
> ---
> The base address and interrupt number match the vendor SDK device
> tree (cv181x_base_riscv.dtsi: gpio@05021000, PLIC interrupt 70,
> i.e. SOC_PERIPHERAL_IRQ(54)). Verified on Milk-V Duo 256M hardware
> via the onboard status LED on porte 2.
> 
>  arch/riscv/boot/dts/sophgo/cv180x.dtsi | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> index 06b0ce5a2db7..25ad2bd265d7 100644
> --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> @@ -160,6 +160,24 @@ portd: gpio-controller@0 {
>  			};
>  		};
>  
> +		gpio4: gpio@5021000 {
> +			compatible = "snps,dw-apb-gpio";
> +			reg = <0x5021000 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			porte: gpio-controller@0 {
> +				compatible = "snps,dw-apb-gpio-port";
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				ngpios = <32>;
> +				reg = <0>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				interrupts = <SOC_PERIPHERAL_IRQ(54) IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +

You should follow the device address order. not by the device name.

>  		saradc: adc@30f0000 {
>  			compatible = "sophgo,cv1800b-saradc";
>  			reg = <0x030f0000 0x1000>;
> -- 
> 2.43.0
> 

  parent reply	other threads:[~2026-07-13  0:58 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-10  7:59 [PATCH v3 0/3] riscv: dts: sophgo: Add Milk-V Duo 256M board support Chen-Yu Yeh
2026-07-10  7:59 ` Chen-Yu Yeh
2026-07-10  7:59 ` [PATCH v3 1/3] dt-bindings: soc: sophgo: add Milk-V Duo 256M board Chen-Yu Yeh
2026-07-10  7:59   ` Chen-Yu Yeh
2026-07-10 16:41   ` Conor Dooley
2026-07-10 16:41     ` Conor Dooley
2026-07-10  7:59 ` [PATCH v3 2/3] riscv: dts: sophgo: cv180x: Add PWR_GPIO controller Chen-Yu Yeh
2026-07-10  7:59   ` Chen-Yu Yeh
2026-07-10  8:06   ` sashiko-bot
2026-07-13  0:56   ` Inochi Amaoto [this message]
2026-07-13  0:56     ` Inochi Amaoto
2026-07-13  1:56     ` 葉宸佑
2026-07-13  1:56       ` 葉宸佑
2026-07-10  7:59 ` [PATCH v3 3/3] riscv: dts: sophgo: Add Milk-V Duo 256M board support Chen-Yu Yeh
2026-07-10  7:59   ` Chen-Yu Yeh
2026-07-10  8:12   ` sashiko-bot

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