From: Chao Liu <chao.liu.zevorn@gmail.com>
To: Max Chou <max.chou@sifive.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Daniel Henrique Barboza" <daniel.barboza@oss.qualcomm.com>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Weiwei Li" <liwei1518@gmail.com>,
"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>
Subject: Re: [PATCH v6 1/9] fpu: Fix biased exponent write in parts_float_to_e5m2 saturate path
Date: Wed, 22 Jul 2026 10:38:23 +0800 [thread overview]
Message-ID: <amAtFXK9m1LXFPM-@ChaodeMacBook-Pro.local> (raw)
In-Reply-To: <20260708161859.1124848-2-max.chou@sifive.com>
On Thu, Jul 09, 2026 at 12:18:51AM +0800, Max Chou wrote:
> FloatParts64.exp holds an unbiased exponent. Subtract exp_bias to store
> the unbiased equivalent of the max-normal biased exponent.
>
> Fixes: d8be49537658 ("fpu: Add conversion routines for OCP FP8 E5M2")
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>
Thanks,
Chao
> ---
> fpu/softfloat.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/fpu/softfloat.c b/fpu/softfloat.c
> index bc244a44ff..e2e53c1d68 100644
> --- a/fpu/softfloat.c
> +++ b/fpu/softfloat.c
> @@ -2435,7 +2435,8 @@ static void parts_float_to_e5m2(FloatParts64 *a, float_status *s, bool saturate)
> /* Per OCP, conversion in SATURATE mode bounds Inf to MAX. */
> if (saturate) {
> a->cls = float_class_normal;
> - a->exp = float8_e5m2_params.exp_max - 1;
> + a->exp = (float8_e5m2_params.exp_max - 1 -
> + float8_e5m2_params.exp_bias);
> a->frac = MAKE_64BIT_MASK(float8_e5m2_params.frac_shift,
> float8_e5m2_params.frac_size + 1);
> }
> --
> 2.55.0
>
next prev parent reply other threads:[~2026-07-22 2:38 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-08 16:18 [PATCH v6 0/9] target/riscv: Add RISC-V Zvfofp8min extension support Max Chou
2026-07-08 16:18 ` [PATCH v6 1/9] fpu: Fix biased exponent write in parts_float_to_e5m2 saturate path Max Chou
2026-07-22 2:38 ` Chao Liu [this message]
2026-07-08 16:18 ` [PATCH v6 2/9] target/riscv: rvv: Fix NOP_UU_B vs2 width Max Chou
2026-07-08 16:18 ` [PATCH v6 3/9] target/riscv: Add cfg property for Zvfofp8min extension Max Chou
2026-07-08 16:18 ` [PATCH v6 4/9] target/riscv: Add implied rules " Max Chou
2026-07-08 16:18 ` [PATCH v6 5/9] target/riscv: rvv: Make vfwcvtbf16.f.f.v support OFP8 to BF16 conversion " Max Chou
2026-07-08 16:18 ` [PATCH v6 6/9] target/riscv: rvv: Make vfncvtbf16.f.f.w support BF16 to OFP8 " Max Chou
2026-07-08 16:18 ` [PATCH v6 7/9] target/riscv: rvv: Add vfncvtbf16.sat.f.f.w instruction " Max Chou
2026-07-08 16:18 ` [PATCH v6 8/9] target/riscv: rvv: Add vfncvt.f.f.q and vfncvt.sat.f.f.q instructions " Max Chou
2026-07-08 16:18 ` [PATCH v6 9/9] disas/riscv: Add support of " Max Chou
2026-07-20 7:25 ` [PATCH v6 0/9] target/riscv: Add RISC-V Zvfofp8min extension support Max Chou
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