* [PATCH 0/3] riscv: Add K230 DDR controller and PHY models
@ 2026-07-16 13:24 Junze Cao
2026-07-16 13:24 ` [PATCH 1/3] hw/misc: " Junze Cao
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Junze Cao @ 2026-07-16 13:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, chao.liu, pierrick.bouvier, palmer, alistair.francis,
liwei1518, daniel.barboza, zhiwei_liu, farosas, lvivier, pbonzini,
Junze Cao
The K230 SDK U-Boot SPL initializes DRAM by programming the DDRC CFG
and DDR PHY MMIO regions. The k230 machine currently exposes the DDR
configuration region as unimplemented and does not provide the PHY, so
the SPL cannot complete the training and DFI handshakes.
Add minimal models for the register behavior exercised by the SDK SPL.
The controller model provides reset values, register access policy, DFI
and software-update handshakes, and the Init-to-Normal transition. The
PHY model provides CSR ownership, the training mailbox, and DFI
completion. Wire both devices into the k230 machine and document the
resulting SPL support.
These device models allow firmware to complete the DDR initialization
sequence.
Testing performed:
* scripts/checkpatch.pl --branch upstream/master..HEAD
* meson test -C build --print-errorlogs
qemu:qtest-riscv64/k230-ddr-test (6 subtests passed)
* Booted the K230 SDK U-Boot SPL through DDR initialization to its SPI
boot path
Junze Cao (3):
hw/misc: Add K230 DDR controller and PHY models
hw/riscv: Connect K230 DDR controller and PHY models
tests/qtest: Add K230 DDR controller tests
MAINTAINERS | 3 +
docs/system/riscv/k230.rst | 4 +
hw/misc/k230_ddr.c | 544 ++++++++++++++++++++++++++++++++++++
hw/misc/meson.build | 1 +
hw/riscv/k230.c | 19 +-
include/hw/misc/k230_ddr.h | 59 ++++
include/hw/riscv/k230.h | 4 +
tests/qtest/k230-ddr-test.c | 226 +++++++++++++++
tests/qtest/meson.build | 3 +-
9 files changed, 859 insertions(+), 4 deletions(-)
create mode 100644 hw/misc/k230_ddr.c
create mode 100644 include/hw/misc/k230_ddr.h
create mode 100644 tests/qtest/k230-ddr-test.c
base-commit: eca2c16212ef9dcb0871de39bb9d1c2efebe76be
--
2.53.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 1/3] hw/misc: Add K230 DDR controller and PHY models 2026-07-16 13:24 [PATCH 0/3] riscv: Add K230 DDR controller and PHY models Junze Cao @ 2026-07-16 13:24 ` Junze Cao 2026-07-22 20:06 ` Daniel Henrique Barboza 2026-07-23 8:41 ` Chao Liu 2026-07-16 13:24 ` [PATCH 2/3] hw/riscv: Connect " Junze Cao 2026-07-16 13:24 ` [PATCH 3/3] tests/qtest: Add K230 DDR controller tests Junze Cao 2 siblings, 2 replies; 10+ messages in thread From: Junze Cao @ 2026-07-16 13:24 UTC (permalink / raw) To: qemu-devel Cc: qemu-riscv, chao.liu, pierrick.bouvier, palmer, alistair.francis, liwei1518, daniel.barboza, zhiwei_liu, farosas, lvivier, pbonzini, Junze Cao The K230 SDK U-Boot SPL programs K230 DDRC CFG and K230 DDR PHY registers before DRAM can be used. Add separate SysBus devices for both register ranges. Model controller reset values, DFI and software-update handshakes. For the PHY, model register ownership, the training mailbox, and DFI completion. Include migration state for both devices. Signed-off-by: Junze Cao <caojunze424@gmail.com> --- MAINTAINERS | 2 + hw/misc/k230_ddr.c | 544 +++++++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + include/hw/misc/k230_ddr.h | 59 ++++ 4 files changed, 606 insertions(+) create mode 100644 hw/misc/k230_ddr.c create mode 100644 include/hw/misc/k230_ddr.h diff --git a/MAINTAINERS b/MAINTAINERS index ecb8cfdc41..1cb3ef6c02 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1826,8 +1826,10 @@ M: Chao Liu <chao.liu@processmission.com> L: qemu-riscv@nongnu.org S: Maintained F: docs/system/riscv/k230.rst +F: hw/misc/k230_ddr.c F: hw/riscv/k230.c F: hw/watchdog/k230_wdt.c +F: include/hw/misc/k230_ddr.h F: include/hw/riscv/k230.h F: include/hw/watchdog/k230_wdt.h F: tests/functional/riscv64/test_k230.py diff --git a/hw/misc/k230_ddr.c b/hw/misc/k230_ddr.c new file mode 100644 index 0000000000..9ff2714e34 --- /dev/null +++ b/hw/misc/k230_ddr.c @@ -0,0 +1,544 @@ +/* + * Kendryte K230 DDR controller and PHY models + * + * Models the K230 DDRC CFG registers and K230 DDR PHY registers exercised + * by the K230 SDK U-Boot SPL. + * + * Copyright (c) 2026 Junze Cao <caojunze424@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/module.h" +#include "migration/vmstate.h" +#include "hw/core/registerfields.h" +#include "hw/core/resettable.h" +#include "hw/misc/k230_ddr.h" + +/* DDRC CFG registers */ + +enum K230DDRCOperatingMode { + K230_DDRC_MODE_INIT = 0, + K230_DDRC_MODE_NORMAL = 1, +}; + +REG32(K230_DDRC_MSTR, 0x000) + +REG32(K230_DDRC_STAT, 0x004) + FIELD(K230_DDRC_STAT, OPERATING_MODE, 0, 3) + +REG32(K230_DDRC_PWRCTL, 0x030) + +REG32(K230_DDRC_RFSHCTL0, 0x050) + +REG32(K230_DDRC_RFSHTMG, 0x064) + +REG32(K230_DDRC_RFSHTMG1, 0x068) + +REG32(K230_DDRC_INIT0, 0x0d0) + +REG32(K230_DDRC_INIT2, 0x0d8) + +REG32(K230_DDRC_INIT3, 0x0dc) + +REG32(K230_DDRC_INIT5, 0x0e4) + +REG32(K230_DDRC_DRAMTMG0, 0x100) +#define R_K230_DDRC_DRAMTMG(index) \ + (R_K230_DDRC_DRAMTMG0 + (index)) + +REG32(K230_DDRC_ZQCTL0, 0x180) + +REG32(K230_DDRC_ZQCTL1, 0x184) + +REG32(K230_DDRC_ZQCTL2, 0x188) + +REG32(K230_DDRC_ZQSTAT, 0x18c) + +REG32(K230_DDRC_DFITMG0, 0x190) + +REG32(K230_DDRC_DFITMG1, 0x194) + +REG32(K230_DDRC_DFIUPD0, 0x1a0) + +REG32(K230_DDRC_DFIUPD1, 0x1a4) + +REG32(K230_DDRC_DFIUPD2, 0x1a8) + +REG32(K230_DDRC_DFIMISC, 0x1b0) + FIELD(K230_DDRC_DFIMISC, DFI_INIT_COMPLETE_EN, 0, 1) + FIELD(K230_DDRC_DFIMISC, DFI_INIT_START, 5, 1) + +REG32(K230_DDRC_DFITMG2, 0x1b4) + +REG32(K230_DDRC_DFISTAT, 0x1bc) + FIELD(K230_DDRC_DFISTAT, DFI_INIT_COMPLETE, 0, 1) + +REG32(K230_DDRC_ODTCFG, 0x240) + +REG32(K230_DDRC_SWCTL, 0x320) + FIELD(K230_DDRC_SWCTL, SW_DONE, 0, 1) + +REG32(K230_DDRC_SWSTAT, 0x324) + FIELD(K230_DDRC_SWSTAT, SW_DONE_ACK, 0, 1) + +static const uint32_t k230_ddrc_reset_values[K230_DDRC_REG_COUNT] = { + [R_K230_DDRC_MSTR] = 0x01040000, + [R_K230_DDRC_RFSHCTL0] = 0x00210000, + [R_K230_DDRC_RFSHTMG] = 0x0062008c, + [R_K230_DDRC_RFSHTMG1] = 0x0000008c, + [R_K230_DDRC_INIT0] = 0x0002004e, + [R_K230_DDRC_INIT3] = 0x00000510, + [R_K230_DDRC_INIT5] = 0x00100000, + [R_K230_DDRC_DRAMTMG(0)] = 0x0f101b0f, + [R_K230_DDRC_DRAMTMG(1)] = 0x00080414, + [R_K230_DDRC_DRAMTMG(2)] = 0x0305060d, + [R_K230_DDRC_DRAMTMG(3)] = 0x00004000, + [R_K230_DDRC_DRAMTMG(4)] = 0x05040405, + [R_K230_DDRC_DRAMTMG(5)] = 0x05050403, + [R_K230_DDRC_DRAMTMG(6)] = 0x02020005, + [R_K230_DDRC_DRAMTMG(7)] = 0x00000202, + [R_K230_DDRC_DRAMTMG(8)] = 0x03034405, + [R_K230_DDRC_DRAMTMG(9)] = 0x0004040d, + [R_K230_DDRC_DRAMTMG(10)] = 0x001c180a, + [R_K230_DDRC_DRAMTMG(11)] = 0x440c021c, + [R_K230_DDRC_DRAMTMG(12)] = 0x00020610, + [R_K230_DDRC_DRAMTMG(13)] = 0x1c200004, + [R_K230_DDRC_DRAMTMG(14)] = 0x000000a0, + [R_K230_DDRC_DRAMTMG(16)] = 0x05100404, + [R_K230_DDRC_ZQCTL0] = 0x02000040, + [R_K230_DDRC_ZQCTL1] = 0x02000100, + [R_K230_DDRC_DFITMG0] = 0x07020002, + [R_K230_DDRC_DFITMG1] = 0x00000404, + [R_K230_DDRC_DFIUPD0] = 0x00400003, + [R_K230_DDRC_DFIUPD1] = 0x00010001, + [R_K230_DDRC_DFIUPD2] = 0x80000000, + [R_K230_DDRC_DFIMISC] = 0x00000001, + [R_K230_DDRC_DFITMG2] = 0x00000202, + [R_K230_DDRC_ODTCFG] = 0x04000400, + [R_K230_DDRC_SWCTL] = 0x00000001, + [R_K230_DDRC_SWSTAT] = 0x00000001, +}; + +/* K230 DDR PHY CSRs use byte offset = CSR index * 4. */ +#define K230_DDR_PHY_CSR_OFFSET(index) ((index) * 4) +#define K230_DDR_PHY_MASTER_CSR(reg) \ + K230_DDR_PHY_CSR_OFFSET(0x20000 + (reg)) +#define K230_DDR_PHY_APBONLY_CSR(reg) \ + K230_DDR_PHY_CSR_OFFSET(0xd0000 + (reg)) + +#define K230_DDR_PHY_ATX_IMPEDANCE_RESET UINT32_C(0x03ff) + +REG32(K230_DDR_PHY_MICRO_CONT_MUX_SEL, + K230_DDR_PHY_APBONLY_CSR(0x000)) + FIELD(K230_DDR_PHY_MICRO_CONT_MUX_SEL, MICRO_CONT_MUX_SEL, 0, 1) + +REG32(K230_DDR_PHY_TRAINING_STATUS, + K230_DDR_PHY_APBONLY_CSR(0x004)) + FIELD(K230_DDR_PHY_TRAINING_STATUS, MAILBOX_EMPTY, 0, 1) + +REG32(K230_DDR_PHY_TRAINING_ACK, + K230_DDR_PHY_APBONLY_CSR(0x031)) + +REG32(K230_DDR_PHY_TRAINING_MESSAGE, + K230_DDR_PHY_APBONLY_CSR(0x032)) + +REG32(K230_DDR_PHY_TRAINING_TRIGGER, + K230_DDR_PHY_APBONLY_CSR(0x099)) + +#define K230_DDR_PHY_TX_IMPEDANCE_CTRL1_RESET UINT32_C(0x0fff) + +REG32(K230_DDR_PHY_DFI_INIT_COMPLETE, + K230_DDR_PHY_MASTER_CSR(0x0f9)) + FIELD(K230_DDR_PHY_DFI_INIT_COMPLETE, DFI_INIT_COMPLETE, 0, 1) + +REG32(K230_DDR_PHY_VREF_IN_GLOBAL, + K230_DDR_PHY_MASTER_CSR(0x0b2)) +#define K230_DDR_PHY_VREF_IN_GLOBAL_RESET UINT32_C(0x0200) + +static void k230_ddr_cfg_update_state(K230DDRCfgState *s) +{ + bool dfi_complete = false; + unsigned int operating_mode = K230_DDRC_MODE_INIT; + + if (s->phy) { + dfi_complete = FIELD_EX32(s->phy->dfi_init_complete, + K230_DDR_PHY_DFI_INIT_COMPLETE, + DFI_INIT_COMPLETE); + } + + ARRAY_FIELD_DP32(s->regs, K230_DDRC_DFISTAT, + DFI_INIT_COMPLETE, dfi_complete); + ARRAY_FIELD_DP32(s->regs, K230_DDRC_SWSTAT, SW_DONE_ACK, + ARRAY_FIELD_EX32(s->regs, K230_DDRC_SWCTL, SW_DONE)); + + if (dfi_complete && + ARRAY_FIELD_EX32(s->regs, K230_DDRC_DFIMISC, + DFI_INIT_COMPLETE_EN)) { + s->initialized = true; + } + + if (s->initialized) { + operating_mode = K230_DDRC_MODE_NORMAL; + } + + ARRAY_FIELD_DP32(s->regs, K230_DDRC_STAT, + OPERATING_MODE, operating_mode); +} + +static uint64_t k230_ddr_cfg_read(void *opaque, hwaddr addr, unsigned int size) +{ + K230DDRCfgState *s = opaque; + uint64_t value = 0; + + if (addr < K230_DDRC_REG_SIZE) { + k230_ddr_cfg_update_state(s); + value = s->regs[addr / sizeof(uint32_t)]; + } + + return value; +} + +static void k230_ddr_cfg_write(void *opaque, hwaddr addr, uint64_t value, + unsigned int size) +{ + K230DDRCfgState *s = opaque; + uint32_t val = value; + + if (addr >= K230_DDRC_REG_SIZE) { + return; + } + + switch (addr) { + case A_K230_DDRC_STAT: + case A_K230_DDRC_DFISTAT: + case A_K230_DDRC_ZQSTAT: + case A_K230_DDRC_SWSTAT: + return; + case A_K230_DDRC_PWRCTL: + s->regs[R_K230_DDRC_PWRCTL] = val & MAKE_64BIT_MASK(0, 9); + break; + case A_K230_DDRC_ZQCTL2: + /* ZQ reset completes immediately and the W1S bit self-clears. */ + s->regs[R_K230_DDRC_ZQCTL2] = 0; + s->regs[R_K230_DDRC_ZQSTAT] = 0; + break; + case A_K230_DDRC_DFIMISC: + s->regs[R_K230_DDRC_DFIMISC] = + val & (MAKE_64BIT_MASK(0, 6) | MAKE_64BIT_MASK(8, 5)); + if (s->phy && s->phy->training_complete && + FIELD_EX32(val, K230_DDRC_DFIMISC, DFI_INIT_START)) { + s->phy->dfi_init_complete = FIELD_DP32( + s->phy->dfi_init_complete, + K230_DDR_PHY_DFI_INIT_COMPLETE, DFI_INIT_COMPLETE, 1); + } + break; + case A_K230_DDRC_SWCTL: + s->regs[R_K230_DDRC_SWCTL] = + val & R_K230_DDRC_SWCTL_SW_DONE_MASK; + break; + default: + s->regs[addr / sizeof(uint32_t)] = val; + break; + } + + k230_ddr_cfg_update_state(s); +} + +static bool k230_ddr_phy_decode_anib(hwaddr addr, unsigned int *anib) +{ + uint32_t csr = addr / sizeof(uint32_t); + + if ((csr & 0xfff) != 0x043) { + return false; + } + + *anib = csr >> 12; + return *anib < K230_DDR_PHY_ANIB_COUNT; +} + +static bool k230_ddr_phy_decode_dbyte(hwaddr addr, uint32_t reg, + unsigned int *dbyte, + unsigned int *nibble) +{ + uint32_t csr = addr / sizeof(uint32_t); + uint32_t block_offset; + + if (csr < 0x10000) { + return false; + } + + csr -= 0x10000; + *dbyte = csr >> 12; + if (*dbyte >= K230_DDR_PHY_DBYTE_COUNT) { + return false; + } + + block_offset = csr & 0xfff; + *nibble = block_offset >> 8; + return *nibble < K230_DDR_PHY_NIBBLES_PER_DBYTE && + (block_offset & 0xff) == reg; +} + +static uint64_t k230_ddr_phy_read(void *opaque, hwaddr addr, + unsigned int size) +{ + K230DDRPhyState *s = opaque; + unsigned int dbyte; + unsigned int nibble; + unsigned int anib; + uint64_t value = 0; + + switch (addr) { + case A_K230_DDR_PHY_MICRO_CONT_MUX_SEL: + value = s->micro_cont_mux_sel; + break; + case A_K230_DDR_PHY_TRAINING_STATUS: + value = s->mailbox_message_pending ? 0 : + R_K230_DDR_PHY_TRAINING_STATUS_MAILBOX_EMPTY_MASK; + break; + case A_K230_DDR_PHY_TRAINING_MESSAGE: + value = s->training_complete ? 0x07 : 0; + break; + case A_K230_DDR_PHY_TRAINING_ACK: + case A_K230_DDR_PHY_TRAINING_TRIGGER: + break; + case A_K230_DDR_PHY_DFI_INIT_COMPLETE: + value = s->dfi_init_complete; + break; + case A_K230_DDR_PHY_VREF_IN_GLOBAL: + value = s->vref_in_global; + break; + default: + if (k230_ddr_phy_decode_anib(addr, &anib)) { + value = s->atx_impedance[anib]; + } else if (k230_ddr_phy_decode_dbyte(addr, 0x049, + &dbyte, &nibble)) { + value = s->tx_impedance_ctrl1[dbyte][nibble]; + } else if (k230_ddr_phy_decode_dbyte(addr, 0x04d, + &dbyte, &nibble)) { + value = s->tx_odt_drv_stren[dbyte][nibble]; + } + break; + } + + return value; +} + +static void k230_ddr_phy_write(void *opaque, hwaddr addr, uint64_t value, + unsigned int size) +{ + K230DDRPhyState *s = opaque; + uint16_t val = value; + unsigned int dbyte; + unsigned int nibble; + unsigned int anib; + + switch (addr) { + case A_K230_DDR_PHY_MICRO_CONT_MUX_SEL: + s->micro_cont_mux_sel = + val & R_K230_DDR_PHY_MICRO_CONT_MUX_SEL_MICRO_CONT_MUX_SEL_MASK; + return; + case A_K230_DDR_PHY_TRAINING_STATUS: + case A_K230_DDR_PHY_TRAINING_MESSAGE: + return; + case A_K230_DDR_PHY_TRAINING_ACK: + if (val == 0) { + s->mailbox_message_pending = false; + } + return; + case A_K230_DDR_PHY_TRAINING_TRIGGER: + if (val != 0) { + s->training_trigger_seen = true; + } else if (s->training_trigger_seen) { + /* Abstract the loaded firmware run to its final mailbox message. */ + s->training_trigger_seen = false; + s->training_complete = true; + s->mailbox_message_pending = true; + } + return; + default: + break; + } + + if (FIELD_EX32(s->micro_cont_mux_sel, + K230_DDR_PHY_MICRO_CONT_MUX_SEL, + MICRO_CONT_MUX_SEL)) { + return; + } + + switch (addr) { + case A_K230_DDR_PHY_DFI_INIT_COMPLETE: + s->dfi_init_complete = + val & R_K230_DDR_PHY_DFI_INIT_COMPLETE_DFI_INIT_COMPLETE_MASK; + return; + case A_K230_DDR_PHY_VREF_IN_GLOBAL: + s->vref_in_global = val & UINT16_C(0x7fff); + return; + default: + break; + } + + if (k230_ddr_phy_decode_anib(addr, &anib)) { + s->atx_impedance[anib] = val & UINT16_C(0x03ff); + return; + } + + if (k230_ddr_phy_decode_dbyte(addr, 0x049, &dbyte, &nibble)) { + s->tx_impedance_ctrl1[dbyte][nibble] = val & UINT16_C(0x0fff); + return; + } + + if (k230_ddr_phy_decode_dbyte(addr, 0x04d, &dbyte, &nibble)) { + s->tx_odt_drv_stren[dbyte][nibble] = val & UINT16_C(0x0fff); + } +} + +static const MemoryRegionOps k230_ddr_cfg_ops = { + .read = k230_ddr_cfg_read, + .write = k230_ddr_cfg_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + .unaligned = false, + }, +}; + +static const MemoryRegionOps k230_ddr_phy_ops = { + .read = k230_ddr_phy_read, + .write = k230_ddr_phy_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + .unaligned = false, + }, +}; + +static void k230_ddr_cfg_init(Object *obj) +{ + K230DDRCfgState *s = K230_DDR_CFG(obj); + + memory_region_init_io(&s->mmio, obj, &k230_ddr_cfg_ops, s, + "k230-ddr-cfg", K230_DDRC_MMIO_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); +} + +static void k230_ddr_phy_init(Object *obj) +{ + K230DDRPhyState *s = K230_DDR_PHY(obj); + + memory_region_init_io(&s->mmio, obj, &k230_ddr_phy_ops, s, + "k230-ddr-phy", K230_DDR_PHY_MMIO_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); +} + +static void k230_ddr_cfg_reset_enter(Object *obj, ResetType type) +{ + K230DDRCfgState *s = K230_DDR_CFG(obj); + + s->initialized = false; + memcpy(s->regs, k230_ddrc_reset_values, sizeof(s->regs)); +} + +static void k230_ddr_phy_reset_enter(Object *obj, ResetType type) +{ + K230DDRPhyState *s = K230_DDR_PHY(obj); + unsigned int dbyte; + unsigned int nibble; + unsigned int anib; + + memset(s->tx_odt_drv_stren, 0, sizeof(s->tx_odt_drv_stren)); + + for (anib = 0; anib < ARRAY_SIZE(s->atx_impedance); anib++) { + s->atx_impedance[anib] = K230_DDR_PHY_ATX_IMPEDANCE_RESET; + } + + for (dbyte = 0; dbyte < ARRAY_SIZE(s->tx_impedance_ctrl1); dbyte++) { + for (nibble = 0; + nibble < ARRAY_SIZE(s->tx_impedance_ctrl1[dbyte]); nibble++) { + s->tx_impedance_ctrl1[dbyte][nibble] = + K230_DDR_PHY_TX_IMPEDANCE_CTRL1_RESET; + } + } + + s->dfi_init_complete = 0; + s->vref_in_global = K230_DDR_PHY_VREF_IN_GLOBAL_RESET; + s->micro_cont_mux_sel = 0; + s->training_trigger_seen = false; + s->training_complete = false; + s->mailbox_message_pending = false; +} + +static const VMStateDescription vmstate_k230_ddr_cfg = { + .name = "k230-ddr-cfg", + .version_id = 1, + .minimum_version_id = 1, + .fields = (const VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, K230DDRCfgState, K230_DDRC_REG_COUNT), + VMSTATE_BOOL(initialized, K230DDRCfgState), + VMSTATE_END_OF_LIST() + }, +}; + +static const VMStateDescription vmstate_k230_ddr_phy = { + .name = "k230-ddr-phy", + .version_id = 1, + .minimum_version_id = 1, + .fields = (const VMStateField[]) { + VMSTATE_UINT16_ARRAY(atx_impedance, K230DDRPhyState, + K230_DDR_PHY_ANIB_COUNT), + VMSTATE_UINT16_2DARRAY(tx_impedance_ctrl1, K230DDRPhyState, + K230_DDR_PHY_DBYTE_COUNT, + K230_DDR_PHY_NIBBLES_PER_DBYTE), + VMSTATE_UINT16_2DARRAY(tx_odt_drv_stren, K230DDRPhyState, + K230_DDR_PHY_DBYTE_COUNT, + K230_DDR_PHY_NIBBLES_PER_DBYTE), + VMSTATE_UINT16(dfi_init_complete, K230DDRPhyState), + VMSTATE_UINT16(vref_in_global, K230DDRPhyState), + VMSTATE_UINT16(micro_cont_mux_sel, K230DDRPhyState), + VMSTATE_BOOL(training_trigger_seen, K230DDRPhyState), + VMSTATE_BOOL(training_complete, K230DDRPhyState), + VMSTATE_BOOL(mailbox_message_pending, K230DDRPhyState), + VMSTATE_END_OF_LIST() + }, +}; + +static void k230_ddr_cfg_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); + + rc->phases.enter = k230_ddr_cfg_reset_enter; + dc->vmsd = &vmstate_k230_ddr_cfg; +} + +static void k230_ddr_phy_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); + + rc->phases.enter = k230_ddr_phy_reset_enter; + dc->vmsd = &vmstate_k230_ddr_phy; +} + +static const TypeInfo k230_ddr_types[] = { + { + .name = TYPE_K230_DDR_CFG, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(K230DDRCfgState), + .instance_init = k230_ddr_cfg_init, + .class_init = k230_ddr_cfg_class_init, + }, + { + .name = TYPE_K230_DDR_PHY, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(K230DDRPhyState), + .instance_init = k230_ddr_phy_init, + .class_init = k230_ddr_phy_class_init, + }, +}; + +DEFINE_TYPES(k230_ddr_types) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 23265f6035..6d5e2b2647 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -28,6 +28,7 @@ system_ss.add(when: 'CONFIG_IOSB', if_true: files('iosb.c')) system_ss.add(when: 'CONFIG_VIRT_CTRL', if_true: files('virt_ctrl.c')) # RISC-V devices +system_ss.add(when: 'CONFIG_K230', if_true: files('k230_ddr.c')) system_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c')) system_ss.add(when: 'CONFIG_MCHP_PFSOC_IOSCB', if_true: files('mchp_pfsoc_ioscb.c')) system_ss.add(when: 'CONFIG_MCHP_PFSOC_SYSREG', if_true: files('mchp_pfsoc_sysreg.c')) diff --git a/include/hw/misc/k230_ddr.h b/include/hw/misc/k230_ddr.h new file mode 100644 index 0000000000..d912e8e1b0 --- /dev/null +++ b/include/hw/misc/k230_ddr.h @@ -0,0 +1,59 @@ +/* + * Kendryte K230 DDR controller and PHY models + * + * Device state and type declarations for the K230 DDRC CFG and K230 DDR PHY + * registers. + * + * Copyright (c) 2026 Junze Cao <caojunze424@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_MISC_K230_DDR_H +#define HW_MISC_K230_DDR_H + +#include "hw/core/sysbus.h" + +#define K230_DDRC_MMIO_SIZE 0x02000000 +#define K230_DDR_PHY_MMIO_SIZE 0x00400000 + +#define K230_DDRC_REG_SIZE 0x328 +#define K230_DDRC_REG_COUNT (K230_DDRC_REG_SIZE / sizeof(uint32_t)) + +#define K230_DDR_PHY_ANIB_COUNT 10 +#define K230_DDR_PHY_DBYTE_COUNT 4 +#define K230_DDR_PHY_NIBBLES_PER_DBYTE 2 + +#define TYPE_K230_DDR_CFG "riscv.k230.ddr-cfg" +OBJECT_DECLARE_SIMPLE_TYPE(K230DDRCfgState, K230_DDR_CFG) + +#define TYPE_K230_DDR_PHY "riscv.k230.ddr-phy" +OBJECT_DECLARE_SIMPLE_TYPE(K230DDRPhyState, K230_DDR_PHY) + +struct K230DDRCfgState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + K230DDRPhyState *phy; + uint32_t regs[K230_DDRC_REG_COUNT]; + bool initialized; +}; + +struct K230DDRPhyState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + uint16_t atx_impedance[K230_DDR_PHY_ANIB_COUNT]; + uint16_t tx_impedance_ctrl1[K230_DDR_PHY_DBYTE_COUNT] + [K230_DDR_PHY_NIBBLES_PER_DBYTE]; + uint16_t tx_odt_drv_stren[K230_DDR_PHY_DBYTE_COUNT] + [K230_DDR_PHY_NIBBLES_PER_DBYTE]; + uint16_t dfi_init_complete; + uint16_t vref_in_global; + uint16_t micro_cont_mux_sel; + bool training_trigger_seen; + bool training_complete; + bool mailbox_message_pending; +}; + +#endif -- 2.53.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] hw/misc: Add K230 DDR controller and PHY models 2026-07-16 13:24 ` [PATCH 1/3] hw/misc: " Junze Cao @ 2026-07-22 20:06 ` Daniel Henrique Barboza 2026-07-23 8:41 ` Chao Liu 1 sibling, 0 replies; 10+ messages in thread From: Daniel Henrique Barboza @ 2026-07-22 20:06 UTC (permalink / raw) To: Junze Cao, qemu-devel Cc: qemu-riscv, chao.liu, pierrick.bouvier, palmer, alistair.francis, liwei1518, zhiwei_liu, farosas, lvivier, pbonzini Hello, On 7/16/2026 10:24 AM, Junze Cao wrote: > The K230 SDK U-Boot SPL programs K230 DDRC CFG and K230 DDR PHY > registers before DRAM can be used. > > Add separate SysBus devices for both register ranges. Model controller > reset values, DFI and software-update handshakes. For the PHY, model > register ownership, the training mailbox, and DFI completion. > > Include migration state for both devices. > > Signed-off-by: Junze Cao <caojunze424@gmail.com> > --- > MAINTAINERS | 2 + > hw/misc/k230_ddr.c | 544 +++++++++++++++++++++++++++++++++++++ > hw/misc/meson.build | 1 + > include/hw/misc/k230_ddr.h | 59 ++++ > 4 files changed, 606 insertions(+) > create mode 100644 hw/misc/k230_ddr.c > create mode 100644 include/hw/misc/k230_ddr.h > > diff --git a/MAINTAINERS b/MAINTAINERS > index ecb8cfdc41..1cb3ef6c02 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1826,8 +1826,10 @@ M: Chao Liu <chao.liu@processmission.com> > L: qemu-riscv@nongnu.org > S: Maintained > F: docs/system/riscv/k230.rst > +F: hw/misc/k230_ddr.c > F: hw/riscv/k230.c > F: hw/watchdog/k230_wdt.c > +F: include/hw/misc/k230_ddr.h > F: include/hw/riscv/k230.h > F: include/hw/watchdog/k230_wdt.h > F: tests/functional/riscv64/test_k230.py > diff --git a/hw/misc/k230_ddr.c b/hw/misc/k230_ddr.c > new file mode 100644 > index 0000000000..9ff2714e34 > --- /dev/null > +++ b/hw/misc/k230_ddr.c > @@ -0,0 +1,544 @@ > +/* > + * Kendryte K230 DDR controller and PHY models > + * > + * Models the K230 DDRC CFG registers and K230 DDR PHY registers exercised > + * by the K230 SDK U-Boot SPL. > + * > + * Copyright (c) 2026 Junze Cao <caojunze424@gmail.com> > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/module.h" > +#include "migration/vmstate.h" > +#include "hw/core/registerfields.h" > +#include "hw/core/resettable.h" > +#include "hw/misc/k230_ddr.h" > + > +/* DDRC CFG registers */ > + > +enum K230DDRCOperatingMode { > + K230_DDRC_MODE_INIT = 0, > + K230_DDRC_MODE_NORMAL = 1, > +}; > + > +REG32(K230_DDRC_MSTR, 0x000) > + > +REG32(K230_DDRC_STAT, 0x004) > + FIELD(K230_DDRC_STAT, OPERATING_MODE, 0, 3) > + > +REG32(K230_DDRC_PWRCTL, 0x030) > + > +REG32(K230_DDRC_RFSHCTL0, 0x050) > + > +REG32(K230_DDRC_RFSHTMG, 0x064) > + > +REG32(K230_DDRC_RFSHTMG1, 0x068) > + > +REG32(K230_DDRC_INIT0, 0x0d0) > + > +REG32(K230_DDRC_INIT2, 0x0d8) > + > +REG32(K230_DDRC_INIT3, 0x0dc) > + > +REG32(K230_DDRC_INIT5, 0x0e4) > + > +REG32(K230_DDRC_DRAMTMG0, 0x100) > +#define R_K230_DDRC_DRAMTMG(index) \ > + (R_K230_DDRC_DRAMTMG0 + (index)) > + > +REG32(K230_DDRC_ZQCTL0, 0x180) > + > +REG32(K230_DDRC_ZQCTL1, 0x184) > + > +REG32(K230_DDRC_ZQCTL2, 0x188) > + > +REG32(K230_DDRC_ZQSTAT, 0x18c) > + > +REG32(K230_DDRC_DFITMG0, 0x190) > + > +REG32(K230_DDRC_DFITMG1, 0x194) > + > +REG32(K230_DDRC_DFIUPD0, 0x1a0) > + > +REG32(K230_DDRC_DFIUPD1, 0x1a4) > + > +REG32(K230_DDRC_DFIUPD2, 0x1a8) > + > +REG32(K230_DDRC_DFIMISC, 0x1b0) > + FIELD(K230_DDRC_DFIMISC, DFI_INIT_COMPLETE_EN, 0, 1) > + FIELD(K230_DDRC_DFIMISC, DFI_INIT_START, 5, 1) > + > +REG32(K230_DDRC_DFITMG2, 0x1b4) > + > +REG32(K230_DDRC_DFISTAT, 0x1bc) > + FIELD(K230_DDRC_DFISTAT, DFI_INIT_COMPLETE, 0, 1) > + > +REG32(K230_DDRC_ODTCFG, 0x240) > + > +REG32(K230_DDRC_SWCTL, 0x320) > + FIELD(K230_DDRC_SWCTL, SW_DONE, 0, 1) > + > +REG32(K230_DDRC_SWSTAT, 0x324) > + FIELD(K230_DDRC_SWSTAT, SW_DONE_ACK, 0, 1) > + > +static const uint32_t k230_ddrc_reset_values[K230_DDRC_REG_COUNT] = { > + [R_K230_DDRC_MSTR] = 0x01040000, > + [R_K230_DDRC_RFSHCTL0] = 0x00210000, > + [R_K230_DDRC_RFSHTMG] = 0x0062008c, > + [R_K230_DDRC_RFSHTMG1] = 0x0000008c, > + [R_K230_DDRC_INIT0] = 0x0002004e, > + [R_K230_DDRC_INIT3] = 0x00000510, > + [R_K230_DDRC_INIT5] = 0x00100000, > + [R_K230_DDRC_DRAMTMG(0)] = 0x0f101b0f, > + [R_K230_DDRC_DRAMTMG(1)] = 0x00080414, > + [R_K230_DDRC_DRAMTMG(2)] = 0x0305060d, > + [R_K230_DDRC_DRAMTMG(3)] = 0x00004000, > + [R_K230_DDRC_DRAMTMG(4)] = 0x05040405, > + [R_K230_DDRC_DRAMTMG(5)] = 0x05050403, > + [R_K230_DDRC_DRAMTMG(6)] = 0x02020005, > + [R_K230_DDRC_DRAMTMG(7)] = 0x00000202, > + [R_K230_DDRC_DRAMTMG(8)] = 0x03034405, > + [R_K230_DDRC_DRAMTMG(9)] = 0x0004040d, > + [R_K230_DDRC_DRAMTMG(10)] = 0x001c180a, > + [R_K230_DDRC_DRAMTMG(11)] = 0x440c021c, > + [R_K230_DDRC_DRAMTMG(12)] = 0x00020610, > + [R_K230_DDRC_DRAMTMG(13)] = 0x1c200004, > + [R_K230_DDRC_DRAMTMG(14)] = 0x000000a0, > + [R_K230_DDRC_DRAMTMG(16)] = 0x05100404, > + [R_K230_DDRC_ZQCTL0] = 0x02000040, > + [R_K230_DDRC_ZQCTL1] = 0x02000100, > + [R_K230_DDRC_DFITMG0] = 0x07020002, > + [R_K230_DDRC_DFITMG1] = 0x00000404, > + [R_K230_DDRC_DFIUPD0] = 0x00400003, > + [R_K230_DDRC_DFIUPD1] = 0x00010001, > + [R_K230_DDRC_DFIUPD2] = 0x80000000, > + [R_K230_DDRC_DFIMISC] = 0x00000001, > + [R_K230_DDRC_DFITMG2] = 0x00000202, > + [R_K230_DDRC_ODTCFG] = 0x04000400, > + [R_K230_DDRC_SWCTL] = 0x00000001, > + [R_K230_DDRC_SWSTAT] = 0x00000001, > +}; > + > +/* K230 DDR PHY CSRs use byte offset = CSR index * 4. */ > +#define K230_DDR_PHY_CSR_OFFSET(index) ((index) * 4) > +#define K230_DDR_PHY_MASTER_CSR(reg) \ > + K230_DDR_PHY_CSR_OFFSET(0x20000 + (reg)) > +#define K230_DDR_PHY_APBONLY_CSR(reg) \ > + K230_DDR_PHY_CSR_OFFSET(0xd0000 + (reg)) > + > +#define K230_DDR_PHY_ATX_IMPEDANCE_RESET UINT32_C(0x03ff) > + > +REG32(K230_DDR_PHY_MICRO_CONT_MUX_SEL, > + K230_DDR_PHY_APBONLY_CSR(0x000)) > + FIELD(K230_DDR_PHY_MICRO_CONT_MUX_SEL, MICRO_CONT_MUX_SEL, 0, 1) > + > +REG32(K230_DDR_PHY_TRAINING_STATUS, > + K230_DDR_PHY_APBONLY_CSR(0x004)) > + FIELD(K230_DDR_PHY_TRAINING_STATUS, MAILBOX_EMPTY, 0, 1) > + > +REG32(K230_DDR_PHY_TRAINING_ACK, > + K230_DDR_PHY_APBONLY_CSR(0x031)) > + > +REG32(K230_DDR_PHY_TRAINING_MESSAGE, > + K230_DDR_PHY_APBONLY_CSR(0x032)) > + > +REG32(K230_DDR_PHY_TRAINING_TRIGGER, > + K230_DDR_PHY_APBONLY_CSR(0x099)) > + > +#define K230_DDR_PHY_TX_IMPEDANCE_CTRL1_RESET UINT32_C(0x0fff) > + > +REG32(K230_DDR_PHY_DFI_INIT_COMPLETE, > + K230_DDR_PHY_MASTER_CSR(0x0f9)) > + FIELD(K230_DDR_PHY_DFI_INIT_COMPLETE, DFI_INIT_COMPLETE, 0, 1) > + > +REG32(K230_DDR_PHY_VREF_IN_GLOBAL, > + K230_DDR_PHY_MASTER_CSR(0x0b2)) > +#define K230_DDR_PHY_VREF_IN_GLOBAL_RESET UINT32_C(0x0200) > + > +static void k230_ddr_cfg_update_state(K230DDRCfgState *s) > +{ > + bool dfi_complete = false; > + unsigned int operating_mode = K230_DDRC_MODE_INIT; > + > + if (s->phy) { > + dfi_complete = FIELD_EX32(s->phy->dfi_init_complete, > + K230_DDR_PHY_DFI_INIT_COMPLETE, > + DFI_INIT_COMPLETE); > + } > + > + ARRAY_FIELD_DP32(s->regs, K230_DDRC_DFISTAT, > + DFI_INIT_COMPLETE, dfi_complete); > + ARRAY_FIELD_DP32(s->regs, K230_DDRC_SWSTAT, SW_DONE_ACK, > + ARRAY_FIELD_EX32(s->regs, K230_DDRC_SWCTL, SW_DONE)); > + > + if (dfi_complete && > + ARRAY_FIELD_EX32(s->regs, K230_DDRC_DFIMISC, > + DFI_INIT_COMPLETE_EN)) { > + s->initialized = true; > + } > + > + if (s->initialized) { > + operating_mode = K230_DDRC_MODE_NORMAL; > + } > + > + ARRAY_FIELD_DP32(s->regs, K230_DDRC_STAT, > + OPERATING_MODE, operating_mode); > +} > + > +static uint64_t k230_ddr_cfg_read(void *opaque, hwaddr addr, unsigned int size) > +{ > + K230DDRCfgState *s = opaque; > + uint64_t value = 0; > + > + if (addr < K230_DDRC_REG_SIZE) { > + k230_ddr_cfg_update_state(s); > + value = s->regs[addr / sizeof(uint32_t)]; > + } > + > + return value; > +} > + > +static void k230_ddr_cfg_write(void *opaque, hwaddr addr, uint64_t value, > + unsigned int size) > +{ > + K230DDRCfgState *s = opaque; > + uint32_t val = value; > + > + if (addr >= K230_DDRC_REG_SIZE) { > + return; > + } > + > + switch (addr) { > + case A_K230_DDRC_STAT: > + case A_K230_DDRC_DFISTAT: > + case A_K230_DDRC_ZQSTAT: > + case A_K230_DDRC_SWSTAT: > + return; > + case A_K230_DDRC_PWRCTL: > + s->regs[R_K230_DDRC_PWRCTL] = val & MAKE_64BIT_MASK(0, 9); > + break; > + case A_K230_DDRC_ZQCTL2: > + /* ZQ reset completes immediately and the W1S bit self-clears. */ > + s->regs[R_K230_DDRC_ZQCTL2] = 0; > + s->regs[R_K230_DDRC_ZQSTAT] = 0; > + break; > + case A_K230_DDRC_DFIMISC: > + s->regs[R_K230_DDRC_DFIMISC] = > + val & (MAKE_64BIT_MASK(0, 6) | MAKE_64BIT_MASK(8, 5)); > + if (s->phy && s->phy->training_complete && > + FIELD_EX32(val, K230_DDRC_DFIMISC, DFI_INIT_START)) { > + s->phy->dfi_init_complete = FIELD_DP32( > + s->phy->dfi_init_complete, > + K230_DDR_PHY_DFI_INIT_COMPLETE, DFI_INIT_COMPLETE, 1); > + } > + break; > + case A_K230_DDRC_SWCTL: > + s->regs[R_K230_DDRC_SWCTL] = > + val & R_K230_DDRC_SWCTL_SW_DONE_MASK; > + break; > + default: > + s->regs[addr / sizeof(uint32_t)] = val; > + break; > + } > + > + k230_ddr_cfg_update_state(s); > +} > + > +static bool k230_ddr_phy_decode_anib(hwaddr addr, unsigned int *anib) > +{ > + uint32_t csr = addr / sizeof(uint32_t); > + > + if ((csr & 0xfff) != 0x043) { > + return false; > + } > + > + *anib = csr >> 12; > + return *anib < K230_DDR_PHY_ANIB_COUNT; > +} > + > +static bool k230_ddr_phy_decode_dbyte(hwaddr addr, uint32_t reg, > + unsigned int *dbyte, > + unsigned int *nibble) > +{ > + uint32_t csr = addr / sizeof(uint32_t); > + uint32_t block_offset; > + > + if (csr < 0x10000) { > + return false; > + } > + > + csr -= 0x10000; > + *dbyte = csr >> 12; > + if (*dbyte >= K230_DDR_PHY_DBYTE_COUNT) { > + return false; > + } > + > + block_offset = csr & 0xfff; > + *nibble = block_offset >> 8; > + return *nibble < K230_DDR_PHY_NIBBLES_PER_DBYTE && > + (block_offset & 0xff) == reg; > +} > + > +static uint64_t k230_ddr_phy_read(void *opaque, hwaddr addr, > + unsigned int size) > +{ > + K230DDRPhyState *s = opaque; > + unsigned int dbyte; > + unsigned int nibble; > + unsigned int anib; > + uint64_t value = 0; > + > + switch (addr) { > + case A_K230_DDR_PHY_MICRO_CONT_MUX_SEL: > + value = s->micro_cont_mux_sel; > + break; > + case A_K230_DDR_PHY_TRAINING_STATUS: > + value = s->mailbox_message_pending ? 0 : > + R_K230_DDR_PHY_TRAINING_STATUS_MAILBOX_EMPTY_MASK; > + break; > + case A_K230_DDR_PHY_TRAINING_MESSAGE: > + value = s->training_complete ? 0x07 : 0; > + break; > + case A_K230_DDR_PHY_TRAINING_ACK: > + case A_K230_DDR_PHY_TRAINING_TRIGGER: > + break; > + case A_K230_DDR_PHY_DFI_INIT_COMPLETE: > + value = s->dfi_init_complete; > + break; > + case A_K230_DDR_PHY_VREF_IN_GLOBAL: > + value = s->vref_in_global; > + break; > + default: > + if (k230_ddr_phy_decode_anib(addr, &anib)) { > + value = s->atx_impedance[anib]; > + } else if (k230_ddr_phy_decode_dbyte(addr, 0x049, > + &dbyte, &nibble)) { > + value = s->tx_impedance_ctrl1[dbyte][nibble]; > + } else if (k230_ddr_phy_decode_dbyte(addr, 0x04d, > + &dbyte, &nibble)) { > + value = s->tx_odt_drv_stren[dbyte][nibble]; > + } > + break; Be aware that there's no guarantee (at least semantically in the code) that you'll hit any of these ifs, i.e. it's possible that 'value' won't be set by any of these. If this the intended behavior then it's fine. If there's an expectation that some of these will return 'true' and value will always be defined, I advise adding a qemu_log() recording that 'value' will be returned 0. If this is really something that shouldn't happen you can even use g_assert_not_reached() to error out. Everything else LGTM. Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> > + } > + > + return value; > +} > + > +static void k230_ddr_phy_write(void *opaque, hwaddr addr, uint64_t value, > + unsigned int size) > +{ > + K230DDRPhyState *s = opaque; > + uint16_t val = value; > + unsigned int dbyte; > + unsigned int nibble; > + unsigned int anib; > + > + switch (addr) { > + case A_K230_DDR_PHY_MICRO_CONT_MUX_SEL: > + s->micro_cont_mux_sel = > + val & R_K230_DDR_PHY_MICRO_CONT_MUX_SEL_MICRO_CONT_MUX_SEL_MASK; > + return; > + case A_K230_DDR_PHY_TRAINING_STATUS: > + case A_K230_DDR_PHY_TRAINING_MESSAGE: > + return; > + case A_K230_DDR_PHY_TRAINING_ACK: > + if (val == 0) { > + s->mailbox_message_pending = false; > + } > + return; > + case A_K230_DDR_PHY_TRAINING_TRIGGER: > + if (val != 0) { > + s->training_trigger_seen = true; > + } else if (s->training_trigger_seen) { > + /* Abstract the loaded firmware run to its final mailbox message. */ > + s->training_trigger_seen = false; > + s->training_complete = true; > + s->mailbox_message_pending = true; > + } > + return; > + default: > + break; > + } > + > + if (FIELD_EX32(s->micro_cont_mux_sel, > + K230_DDR_PHY_MICRO_CONT_MUX_SEL, > + MICRO_CONT_MUX_SEL)) { > + return; > + } > + > + switch (addr) { > + case A_K230_DDR_PHY_DFI_INIT_COMPLETE: > + s->dfi_init_complete = > + val & R_K230_DDR_PHY_DFI_INIT_COMPLETE_DFI_INIT_COMPLETE_MASK; > + return; > + case A_K230_DDR_PHY_VREF_IN_GLOBAL: > + s->vref_in_global = val & UINT16_C(0x7fff); > + return; > + default: > + break; > + } > + > + if (k230_ddr_phy_decode_anib(addr, &anib)) { > + s->atx_impedance[anib] = val & UINT16_C(0x03ff); > + return; > + } > + > + if (k230_ddr_phy_decode_dbyte(addr, 0x049, &dbyte, &nibble)) { > + s->tx_impedance_ctrl1[dbyte][nibble] = val & UINT16_C(0x0fff); > + return; > + } > + > + if (k230_ddr_phy_decode_dbyte(addr, 0x04d, &dbyte, &nibble)) { > + s->tx_odt_drv_stren[dbyte][nibble] = val & UINT16_C(0x0fff); > + } > +} > + > +static const MemoryRegionOps k230_ddr_cfg_ops = { > + .read = k230_ddr_cfg_read, > + .write = k230_ddr_cfg_write, > + .endianness = DEVICE_LITTLE_ENDIAN, > + .valid = { > + .min_access_size = 4, > + .max_access_size = 4, > + .unaligned = false, > + }, > +}; > + > +static const MemoryRegionOps k230_ddr_phy_ops = { > + .read = k230_ddr_phy_read, > + .write = k230_ddr_phy_write, > + .endianness = DEVICE_LITTLE_ENDIAN, > + .valid = { > + .min_access_size = 4, > + .max_access_size = 4, > + .unaligned = false, > + }, > +}; > + > +static void k230_ddr_cfg_init(Object *obj) > +{ > + K230DDRCfgState *s = K230_DDR_CFG(obj); > + > + memory_region_init_io(&s->mmio, obj, &k230_ddr_cfg_ops, s, > + "k230-ddr-cfg", K230_DDRC_MMIO_SIZE); > + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); > +} > + > +static void k230_ddr_phy_init(Object *obj) > +{ > + K230DDRPhyState *s = K230_DDR_PHY(obj); > + > + memory_region_init_io(&s->mmio, obj, &k230_ddr_phy_ops, s, > + "k230-ddr-phy", K230_DDR_PHY_MMIO_SIZE); > + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); > +} > + > +static void k230_ddr_cfg_reset_enter(Object *obj, ResetType type) > +{ > + K230DDRCfgState *s = K230_DDR_CFG(obj); > + > + s->initialized = false; > + memcpy(s->regs, k230_ddrc_reset_values, sizeof(s->regs)); > +} > + > +static void k230_ddr_phy_reset_enter(Object *obj, ResetType type) > +{ > + K230DDRPhyState *s = K230_DDR_PHY(obj); > + unsigned int dbyte; > + unsigned int nibble; > + unsigned int anib; > + > + memset(s->tx_odt_drv_stren, 0, sizeof(s->tx_odt_drv_stren)); > + > + for (anib = 0; anib < ARRAY_SIZE(s->atx_impedance); anib++) { > + s->atx_impedance[anib] = K230_DDR_PHY_ATX_IMPEDANCE_RESET; > + } > + > + for (dbyte = 0; dbyte < ARRAY_SIZE(s->tx_impedance_ctrl1); dbyte++) { > + for (nibble = 0; > + nibble < ARRAY_SIZE(s->tx_impedance_ctrl1[dbyte]); nibble++) { > + s->tx_impedance_ctrl1[dbyte][nibble] = > + K230_DDR_PHY_TX_IMPEDANCE_CTRL1_RESET; > + } > + } > + > + s->dfi_init_complete = 0; > + s->vref_in_global = K230_DDR_PHY_VREF_IN_GLOBAL_RESET; > + s->micro_cont_mux_sel = 0; > + s->training_trigger_seen = false; > + s->training_complete = false; > + s->mailbox_message_pending = false; > +} > + > +static const VMStateDescription vmstate_k230_ddr_cfg = { > + .name = "k230-ddr-cfg", > + .version_id = 1, > + .minimum_version_id = 1, > + .fields = (const VMStateField[]) { > + VMSTATE_UINT32_ARRAY(regs, K230DDRCfgState, K230_DDRC_REG_COUNT), > + VMSTATE_BOOL(initialized, K230DDRCfgState), > + VMSTATE_END_OF_LIST() > + }, > +}; > + > +static const VMStateDescription vmstate_k230_ddr_phy = { > + .name = "k230-ddr-phy", > + .version_id = 1, > + .minimum_version_id = 1, > + .fields = (const VMStateField[]) { > + VMSTATE_UINT16_ARRAY(atx_impedance, K230DDRPhyState, > + K230_DDR_PHY_ANIB_COUNT), > + VMSTATE_UINT16_2DARRAY(tx_impedance_ctrl1, K230DDRPhyState, > + K230_DDR_PHY_DBYTE_COUNT, > + K230_DDR_PHY_NIBBLES_PER_DBYTE), > + VMSTATE_UINT16_2DARRAY(tx_odt_drv_stren, K230DDRPhyState, > + K230_DDR_PHY_DBYTE_COUNT, > + K230_DDR_PHY_NIBBLES_PER_DBYTE), > + VMSTATE_UINT16(dfi_init_complete, K230DDRPhyState), > + VMSTATE_UINT16(vref_in_global, K230DDRPhyState), > + VMSTATE_UINT16(micro_cont_mux_sel, K230DDRPhyState), > + VMSTATE_BOOL(training_trigger_seen, K230DDRPhyState), > + VMSTATE_BOOL(training_complete, K230DDRPhyState), > + VMSTATE_BOOL(mailbox_message_pending, K230DDRPhyState), > + VMSTATE_END_OF_LIST() > + }, > +}; > + > +static void k230_ddr_cfg_class_init(ObjectClass *klass, const void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + ResettableClass *rc = RESETTABLE_CLASS(klass); > + > + rc->phases.enter = k230_ddr_cfg_reset_enter; > + dc->vmsd = &vmstate_k230_ddr_cfg; > +} > + > +static void k230_ddr_phy_class_init(ObjectClass *klass, const void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + ResettableClass *rc = RESETTABLE_CLASS(klass); > + > + rc->phases.enter = k230_ddr_phy_reset_enter; > + dc->vmsd = &vmstate_k230_ddr_phy; > +} > + > +static const TypeInfo k230_ddr_types[] = { > + { > + .name = TYPE_K230_DDR_CFG, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_size = sizeof(K230DDRCfgState), > + .instance_init = k230_ddr_cfg_init, > + .class_init = k230_ddr_cfg_class_init, > + }, > + { > + .name = TYPE_K230_DDR_PHY, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_size = sizeof(K230DDRPhyState), > + .instance_init = k230_ddr_phy_init, > + .class_init = k230_ddr_phy_class_init, > + }, > +}; > + > +DEFINE_TYPES(k230_ddr_types) > diff --git a/hw/misc/meson.build b/hw/misc/meson.build > index 23265f6035..6d5e2b2647 100644 > --- a/hw/misc/meson.build > +++ b/hw/misc/meson.build > @@ -28,6 +28,7 @@ system_ss.add(when: 'CONFIG_IOSB', if_true: files('iosb.c')) > system_ss.add(when: 'CONFIG_VIRT_CTRL', if_true: files('virt_ctrl.c')) > > # RISC-V devices > +system_ss.add(when: 'CONFIG_K230', if_true: files('k230_ddr.c')) > system_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c')) > system_ss.add(when: 'CONFIG_MCHP_PFSOC_IOSCB', if_true: files('mchp_pfsoc_ioscb.c')) > system_ss.add(when: 'CONFIG_MCHP_PFSOC_SYSREG', if_true: files('mchp_pfsoc_sysreg.c')) > diff --git a/include/hw/misc/k230_ddr.h b/include/hw/misc/k230_ddr.h > new file mode 100644 > index 0000000000..d912e8e1b0 > --- /dev/null > +++ b/include/hw/misc/k230_ddr.h > @@ -0,0 +1,59 @@ > +/* > + * Kendryte K230 DDR controller and PHY models > + * > + * Device state and type declarations for the K230 DDRC CFG and K230 DDR PHY > + * registers. > + * > + * Copyright (c) 2026 Junze Cao <caojunze424@gmail.com> > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#ifndef HW_MISC_K230_DDR_H > +#define HW_MISC_K230_DDR_H > + > +#include "hw/core/sysbus.h" > + > +#define K230_DDRC_MMIO_SIZE 0x02000000 > +#define K230_DDR_PHY_MMIO_SIZE 0x00400000 > + > +#define K230_DDRC_REG_SIZE 0x328 > +#define K230_DDRC_REG_COUNT (K230_DDRC_REG_SIZE / sizeof(uint32_t)) > + > +#define K230_DDR_PHY_ANIB_COUNT 10 > +#define K230_DDR_PHY_DBYTE_COUNT 4 > +#define K230_DDR_PHY_NIBBLES_PER_DBYTE 2 > + > +#define TYPE_K230_DDR_CFG "riscv.k230.ddr-cfg" > +OBJECT_DECLARE_SIMPLE_TYPE(K230DDRCfgState, K230_DDR_CFG) > + > +#define TYPE_K230_DDR_PHY "riscv.k230.ddr-phy" > +OBJECT_DECLARE_SIMPLE_TYPE(K230DDRPhyState, K230_DDR_PHY) > + > +struct K230DDRCfgState { > + SysBusDevice parent_obj; > + > + MemoryRegion mmio; > + K230DDRPhyState *phy; > + uint32_t regs[K230_DDRC_REG_COUNT]; > + bool initialized; > +}; > + > +struct K230DDRPhyState { > + SysBusDevice parent_obj; > + > + MemoryRegion mmio; > + uint16_t atx_impedance[K230_DDR_PHY_ANIB_COUNT]; > + uint16_t tx_impedance_ctrl1[K230_DDR_PHY_DBYTE_COUNT] > + [K230_DDR_PHY_NIBBLES_PER_DBYTE]; > + uint16_t tx_odt_drv_stren[K230_DDR_PHY_DBYTE_COUNT] > + [K230_DDR_PHY_NIBBLES_PER_DBYTE]; > + uint16_t dfi_init_complete; > + uint16_t vref_in_global; > + uint16_t micro_cont_mux_sel; > + bool training_trigger_seen; > + bool training_complete; > + bool mailbox_message_pending; > +}; > + > +#endif ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] hw/misc: Add K230 DDR controller and PHY models 2026-07-16 13:24 ` [PATCH 1/3] hw/misc: " Junze Cao 2026-07-22 20:06 ` Daniel Henrique Barboza @ 2026-07-23 8:41 ` Chao Liu 1 sibling, 0 replies; 10+ messages in thread From: Chao Liu @ 2026-07-23 8:41 UTC (permalink / raw) To: Junze Cao Cc: qemu-devel, qemu-riscv, pierrick.bouvier, palmer, alistair.francis, liwei1518, daniel.barboza, zhiwei_liu, farosas, lvivier, pbonzini On Thu, Jul 16, 2026 at 09:24:21PM +0800, Junze Cao wrote: > The K230 SDK U-Boot SPL programs K230 DDRC CFG and K230 DDR PHY > registers before DRAM can be used. > > Add separate SysBus devices for both register ranges. Model controller > reset values, DFI and software-update handshakes. For the PHY, model > register ownership, the training mailbox, and DFI completion. > > Include migration state for both devices. > > Signed-off-by: Junze Cao <caojunze424@gmail.com> Suggested-by: Chao Liu <chao.liu@processmission.com> Thanks, Chao > --- > MAINTAINERS | 2 + > hw/misc/k230_ddr.c | 544 +++++++++++++++++++++++++++++++++++++ > hw/misc/meson.build | 1 + > include/hw/misc/k230_ddr.h | 59 ++++ > 4 files changed, 606 insertions(+) > create mode 100644 hw/misc/k230_ddr.c > create mode 100644 include/hw/misc/k230_ddr.h > > diff --git a/MAINTAINERS b/MAINTAINERS > index ecb8cfdc41..1cb3ef6c02 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1826,8 +1826,10 @@ M: Chao Liu <chao.liu@processmission.com> > L: qemu-riscv@nongnu.org > S: Maintained > F: docs/system/riscv/k230.rst > +F: hw/misc/k230_ddr.c > F: hw/riscv/k230.c > F: hw/watchdog/k230_wdt.c > +F: include/hw/misc/k230_ddr.h > F: include/hw/riscv/k230.h > F: include/hw/watchdog/k230_wdt.h > F: tests/functional/riscv64/test_k230.py > diff --git a/hw/misc/k230_ddr.c b/hw/misc/k230_ddr.c > new file mode 100644 > index 0000000000..9ff2714e34 > --- /dev/null > +++ b/hw/misc/k230_ddr.c > @@ -0,0 +1,544 @@ > +/* > + * Kendryte K230 DDR controller and PHY models > + * > + * Models the K230 DDRC CFG registers and K230 DDR PHY registers exercised > + * by the K230 SDK U-Boot SPL. > + * > + * Copyright (c) 2026 Junze Cao <caojunze424@gmail.com> > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/module.h" > +#include "migration/vmstate.h" > +#include "hw/core/registerfields.h" > +#include "hw/core/resettable.h" > +#include "hw/misc/k230_ddr.h" > + > +/* DDRC CFG registers */ > + > +enum K230DDRCOperatingMode { > + K230_DDRC_MODE_INIT = 0, > + K230_DDRC_MODE_NORMAL = 1, > +}; > + > +REG32(K230_DDRC_MSTR, 0x000) > + > +REG32(K230_DDRC_STAT, 0x004) > + FIELD(K230_DDRC_STAT, OPERATING_MODE, 0, 3) > + > +REG32(K230_DDRC_PWRCTL, 0x030) > + > +REG32(K230_DDRC_RFSHCTL0, 0x050) > + > +REG32(K230_DDRC_RFSHTMG, 0x064) > + > +REG32(K230_DDRC_RFSHTMG1, 0x068) > + > +REG32(K230_DDRC_INIT0, 0x0d0) > + > +REG32(K230_DDRC_INIT2, 0x0d8) > + > +REG32(K230_DDRC_INIT3, 0x0dc) > + > +REG32(K230_DDRC_INIT5, 0x0e4) > + > +REG32(K230_DDRC_DRAMTMG0, 0x100) > +#define R_K230_DDRC_DRAMTMG(index) \ > + (R_K230_DDRC_DRAMTMG0 + (index)) > + > +REG32(K230_DDRC_ZQCTL0, 0x180) > + > +REG32(K230_DDRC_ZQCTL1, 0x184) > + > +REG32(K230_DDRC_ZQCTL2, 0x188) > + > +REG32(K230_DDRC_ZQSTAT, 0x18c) > + > +REG32(K230_DDRC_DFITMG0, 0x190) > + > +REG32(K230_DDRC_DFITMG1, 0x194) > + > +REG32(K230_DDRC_DFIUPD0, 0x1a0) > + > +REG32(K230_DDRC_DFIUPD1, 0x1a4) > + > +REG32(K230_DDRC_DFIUPD2, 0x1a8) > + > +REG32(K230_DDRC_DFIMISC, 0x1b0) > + FIELD(K230_DDRC_DFIMISC, DFI_INIT_COMPLETE_EN, 0, 1) > + FIELD(K230_DDRC_DFIMISC, DFI_INIT_START, 5, 1) > + > +REG32(K230_DDRC_DFITMG2, 0x1b4) > + > +REG32(K230_DDRC_DFISTAT, 0x1bc) > + FIELD(K230_DDRC_DFISTAT, DFI_INIT_COMPLETE, 0, 1) > + > +REG32(K230_DDRC_ODTCFG, 0x240) > + > +REG32(K230_DDRC_SWCTL, 0x320) > + FIELD(K230_DDRC_SWCTL, SW_DONE, 0, 1) > + > +REG32(K230_DDRC_SWSTAT, 0x324) > + FIELD(K230_DDRC_SWSTAT, SW_DONE_ACK, 0, 1) > + > +static const uint32_t k230_ddrc_reset_values[K230_DDRC_REG_COUNT] = { > + [R_K230_DDRC_MSTR] = 0x01040000, > + [R_K230_DDRC_RFSHCTL0] = 0x00210000, > + [R_K230_DDRC_RFSHTMG] = 0x0062008c, > + [R_K230_DDRC_RFSHTMG1] = 0x0000008c, > + [R_K230_DDRC_INIT0] = 0x0002004e, > + [R_K230_DDRC_INIT3] = 0x00000510, > + [R_K230_DDRC_INIT5] = 0x00100000, > + [R_K230_DDRC_DRAMTMG(0)] = 0x0f101b0f, > + [R_K230_DDRC_DRAMTMG(1)] = 0x00080414, > + [R_K230_DDRC_DRAMTMG(2)] = 0x0305060d, > + [R_K230_DDRC_DRAMTMG(3)] = 0x00004000, > + [R_K230_DDRC_DRAMTMG(4)] = 0x05040405, > + [R_K230_DDRC_DRAMTMG(5)] = 0x05050403, > + [R_K230_DDRC_DRAMTMG(6)] = 0x02020005, > + [R_K230_DDRC_DRAMTMG(7)] = 0x00000202, > + [R_K230_DDRC_DRAMTMG(8)] = 0x03034405, > + [R_K230_DDRC_DRAMTMG(9)] = 0x0004040d, > + [R_K230_DDRC_DRAMTMG(10)] = 0x001c180a, > + [R_K230_DDRC_DRAMTMG(11)] = 0x440c021c, > + [R_K230_DDRC_DRAMTMG(12)] = 0x00020610, > + [R_K230_DDRC_DRAMTMG(13)] = 0x1c200004, > + [R_K230_DDRC_DRAMTMG(14)] = 0x000000a0, > + [R_K230_DDRC_DRAMTMG(16)] = 0x05100404, > + [R_K230_DDRC_ZQCTL0] = 0x02000040, > + [R_K230_DDRC_ZQCTL1] = 0x02000100, > + [R_K230_DDRC_DFITMG0] = 0x07020002, > + [R_K230_DDRC_DFITMG1] = 0x00000404, > + [R_K230_DDRC_DFIUPD0] = 0x00400003, > + [R_K230_DDRC_DFIUPD1] = 0x00010001, > + [R_K230_DDRC_DFIUPD2] = 0x80000000, > + [R_K230_DDRC_DFIMISC] = 0x00000001, > + [R_K230_DDRC_DFITMG2] = 0x00000202, > + [R_K230_DDRC_ODTCFG] = 0x04000400, > + [R_K230_DDRC_SWCTL] = 0x00000001, > + [R_K230_DDRC_SWSTAT] = 0x00000001, > +}; > + > +/* K230 DDR PHY CSRs use byte offset = CSR index * 4. */ > +#define K230_DDR_PHY_CSR_OFFSET(index) ((index) * 4) > +#define K230_DDR_PHY_MASTER_CSR(reg) \ > + K230_DDR_PHY_CSR_OFFSET(0x20000 + (reg)) > +#define K230_DDR_PHY_APBONLY_CSR(reg) \ > + K230_DDR_PHY_CSR_OFFSET(0xd0000 + (reg)) > + > +#define K230_DDR_PHY_ATX_IMPEDANCE_RESET UINT32_C(0x03ff) > + > +REG32(K230_DDR_PHY_MICRO_CONT_MUX_SEL, > + K230_DDR_PHY_APBONLY_CSR(0x000)) > + FIELD(K230_DDR_PHY_MICRO_CONT_MUX_SEL, MICRO_CONT_MUX_SEL, 0, 1) > + > +REG32(K230_DDR_PHY_TRAINING_STATUS, > + K230_DDR_PHY_APBONLY_CSR(0x004)) > + FIELD(K230_DDR_PHY_TRAINING_STATUS, MAILBOX_EMPTY, 0, 1) > + > +REG32(K230_DDR_PHY_TRAINING_ACK, > + K230_DDR_PHY_APBONLY_CSR(0x031)) > + > +REG32(K230_DDR_PHY_TRAINING_MESSAGE, > + K230_DDR_PHY_APBONLY_CSR(0x032)) > + > +REG32(K230_DDR_PHY_TRAINING_TRIGGER, > + K230_DDR_PHY_APBONLY_CSR(0x099)) > + > +#define K230_DDR_PHY_TX_IMPEDANCE_CTRL1_RESET UINT32_C(0x0fff) > + > +REG32(K230_DDR_PHY_DFI_INIT_COMPLETE, > + K230_DDR_PHY_MASTER_CSR(0x0f9)) > + FIELD(K230_DDR_PHY_DFI_INIT_COMPLETE, DFI_INIT_COMPLETE, 0, 1) > + > +REG32(K230_DDR_PHY_VREF_IN_GLOBAL, > + K230_DDR_PHY_MASTER_CSR(0x0b2)) > +#define K230_DDR_PHY_VREF_IN_GLOBAL_RESET UINT32_C(0x0200) > + > +static void k230_ddr_cfg_update_state(K230DDRCfgState *s) > +{ > + bool dfi_complete = false; > + unsigned int operating_mode = K230_DDRC_MODE_INIT; > + > + if (s->phy) { > + dfi_complete = FIELD_EX32(s->phy->dfi_init_complete, > + K230_DDR_PHY_DFI_INIT_COMPLETE, > + DFI_INIT_COMPLETE); > + } > + > + ARRAY_FIELD_DP32(s->regs, K230_DDRC_DFISTAT, > + DFI_INIT_COMPLETE, dfi_complete); > + ARRAY_FIELD_DP32(s->regs, K230_DDRC_SWSTAT, SW_DONE_ACK, > + ARRAY_FIELD_EX32(s->regs, K230_DDRC_SWCTL, SW_DONE)); > + > + if (dfi_complete && > + ARRAY_FIELD_EX32(s->regs, K230_DDRC_DFIMISC, > + DFI_INIT_COMPLETE_EN)) { > + s->initialized = true; > + } > + > + if (s->initialized) { > + operating_mode = K230_DDRC_MODE_NORMAL; > + } > + > + ARRAY_FIELD_DP32(s->regs, K230_DDRC_STAT, > + OPERATING_MODE, operating_mode); > +} > + > +static uint64_t k230_ddr_cfg_read(void *opaque, hwaddr addr, unsigned int size) > +{ > + K230DDRCfgState *s = opaque; > + uint64_t value = 0; > + > + if (addr < K230_DDRC_REG_SIZE) { > + k230_ddr_cfg_update_state(s); > + value = s->regs[addr / sizeof(uint32_t)]; > + } > + > + return value; > +} > + > +static void k230_ddr_cfg_write(void *opaque, hwaddr addr, uint64_t value, > + unsigned int size) > +{ > + K230DDRCfgState *s = opaque; > + uint32_t val = value; > + > + if (addr >= K230_DDRC_REG_SIZE) { > + return; > + } > + > + switch (addr) { > + case A_K230_DDRC_STAT: > + case A_K230_DDRC_DFISTAT: > + case A_K230_DDRC_ZQSTAT: > + case A_K230_DDRC_SWSTAT: > + return; > + case A_K230_DDRC_PWRCTL: > + s->regs[R_K230_DDRC_PWRCTL] = val & MAKE_64BIT_MASK(0, 9); > + break; > + case A_K230_DDRC_ZQCTL2: > + /* ZQ reset completes immediately and the W1S bit self-clears. */ > + s->regs[R_K230_DDRC_ZQCTL2] = 0; > + s->regs[R_K230_DDRC_ZQSTAT] = 0; > + break; > + case A_K230_DDRC_DFIMISC: > + s->regs[R_K230_DDRC_DFIMISC] = > + val & (MAKE_64BIT_MASK(0, 6) | MAKE_64BIT_MASK(8, 5)); > + if (s->phy && s->phy->training_complete && > + FIELD_EX32(val, K230_DDRC_DFIMISC, DFI_INIT_START)) { > + s->phy->dfi_init_complete = FIELD_DP32( > + s->phy->dfi_init_complete, > + K230_DDR_PHY_DFI_INIT_COMPLETE, DFI_INIT_COMPLETE, 1); > + } > + break; > + case A_K230_DDRC_SWCTL: > + s->regs[R_K230_DDRC_SWCTL] = > + val & R_K230_DDRC_SWCTL_SW_DONE_MASK; > + break; > + default: > + s->regs[addr / sizeof(uint32_t)] = val; > + break; > + } > + > + k230_ddr_cfg_update_state(s); > +} > + > +static bool k230_ddr_phy_decode_anib(hwaddr addr, unsigned int *anib) > +{ > + uint32_t csr = addr / sizeof(uint32_t); > + > + if ((csr & 0xfff) != 0x043) { > + return false; > + } > + > + *anib = csr >> 12; > + return *anib < K230_DDR_PHY_ANIB_COUNT; > +} > + > +static bool k230_ddr_phy_decode_dbyte(hwaddr addr, uint32_t reg, > + unsigned int *dbyte, > + unsigned int *nibble) > +{ > + uint32_t csr = addr / sizeof(uint32_t); > + uint32_t block_offset; > + > + if (csr < 0x10000) { > + return false; > + } > + > + csr -= 0x10000; > + *dbyte = csr >> 12; > + if (*dbyte >= K230_DDR_PHY_DBYTE_COUNT) { > + return false; > + } > + > + block_offset = csr & 0xfff; > + *nibble = block_offset >> 8; > + return *nibble < K230_DDR_PHY_NIBBLES_PER_DBYTE && > + (block_offset & 0xff) == reg; > +} > + > +static uint64_t k230_ddr_phy_read(void *opaque, hwaddr addr, > + unsigned int size) > +{ > + K230DDRPhyState *s = opaque; > + unsigned int dbyte; > + unsigned int nibble; > + unsigned int anib; > + uint64_t value = 0; > + > + switch (addr) { > + case A_K230_DDR_PHY_MICRO_CONT_MUX_SEL: > + value = s->micro_cont_mux_sel; > + break; > + case A_K230_DDR_PHY_TRAINING_STATUS: > + value = s->mailbox_message_pending ? 0 : > + R_K230_DDR_PHY_TRAINING_STATUS_MAILBOX_EMPTY_MASK; > + break; > + case A_K230_DDR_PHY_TRAINING_MESSAGE: > + value = s->training_complete ? 0x07 : 0; > + break; > + case A_K230_DDR_PHY_TRAINING_ACK: > + case A_K230_DDR_PHY_TRAINING_TRIGGER: > + break; > + case A_K230_DDR_PHY_DFI_INIT_COMPLETE: > + value = s->dfi_init_complete; > + break; > + case A_K230_DDR_PHY_VREF_IN_GLOBAL: > + value = s->vref_in_global; > + break; > + default: > + if (k230_ddr_phy_decode_anib(addr, &anib)) { > + value = s->atx_impedance[anib]; > + } else if (k230_ddr_phy_decode_dbyte(addr, 0x049, > + &dbyte, &nibble)) { > + value = s->tx_impedance_ctrl1[dbyte][nibble]; > + } else if (k230_ddr_phy_decode_dbyte(addr, 0x04d, > + &dbyte, &nibble)) { > + value = s->tx_odt_drv_stren[dbyte][nibble]; > + } > + break; > + } > + > + return value; > +} > + > +static void k230_ddr_phy_write(void *opaque, hwaddr addr, uint64_t value, > + unsigned int size) > +{ > + K230DDRPhyState *s = opaque; > + uint16_t val = value; > + unsigned int dbyte; > + unsigned int nibble; > + unsigned int anib; > + > + switch (addr) { > + case A_K230_DDR_PHY_MICRO_CONT_MUX_SEL: > + s->micro_cont_mux_sel = > + val & R_K230_DDR_PHY_MICRO_CONT_MUX_SEL_MICRO_CONT_MUX_SEL_MASK; > + return; > + case A_K230_DDR_PHY_TRAINING_STATUS: > + case A_K230_DDR_PHY_TRAINING_MESSAGE: > + return; > + case A_K230_DDR_PHY_TRAINING_ACK: > + if (val == 0) { > + s->mailbox_message_pending = false; > + } > + return; > + case A_K230_DDR_PHY_TRAINING_TRIGGER: > + if (val != 0) { > + s->training_trigger_seen = true; > + } else if (s->training_trigger_seen) { > + /* Abstract the loaded firmware run to its final mailbox message. */ > + s->training_trigger_seen = false; > + s->training_complete = true; > + s->mailbox_message_pending = true; > + } > + return; > + default: > + break; > + } > + > + if (FIELD_EX32(s->micro_cont_mux_sel, > + K230_DDR_PHY_MICRO_CONT_MUX_SEL, > + MICRO_CONT_MUX_SEL)) { > + return; > + } > + > + switch (addr) { > + case A_K230_DDR_PHY_DFI_INIT_COMPLETE: > + s->dfi_init_complete = > + val & R_K230_DDR_PHY_DFI_INIT_COMPLETE_DFI_INIT_COMPLETE_MASK; > + return; > + case A_K230_DDR_PHY_VREF_IN_GLOBAL: > + s->vref_in_global = val & UINT16_C(0x7fff); > + return; > + default: > + break; > + } > + > + if (k230_ddr_phy_decode_anib(addr, &anib)) { > + s->atx_impedance[anib] = val & UINT16_C(0x03ff); > + return; > + } > + > + if (k230_ddr_phy_decode_dbyte(addr, 0x049, &dbyte, &nibble)) { > + s->tx_impedance_ctrl1[dbyte][nibble] = val & UINT16_C(0x0fff); > + return; > + } > + > + if (k230_ddr_phy_decode_dbyte(addr, 0x04d, &dbyte, &nibble)) { > + s->tx_odt_drv_stren[dbyte][nibble] = val & UINT16_C(0x0fff); > + } > +} > + > +static const MemoryRegionOps k230_ddr_cfg_ops = { > + .read = k230_ddr_cfg_read, > + .write = k230_ddr_cfg_write, > + .endianness = DEVICE_LITTLE_ENDIAN, > + .valid = { > + .min_access_size = 4, > + .max_access_size = 4, > + .unaligned = false, > + }, > +}; > + > +static const MemoryRegionOps k230_ddr_phy_ops = { > + .read = k230_ddr_phy_read, > + .write = k230_ddr_phy_write, > + .endianness = DEVICE_LITTLE_ENDIAN, > + .valid = { > + .min_access_size = 4, > + .max_access_size = 4, > + .unaligned = false, > + }, > +}; > + > +static void k230_ddr_cfg_init(Object *obj) > +{ > + K230DDRCfgState *s = K230_DDR_CFG(obj); > + > + memory_region_init_io(&s->mmio, obj, &k230_ddr_cfg_ops, s, > + "k230-ddr-cfg", K230_DDRC_MMIO_SIZE); > + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); > +} > + > +static void k230_ddr_phy_init(Object *obj) > +{ > + K230DDRPhyState *s = K230_DDR_PHY(obj); > + > + memory_region_init_io(&s->mmio, obj, &k230_ddr_phy_ops, s, > + "k230-ddr-phy", K230_DDR_PHY_MMIO_SIZE); > + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); > +} > + > +static void k230_ddr_cfg_reset_enter(Object *obj, ResetType type) > +{ > + K230DDRCfgState *s = K230_DDR_CFG(obj); > + > + s->initialized = false; > + memcpy(s->regs, k230_ddrc_reset_values, sizeof(s->regs)); > +} > + > +static void k230_ddr_phy_reset_enter(Object *obj, ResetType type) > +{ > + K230DDRPhyState *s = K230_DDR_PHY(obj); > + unsigned int dbyte; > + unsigned int nibble; > + unsigned int anib; > + > + memset(s->tx_odt_drv_stren, 0, sizeof(s->tx_odt_drv_stren)); > + > + for (anib = 0; anib < ARRAY_SIZE(s->atx_impedance); anib++) { > + s->atx_impedance[anib] = K230_DDR_PHY_ATX_IMPEDANCE_RESET; > + } > + > + for (dbyte = 0; dbyte < ARRAY_SIZE(s->tx_impedance_ctrl1); dbyte++) { > + for (nibble = 0; > + nibble < ARRAY_SIZE(s->tx_impedance_ctrl1[dbyte]); nibble++) { > + s->tx_impedance_ctrl1[dbyte][nibble] = > + K230_DDR_PHY_TX_IMPEDANCE_CTRL1_RESET; > + } > + } > + > + s->dfi_init_complete = 0; > + s->vref_in_global = K230_DDR_PHY_VREF_IN_GLOBAL_RESET; > + s->micro_cont_mux_sel = 0; > + s->training_trigger_seen = false; > + s->training_complete = false; > + s->mailbox_message_pending = false; > +} > + > +static const VMStateDescription vmstate_k230_ddr_cfg = { > + .name = "k230-ddr-cfg", > + .version_id = 1, > + .minimum_version_id = 1, > + .fields = (const VMStateField[]) { > + VMSTATE_UINT32_ARRAY(regs, K230DDRCfgState, K230_DDRC_REG_COUNT), > + VMSTATE_BOOL(initialized, K230DDRCfgState), > + VMSTATE_END_OF_LIST() > + }, > +}; > + > +static const VMStateDescription vmstate_k230_ddr_phy = { > + .name = "k230-ddr-phy", > + .version_id = 1, > + .minimum_version_id = 1, > + .fields = (const VMStateField[]) { > + VMSTATE_UINT16_ARRAY(atx_impedance, K230DDRPhyState, > + K230_DDR_PHY_ANIB_COUNT), > + VMSTATE_UINT16_2DARRAY(tx_impedance_ctrl1, K230DDRPhyState, > + K230_DDR_PHY_DBYTE_COUNT, > + K230_DDR_PHY_NIBBLES_PER_DBYTE), > + VMSTATE_UINT16_2DARRAY(tx_odt_drv_stren, K230DDRPhyState, > + K230_DDR_PHY_DBYTE_COUNT, > + K230_DDR_PHY_NIBBLES_PER_DBYTE), > + VMSTATE_UINT16(dfi_init_complete, K230DDRPhyState), > + VMSTATE_UINT16(vref_in_global, K230DDRPhyState), > + VMSTATE_UINT16(micro_cont_mux_sel, K230DDRPhyState), > + VMSTATE_BOOL(training_trigger_seen, K230DDRPhyState), > + VMSTATE_BOOL(training_complete, K230DDRPhyState), > + VMSTATE_BOOL(mailbox_message_pending, K230DDRPhyState), > + VMSTATE_END_OF_LIST() > + }, > +}; > + > +static void k230_ddr_cfg_class_init(ObjectClass *klass, const void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + ResettableClass *rc = RESETTABLE_CLASS(klass); > + > + rc->phases.enter = k230_ddr_cfg_reset_enter; > + dc->vmsd = &vmstate_k230_ddr_cfg; > +} > + > +static void k230_ddr_phy_class_init(ObjectClass *klass, const void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + ResettableClass *rc = RESETTABLE_CLASS(klass); > + > + rc->phases.enter = k230_ddr_phy_reset_enter; > + dc->vmsd = &vmstate_k230_ddr_phy; > +} > + > +static const TypeInfo k230_ddr_types[] = { > + { > + .name = TYPE_K230_DDR_CFG, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_size = sizeof(K230DDRCfgState), > + .instance_init = k230_ddr_cfg_init, > + .class_init = k230_ddr_cfg_class_init, > + }, > + { > + .name = TYPE_K230_DDR_PHY, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_size = sizeof(K230DDRPhyState), > + .instance_init = k230_ddr_phy_init, > + .class_init = k230_ddr_phy_class_init, > + }, > +}; > + > +DEFINE_TYPES(k230_ddr_types) > diff --git a/hw/misc/meson.build b/hw/misc/meson.build > index 23265f6035..6d5e2b2647 100644 > --- a/hw/misc/meson.build > +++ b/hw/misc/meson.build > @@ -28,6 +28,7 @@ system_ss.add(when: 'CONFIG_IOSB', if_true: files('iosb.c')) > system_ss.add(when: 'CONFIG_VIRT_CTRL', if_true: files('virt_ctrl.c')) > > # RISC-V devices > +system_ss.add(when: 'CONFIG_K230', if_true: files('k230_ddr.c')) > system_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c')) > system_ss.add(when: 'CONFIG_MCHP_PFSOC_IOSCB', if_true: files('mchp_pfsoc_ioscb.c')) > system_ss.add(when: 'CONFIG_MCHP_PFSOC_SYSREG', if_true: files('mchp_pfsoc_sysreg.c')) > diff --git a/include/hw/misc/k230_ddr.h b/include/hw/misc/k230_ddr.h > new file mode 100644 > index 0000000000..d912e8e1b0 > --- /dev/null > +++ b/include/hw/misc/k230_ddr.h > @@ -0,0 +1,59 @@ > +/* > + * Kendryte K230 DDR controller and PHY models > + * > + * Device state and type declarations for the K230 DDRC CFG and K230 DDR PHY > + * registers. > + * > + * Copyright (c) 2026 Junze Cao <caojunze424@gmail.com> > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#ifndef HW_MISC_K230_DDR_H > +#define HW_MISC_K230_DDR_H > + > +#include "hw/core/sysbus.h" > + > +#define K230_DDRC_MMIO_SIZE 0x02000000 > +#define K230_DDR_PHY_MMIO_SIZE 0x00400000 > + > +#define K230_DDRC_REG_SIZE 0x328 > +#define K230_DDRC_REG_COUNT (K230_DDRC_REG_SIZE / sizeof(uint32_t)) > + > +#define K230_DDR_PHY_ANIB_COUNT 10 > +#define K230_DDR_PHY_DBYTE_COUNT 4 > +#define K230_DDR_PHY_NIBBLES_PER_DBYTE 2 > + > +#define TYPE_K230_DDR_CFG "riscv.k230.ddr-cfg" > +OBJECT_DECLARE_SIMPLE_TYPE(K230DDRCfgState, K230_DDR_CFG) > + > +#define TYPE_K230_DDR_PHY "riscv.k230.ddr-phy" > +OBJECT_DECLARE_SIMPLE_TYPE(K230DDRPhyState, K230_DDR_PHY) > + > +struct K230DDRCfgState { > + SysBusDevice parent_obj; > + > + MemoryRegion mmio; > + K230DDRPhyState *phy; > + uint32_t regs[K230_DDRC_REG_COUNT]; > + bool initialized; > +}; > + > +struct K230DDRPhyState { > + SysBusDevice parent_obj; > + > + MemoryRegion mmio; > + uint16_t atx_impedance[K230_DDR_PHY_ANIB_COUNT]; > + uint16_t tx_impedance_ctrl1[K230_DDR_PHY_DBYTE_COUNT] > + [K230_DDR_PHY_NIBBLES_PER_DBYTE]; > + uint16_t tx_odt_drv_stren[K230_DDR_PHY_DBYTE_COUNT] > + [K230_DDR_PHY_NIBBLES_PER_DBYTE]; > + uint16_t dfi_init_complete; > + uint16_t vref_in_global; > + uint16_t micro_cont_mux_sel; > + bool training_trigger_seen; > + bool training_complete; > + bool mailbox_message_pending; > +}; > + > +#endif > -- > 2.53.0 > ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/3] hw/riscv: Connect K230 DDR controller and PHY models 2026-07-16 13:24 [PATCH 0/3] riscv: Add K230 DDR controller and PHY models Junze Cao 2026-07-16 13:24 ` [PATCH 1/3] hw/misc: " Junze Cao @ 2026-07-16 13:24 ` Junze Cao 2026-07-22 20:08 ` Daniel Henrique Barboza 2026-07-23 8:42 ` Chao Liu 2026-07-16 13:24 ` [PATCH 3/3] tests/qtest: Add K230 DDR controller tests Junze Cao 2 siblings, 2 replies; 10+ messages in thread From: Junze Cao @ 2026-07-16 13:24 UTC (permalink / raw) To: qemu-devel Cc: qemu-riscv, chao.liu, pierrick.bouvier, palmer, alistair.francis, liwei1518, daniel.barboza, zhiwei_liu, farosas, lvivier, pbonzini, Junze Cao Replace the unimplemented K230 DDR configuration region with the DDRC model and map the PHY model at 0x9a000000. Connect the controller to the PHY so DFI status reflects PHY training and initialization state. Signed-off-by: Junze Cao <caojunze424@gmail.com> --- docs/system/riscv/k230.rst | 4 ++++ hw/riscv/k230.c | 19 ++++++++++++++++--- include/hw/riscv/k230.h | 4 ++++ 3 files changed, 24 insertions(+), 3 deletions(-) diff --git a/docs/system/riscv/k230.rst b/docs/system/riscv/k230.rst index cea8202e55..06a819fbdb 100644 --- a/docs/system/riscv/k230.rst +++ b/docs/system/riscv/k230.rst @@ -20,12 +20,16 @@ The ``k230`` machine supports the following devices: * Platform-Level Interrupt Controller (PLIC) * 2 K230 Watchdog Timer * 5 UART +* K230 DDRC CFG and DDR PHY Boot options ------------ The ``k230`` machine supports K230 SDK boot through M-mode U-Boot, which then starts OpenSBI/Linux with ``bootm``. It also supports direct Linux boot. +The DDRC CFG and DDR PHY models allow the K230 SDK U-Boot SPL to complete DDR +initialization before loading the next boot stage. + K230 SDK Linux kernels use T-HEAD C9xx private MAEE page table attributes. QEMU does not implement MAEE in the generic RISC-V MMU, so such kernels need to be built with standard RISC-V PTE bits before they can boot under QEMU. diff --git a/hw/riscv/k230.c b/hw/riscv/k230.c index 656f28190c..627150b463 100644 --- a/hw/riscv/k230.c +++ b/hw/riscv/k230.c @@ -97,6 +97,7 @@ static const MemMapEntry memmap[] = { [K230_DEV_SPI] = { 0x91584000, 0x00001000 }, [K230_DEV_HI_SYS_CFG] = { 0x91585000, 0x00000400 }, [K230_DEV_DDRC_CFG] = { 0x98000000, 0x02000000 }, + [K230_DEV_DDR_PHY] = { 0x9A000000, 0x00400000 }, [K230_DEV_FLASH] = { 0xC0000000, 0x08000000 }, [K230_DEV_PLIC] = { 0xF00000000, 0x00400000 }, [K230_DEV_CLINT] = { 0xF04000000, 0x00400000 }, @@ -108,6 +109,11 @@ static void k230_soc_init(Object *obj) RISCVHartArrayState *cpu0 = &s->c908_cpu; object_initialize_child(obj, "c908-cpu", cpu0, TYPE_RISCV_HART_ARRAY); + object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg, + TYPE_K230_DDR_CFG); + object_initialize_child(obj, "ddr-phy", &s->ddr_phy, + TYPE_K230_DDR_PHY); + s->ddr_cfg.phy = &s->ddr_phy; object_initialize_child(obj, "k230-wdt0", &s->wdt[0], TYPE_K230_WDT); object_initialize_child(obj, "k230-wdt1", &s->wdt[1], TYPE_K230_WDT); @@ -158,6 +164,16 @@ static void k230_soc_realize(DeviceState *dev, Error **errp) int c908_cpus; sysbus_realize(SYS_BUS_DEVICE(&s->c908_cpu), &error_fatal); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp)) { + return; + } + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ddr_phy), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0, + memmap[K230_DEV_DDRC_CFG].base); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_phy), 0, + memmap[K230_DEV_DDR_PHY].base); c908_cpus = s->c908_cpu.num_harts; @@ -361,9 +377,6 @@ static void k230_soc_realize(DeviceState *dev, Error **errp) create_unimplemented_device("hi_sys_cfg", memmap[K230_DEV_HI_SYS_CFG].base, memmap[K230_DEV_HI_SYS_CFG].size); - create_unimplemented_device("ddrc_cfg", memmap[K230_DEV_DDRC_CFG].base, - memmap[K230_DEV_DDRC_CFG].size); - create_unimplemented_device("flash", memmap[K230_DEV_FLASH].base, memmap[K230_DEV_FLASH].size); } diff --git a/include/hw/riscv/k230.h b/include/hw/riscv/k230.h index 592e1c26bf..80ca16338c 100644 --- a/include/hw/riscv/k230.h +++ b/include/hw/riscv/k230.h @@ -16,6 +16,7 @@ #define HW_K230_H #include "hw/core/boards.h" +#include "hw/misc/k230_ddr.h" #include "hw/riscv/riscv_hart.h" #include "hw/watchdog/k230_wdt.h" @@ -32,6 +33,8 @@ typedef struct K230SoCState { /*< public >*/ RISCVHartArrayState c908_cpu; /* Small core */ + K230DDRCfgState ddr_cfg; + K230DDRPhyState ddr_phy; K230WdtState wdt[2]; MemoryRegion sram; MemoryRegion bootrom; @@ -112,6 +115,7 @@ enum { K230_DEV_SPI, K230_DEV_HI_SYS_CFG, K230_DEV_DDRC_CFG, + K230_DEV_DDR_PHY, K230_DEV_FLASH, K230_DEV_PLIC, K230_DEV_CLINT, -- 2.53.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] hw/riscv: Connect K230 DDR controller and PHY models 2026-07-16 13:24 ` [PATCH 2/3] hw/riscv: Connect " Junze Cao @ 2026-07-22 20:08 ` Daniel Henrique Barboza 2026-07-23 8:42 ` Chao Liu 1 sibling, 0 replies; 10+ messages in thread From: Daniel Henrique Barboza @ 2026-07-22 20:08 UTC (permalink / raw) To: Junze Cao, qemu-devel Cc: qemu-riscv, chao.liu, pierrick.bouvier, palmer, alistair.francis, liwei1518, zhiwei_liu, farosas, lvivier, pbonzini On 7/16/2026 10:24 AM, Junze Cao wrote: > Replace the unimplemented K230 DDR configuration region with the DDRC > model and map the PHY model at 0x9a000000. > > Connect the controller to the PHY so DFI status reflects PHY training and > initialization state. > > Signed-off-by: Junze Cao <caojunze424@gmail.com> > --- Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> > docs/system/riscv/k230.rst | 4 ++++ > hw/riscv/k230.c | 19 ++++++++++++++++--- > include/hw/riscv/k230.h | 4 ++++ > 3 files changed, 24 insertions(+), 3 deletions(-) > > diff --git a/docs/system/riscv/k230.rst b/docs/system/riscv/k230.rst > index cea8202e55..06a819fbdb 100644 > --- a/docs/system/riscv/k230.rst > +++ b/docs/system/riscv/k230.rst > @@ -20,12 +20,16 @@ The ``k230`` machine supports the following devices: > * Platform-Level Interrupt Controller (PLIC) > * 2 K230 Watchdog Timer > * 5 UART > +* K230 DDRC CFG and DDR PHY > > Boot options > ------------ > The ``k230`` machine supports K230 SDK boot through M-mode U-Boot, which then > starts OpenSBI/Linux with ``bootm``. It also supports direct Linux boot. > > +The DDRC CFG and DDR PHY models allow the K230 SDK U-Boot SPL to complete DDR > +initialization before loading the next boot stage. > + > K230 SDK Linux kernels use T-HEAD C9xx private MAEE page table attributes. QEMU > does not implement MAEE in the generic RISC-V MMU, so such kernels need to be > built with standard RISC-V PTE bits before they can boot under QEMU. > diff --git a/hw/riscv/k230.c b/hw/riscv/k230.c > index 656f28190c..627150b463 100644 > --- a/hw/riscv/k230.c > +++ b/hw/riscv/k230.c > @@ -97,6 +97,7 @@ static const MemMapEntry memmap[] = { > [K230_DEV_SPI] = { 0x91584000, 0x00001000 }, > [K230_DEV_HI_SYS_CFG] = { 0x91585000, 0x00000400 }, > [K230_DEV_DDRC_CFG] = { 0x98000000, 0x02000000 }, > + [K230_DEV_DDR_PHY] = { 0x9A000000, 0x00400000 }, > [K230_DEV_FLASH] = { 0xC0000000, 0x08000000 }, > [K230_DEV_PLIC] = { 0xF00000000, 0x00400000 }, > [K230_DEV_CLINT] = { 0xF04000000, 0x00400000 }, > @@ -108,6 +109,11 @@ static void k230_soc_init(Object *obj) > RISCVHartArrayState *cpu0 = &s->c908_cpu; > > object_initialize_child(obj, "c908-cpu", cpu0, TYPE_RISCV_HART_ARRAY); > + object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg, > + TYPE_K230_DDR_CFG); > + object_initialize_child(obj, "ddr-phy", &s->ddr_phy, > + TYPE_K230_DDR_PHY); > + s->ddr_cfg.phy = &s->ddr_phy; > object_initialize_child(obj, "k230-wdt0", &s->wdt[0], TYPE_K230_WDT); > object_initialize_child(obj, "k230-wdt1", &s->wdt[1], TYPE_K230_WDT); > > @@ -158,6 +164,16 @@ static void k230_soc_realize(DeviceState *dev, Error **errp) > int c908_cpus; > > sysbus_realize(SYS_BUS_DEVICE(&s->c908_cpu), &error_fatal); > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp)) { > + return; > + } > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ddr_phy), errp)) { > + return; > + } > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0, > + memmap[K230_DEV_DDRC_CFG].base); > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_phy), 0, > + memmap[K230_DEV_DDR_PHY].base); > > c908_cpus = s->c908_cpu.num_harts; > > @@ -361,9 +377,6 @@ static void k230_soc_realize(DeviceState *dev, Error **errp) > create_unimplemented_device("hi_sys_cfg", memmap[K230_DEV_HI_SYS_CFG].base, > memmap[K230_DEV_HI_SYS_CFG].size); > > - create_unimplemented_device("ddrc_cfg", memmap[K230_DEV_DDRC_CFG].base, > - memmap[K230_DEV_DDRC_CFG].size); > - > create_unimplemented_device("flash", memmap[K230_DEV_FLASH].base, > memmap[K230_DEV_FLASH].size); > } > diff --git a/include/hw/riscv/k230.h b/include/hw/riscv/k230.h > index 592e1c26bf..80ca16338c 100644 > --- a/include/hw/riscv/k230.h > +++ b/include/hw/riscv/k230.h > @@ -16,6 +16,7 @@ > #define HW_K230_H > > #include "hw/core/boards.h" > +#include "hw/misc/k230_ddr.h" > #include "hw/riscv/riscv_hart.h" > #include "hw/watchdog/k230_wdt.h" > > @@ -32,6 +33,8 @@ typedef struct K230SoCState { > /*< public >*/ > RISCVHartArrayState c908_cpu; /* Small core */ > > + K230DDRCfgState ddr_cfg; > + K230DDRPhyState ddr_phy; > K230WdtState wdt[2]; > MemoryRegion sram; > MemoryRegion bootrom; > @@ -112,6 +115,7 @@ enum { > K230_DEV_SPI, > K230_DEV_HI_SYS_CFG, > K230_DEV_DDRC_CFG, > + K230_DEV_DDR_PHY, > K230_DEV_FLASH, > K230_DEV_PLIC, > K230_DEV_CLINT, ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] hw/riscv: Connect K230 DDR controller and PHY models 2026-07-16 13:24 ` [PATCH 2/3] hw/riscv: Connect " Junze Cao 2026-07-22 20:08 ` Daniel Henrique Barboza @ 2026-07-23 8:42 ` Chao Liu 1 sibling, 0 replies; 10+ messages in thread From: Chao Liu @ 2026-07-23 8:42 UTC (permalink / raw) To: Junze Cao Cc: qemu-devel, qemu-riscv, pierrick.bouvier, palmer, alistair.francis, liwei1518, daniel.barboza, zhiwei_liu, farosas, lvivier, pbonzini On Thu, Jul 16, 2026 at 09:24:22PM +0800, Junze Cao wrote: > Replace the unimplemented K230 DDR configuration region with the DDRC > model and map the PHY model at 0x9a000000. > > Connect the controller to the PHY so DFI status reflects PHY training and > initialization state. > > Signed-off-by: Junze Cao <caojunze424@gmail.com> Suggested-by: Chao Liu <chao.liu@processmission.com> Thanks, Chao > --- > docs/system/riscv/k230.rst | 4 ++++ > hw/riscv/k230.c | 19 ++++++++++++++++--- > include/hw/riscv/k230.h | 4 ++++ > 3 files changed, 24 insertions(+), 3 deletions(-) > > diff --git a/docs/system/riscv/k230.rst b/docs/system/riscv/k230.rst > index cea8202e55..06a819fbdb 100644 > --- a/docs/system/riscv/k230.rst > +++ b/docs/system/riscv/k230.rst > @@ -20,12 +20,16 @@ The ``k230`` machine supports the following devices: > * Platform-Level Interrupt Controller (PLIC) > * 2 K230 Watchdog Timer > * 5 UART > +* K230 DDRC CFG and DDR PHY > > Boot options > ------------ > The ``k230`` machine supports K230 SDK boot through M-mode U-Boot, which then > starts OpenSBI/Linux with ``bootm``. It also supports direct Linux boot. > > +The DDRC CFG and DDR PHY models allow the K230 SDK U-Boot SPL to complete DDR > +initialization before loading the next boot stage. > + > K230 SDK Linux kernels use T-HEAD C9xx private MAEE page table attributes. QEMU > does not implement MAEE in the generic RISC-V MMU, so such kernels need to be > built with standard RISC-V PTE bits before they can boot under QEMU. > diff --git a/hw/riscv/k230.c b/hw/riscv/k230.c > index 656f28190c..627150b463 100644 > --- a/hw/riscv/k230.c > +++ b/hw/riscv/k230.c > @@ -97,6 +97,7 @@ static const MemMapEntry memmap[] = { > [K230_DEV_SPI] = { 0x91584000, 0x00001000 }, > [K230_DEV_HI_SYS_CFG] = { 0x91585000, 0x00000400 }, > [K230_DEV_DDRC_CFG] = { 0x98000000, 0x02000000 }, > + [K230_DEV_DDR_PHY] = { 0x9A000000, 0x00400000 }, > [K230_DEV_FLASH] = { 0xC0000000, 0x08000000 }, > [K230_DEV_PLIC] = { 0xF00000000, 0x00400000 }, > [K230_DEV_CLINT] = { 0xF04000000, 0x00400000 }, > @@ -108,6 +109,11 @@ static void k230_soc_init(Object *obj) > RISCVHartArrayState *cpu0 = &s->c908_cpu; > > object_initialize_child(obj, "c908-cpu", cpu0, TYPE_RISCV_HART_ARRAY); > + object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg, > + TYPE_K230_DDR_CFG); > + object_initialize_child(obj, "ddr-phy", &s->ddr_phy, > + TYPE_K230_DDR_PHY); > + s->ddr_cfg.phy = &s->ddr_phy; > object_initialize_child(obj, "k230-wdt0", &s->wdt[0], TYPE_K230_WDT); > object_initialize_child(obj, "k230-wdt1", &s->wdt[1], TYPE_K230_WDT); > > @@ -158,6 +164,16 @@ static void k230_soc_realize(DeviceState *dev, Error **errp) > int c908_cpus; > > sysbus_realize(SYS_BUS_DEVICE(&s->c908_cpu), &error_fatal); > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp)) { > + return; > + } > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ddr_phy), errp)) { > + return; > + } > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0, > + memmap[K230_DEV_DDRC_CFG].base); > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_phy), 0, > + memmap[K230_DEV_DDR_PHY].base); > > c908_cpus = s->c908_cpu.num_harts; > > @@ -361,9 +377,6 @@ static void k230_soc_realize(DeviceState *dev, Error **errp) > create_unimplemented_device("hi_sys_cfg", memmap[K230_DEV_HI_SYS_CFG].base, > memmap[K230_DEV_HI_SYS_CFG].size); > > - create_unimplemented_device("ddrc_cfg", memmap[K230_DEV_DDRC_CFG].base, > - memmap[K230_DEV_DDRC_CFG].size); > - > create_unimplemented_device("flash", memmap[K230_DEV_FLASH].base, > memmap[K230_DEV_FLASH].size); > } > diff --git a/include/hw/riscv/k230.h b/include/hw/riscv/k230.h > index 592e1c26bf..80ca16338c 100644 > --- a/include/hw/riscv/k230.h > +++ b/include/hw/riscv/k230.h > @@ -16,6 +16,7 @@ > #define HW_K230_H > > #include "hw/core/boards.h" > +#include "hw/misc/k230_ddr.h" > #include "hw/riscv/riscv_hart.h" > #include "hw/watchdog/k230_wdt.h" > > @@ -32,6 +33,8 @@ typedef struct K230SoCState { > /*< public >*/ > RISCVHartArrayState c908_cpu; /* Small core */ > > + K230DDRCfgState ddr_cfg; > + K230DDRPhyState ddr_phy; > K230WdtState wdt[2]; > MemoryRegion sram; > MemoryRegion bootrom; > @@ -112,6 +115,7 @@ enum { > K230_DEV_SPI, > K230_DEV_HI_SYS_CFG, > K230_DEV_DDRC_CFG, > + K230_DEV_DDR_PHY, > K230_DEV_FLASH, > K230_DEV_PLIC, > K230_DEV_CLINT, > -- > 2.53.0 > ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/3] tests/qtest: Add K230 DDR controller tests 2026-07-16 13:24 [PATCH 0/3] riscv: Add K230 DDR controller and PHY models Junze Cao 2026-07-16 13:24 ` [PATCH 1/3] hw/misc: " Junze Cao 2026-07-16 13:24 ` [PATCH 2/3] hw/riscv: Connect " Junze Cao @ 2026-07-16 13:24 ` Junze Cao 2026-07-22 20:16 ` Daniel Henrique Barboza 2026-07-23 8:42 ` Chao Liu 2 siblings, 2 replies; 10+ messages in thread From: Junze Cao @ 2026-07-16 13:24 UTC (permalink / raw) To: qemu-devel Cc: qemu-riscv, chao.liu, pierrick.bouvier, palmer, alistair.francis, liwei1518, daniel.barboza, zhiwei_liu, farosas, lvivier, pbonzini, Junze Cao Add qtests for DDRC and PHY reset values, register access policy, the software-update handshake, and PHY register ownership. Exercise PHY training and mailbox acknowledgement through the DFI initialization sequence. Include negative coverage to ensure DFI cannot complete before PHY training or enter Normal mode before completion is enabled. Signed-off-by: Junze Cao <caojunze424@gmail.com> --- MAINTAINERS | 1 + tests/qtest/k230-ddr-test.c | 226 ++++++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 3 +- 3 files changed, 229 insertions(+), 1 deletion(-) create mode 100644 tests/qtest/k230-ddr-test.c diff --git a/MAINTAINERS b/MAINTAINERS index 1cb3ef6c02..ace7def55e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1833,6 +1833,7 @@ F: include/hw/misc/k230_ddr.h F: include/hw/riscv/k230.h F: include/hw/watchdog/k230_wdt.h F: tests/functional/riscv64/test_k230.py +F: tests/qtest/k230-ddr-test.c F: tests/qtest/k230-wdt-test.c RX Machines diff --git a/tests/qtest/k230-ddr-test.c b/tests/qtest/k230-ddr-test.c new file mode 100644 index 0000000000..72362929bc --- /dev/null +++ b/tests/qtest/k230-ddr-test.c @@ -0,0 +1,226 @@ +/* + * QTest testcase for the K230 DDR controller and PHY + * + * Exercises register access, reset, PHY ownership, training mailbox, and DFI + * initialization. + * + * Copyright (c) 2026 Junze Cao <caojunze424@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "libqtest.h" + +#define K230_DDRC_BASE UINT64_C(0x98000000) +#define K230_DDR_PHY_BASE UINT64_C(0x9a000000) + +#define K230_DDRC_MSTR 0x000 +#define K230_DDRC_STAT 0x004 +#define K230_DDRC_DRAMTMG4 0x110 +#define K230_DDRC_DFIMISC 0x1b0 +#define K230_DDRC_DFISTAT 0x1bc +#define K230_DDRC_SWCTL 0x320 +#define K230_DDRC_SWSTAT 0x324 + +#define K230_DDRC_STAT_OPERATING_MODE_MASK 0x7 +#define K230_DDRC_DFISTAT_DFI_INIT_COMPLETE_MASK 0x1 + +#define K230_DDR_PHY_CSR(index) \ + (K230_DDR_PHY_BASE + (uint64_t)(index) * sizeof(uint32_t)) + +#define K230_DDR_PHY_ATX_IMPEDANCE 0x00043 +#define K230_DDR_PHY_TX_IMPEDANCE_CTRL1 0x10049 +#define K230_DDR_PHY_VREF_IN_GLOBAL 0x200b2 +#define K230_DDR_PHY_MICRO_CONT_MUX_SEL 0xd0000 +#define K230_DDR_PHY_TRAINING_STATUS 0xd0004 +#define K230_DDR_PHY_TRAINING_ACK 0xd0031 +#define K230_DDR_PHY_TRAINING_MESSAGE 0xd0032 +#define K230_DDR_PHY_TRAINING_TRIGGER 0xd0099 + +static void complete_phy_training(QTestState *qts) +{ + qtest_writel(qts, + K230_DDR_PHY_CSR(K230_DDR_PHY_MICRO_CONT_MUX_SEL), 1); + qtest_writel(qts, K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_TRIGGER), 9); + qtest_writel(qts, K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_TRIGGER), 1); + qtest_writel(qts, K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_TRIGGER), 0); +} + +static void test_reset_and_register_access(void) +{ + QTestState *qts = qtest_init("-machine k230"); + + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_MSTR), + ==, 0x01040000); + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_STAT), + ==, 0x00000000); + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_DRAMTMG4), + ==, 0x05040405); + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_DFIMISC), + ==, 0x00000001); + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_SWCTL), + ==, 0x00000001); + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_SWSTAT), + ==, 0x00000001); + + g_assert_cmphex(qtest_readl(qts, + K230_DDR_PHY_CSR(K230_DDR_PHY_ATX_IMPEDANCE)), + ==, 0x03ff); + g_assert_cmphex(qtest_readl(qts, + K230_DDR_PHY_CSR(K230_DDR_PHY_TX_IMPEDANCE_CTRL1)), + ==, 0x0fff); + g_assert_cmphex(qtest_readl(qts, + K230_DDR_PHY_CSR(K230_DDR_PHY_VREF_IN_GLOBAL)), + ==, 0x0200); + + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_MSTR, 0x01040008); + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_MSTR), + ==, 0x01040008); + + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_STAT, 0xffffffff); + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_STAT), + ==, 0x00000000); + + qtest_writel(qts, K230_DDR_PHY_CSR(K230_DDR_PHY_VREF_IN_GLOBAL), + 0xffffffff); + g_assert_cmphex(qtest_readl(qts, + K230_DDR_PHY_CSR(K230_DDR_PHY_VREF_IN_GLOBAL)), + ==, 0x7fff); + + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_DRAMTMG4, 0); + + qtest_system_reset(qts); + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_MSTR), + ==, 0x01040000); + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_DRAMTMG4), + ==, 0x05040405); + g_assert_cmphex(qtest_readl(qts, + K230_DDR_PHY_CSR(K230_DDR_PHY_VREF_IN_GLOBAL)), + ==, 0x0200); + + qtest_quit(qts); +} + +static void test_software_update_handshake(void) +{ + QTestState *qts = qtest_init("-machine k230"); + + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_SWCTL, 0); + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_SWSTAT), + ==, 0); + + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_SWCTL, 1); + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_SWSTAT), + ==, 1); + + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_SWSTAT, 0); + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_SWSTAT), + ==, 1); + + qtest_quit(qts); +} + +static void test_phy_ownership(void) +{ + QTestState *qts = qtest_init("-machine k230"); + uint64_t atx = K230_DDR_PHY_CSR(K230_DDR_PHY_ATX_IMPEDANCE); + uint64_t mux = K230_DDR_PHY_CSR(K230_DDR_PHY_MICRO_CONT_MUX_SEL); + + qtest_writel(qts, atx, 0x155); + g_assert_cmphex(qtest_readl(qts, atx), ==, 0x155); + + qtest_writel(qts, mux, 1); + qtest_writel(qts, atx, 0x2aa); + g_assert_cmphex(qtest_readl(qts, atx), ==, 0x155); + + qtest_writel(qts, mux, 0); + qtest_writel(qts, atx, 0x2aa); + g_assert_cmphex(qtest_readl(qts, atx), ==, 0x2aa); + + qtest_quit(qts); +} + +static void test_dfi_prerequisites(void) +{ + QTestState *qts = qtest_init("-machine k230"); + + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_DFIMISC, 0x20); + + g_assert_cmphex(qtest_readl(qts, + K230_DDRC_BASE + K230_DDRC_DFISTAT) & + K230_DDRC_DFISTAT_DFI_INIT_COMPLETE_MASK, + ==, 0); + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_STAT) & + K230_DDRC_STAT_OPERATING_MODE_MASK, + ==, 0); + + qtest_quit(qts); +} + +static void test_dfi_complete_enable(void) +{ + QTestState *qts = qtest_init("-machine k230"); + + complete_phy_training(qts); + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_DFIMISC, 0x20); + + g_assert_cmphex(qtest_readl(qts, + K230_DDRC_BASE + K230_DDRC_DFISTAT) & + K230_DDRC_DFISTAT_DFI_INIT_COMPLETE_MASK, + ==, 1); + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_STAT) & + K230_DDRC_STAT_OPERATING_MODE_MASK, + ==, 0); + + qtest_quit(qts); +} + +static void test_training_and_dfi_handshake(void) +{ + QTestState *qts = qtest_init("-machine k230"); + + complete_phy_training(qts); + + g_assert_cmphex(qtest_readl(qts, + K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_STATUS)), + ==, 0); + g_assert_cmphex(qtest_readl(qts, + K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_MESSAGE)), + ==, 0x07); + + qtest_writel(qts, K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_ACK), 0); + g_assert_cmphex(qtest_readl(qts, + K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_STATUS)), + ==, 1); + qtest_writel(qts, K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_ACK), 1); + + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_DFIMISC, 0x20); + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_DFISTAT), + ==, 1); + + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_DFIMISC, 0); + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_DFIMISC, 1); + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_STAT) & 0x7, + ==, 1); + + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/k230-ddr/reset-and-register-access", + test_reset_and_register_access); + qtest_add_func("/k230-ddr/software-update-handshake", + test_software_update_handshake); + qtest_add_func("/k230-ddr/phy-ownership", test_phy_ownership); + qtest_add_func("/k230-ddr/dfi-prerequisites", test_dfi_prerequisites); + qtest_add_func("/k230-ddr/dfi-complete-enable", + test_dfi_complete_enable); + qtest_add_func("/k230-ddr/training-and-dfi-handshake", + test_training_and_dfi_handshake); + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 56ff860e21..dc110f72c8 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -297,7 +297,8 @@ qtests_riscv64 = ['riscv-csr-test'] + \ (config_all_devices.has_key('CONFIG_IOMMU_TESTDEV') and config_all_devices.has_key('CONFIG_RISCV_IOMMU') ? ['iommu-riscv-test'] : []) + \ - (config_all_devices.has_key('CONFIG_K230') ? ['k230-wdt-test'] : []) + (config_all_devices.has_key('CONFIG_K230') ? + ['k230-ddr-test', 'k230-wdt-test'] : []) qtests_hexagon = ['boot-serial-test'] -- 2.53.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] tests/qtest: Add K230 DDR controller tests 2026-07-16 13:24 ` [PATCH 3/3] tests/qtest: Add K230 DDR controller tests Junze Cao @ 2026-07-22 20:16 ` Daniel Henrique Barboza 2026-07-23 8:42 ` Chao Liu 1 sibling, 0 replies; 10+ messages in thread From: Daniel Henrique Barboza @ 2026-07-22 20:16 UTC (permalink / raw) To: Junze Cao, qemu-devel Cc: qemu-riscv, chao.liu, pierrick.bouvier, palmer, alistair.francis, liwei1518, zhiwei_liu, farosas, lvivier, pbonzini On 7/16/2026 10:24 AM, Junze Cao wrote: > Add qtests for DDRC and PHY reset values, register access policy, the > software-update handshake, and PHY register ownership. > > Exercise PHY training and mailbox acknowledgement through the DFI > initialization sequence. Include negative coverage to ensure DFI cannot > complete before PHY training or enter Normal mode before completion is > enabled. > > Signed-off-by: Junze Cao <caojunze424@gmail.com> > --- Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> > MAINTAINERS | 1 + > tests/qtest/k230-ddr-test.c | 226 ++++++++++++++++++++++++++++++++++++ > tests/qtest/meson.build | 3 +- > 3 files changed, 229 insertions(+), 1 deletion(-) > create mode 100644 tests/qtest/k230-ddr-test.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 1cb3ef6c02..ace7def55e 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1833,6 +1833,7 @@ F: include/hw/misc/k230_ddr.h > F: include/hw/riscv/k230.h > F: include/hw/watchdog/k230_wdt.h > F: tests/functional/riscv64/test_k230.py > +F: tests/qtest/k230-ddr-test.c > F: tests/qtest/k230-wdt-test.c > > RX Machines > diff --git a/tests/qtest/k230-ddr-test.c b/tests/qtest/k230-ddr-test.c > new file mode 100644 > index 0000000000..72362929bc > --- /dev/null > +++ b/tests/qtest/k230-ddr-test.c > @@ -0,0 +1,226 @@ > +/* > + * QTest testcase for the K230 DDR controller and PHY > + * > + * Exercises register access, reset, PHY ownership, training mailbox, and DFI > + * initialization. > + * > + * Copyright (c) 2026 Junze Cao <caojunze424@gmail.com> > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#include "qemu/osdep.h" > +#include "libqtest.h" > + > +#define K230_DDRC_BASE UINT64_C(0x98000000) > +#define K230_DDR_PHY_BASE UINT64_C(0x9a000000) > + > +#define K230_DDRC_MSTR 0x000 > +#define K230_DDRC_STAT 0x004 > +#define K230_DDRC_DRAMTMG4 0x110 > +#define K230_DDRC_DFIMISC 0x1b0 > +#define K230_DDRC_DFISTAT 0x1bc > +#define K230_DDRC_SWCTL 0x320 > +#define K230_DDRC_SWSTAT 0x324 > + > +#define K230_DDRC_STAT_OPERATING_MODE_MASK 0x7 > +#define K230_DDRC_DFISTAT_DFI_INIT_COMPLETE_MASK 0x1 > + > +#define K230_DDR_PHY_CSR(index) \ > + (K230_DDR_PHY_BASE + (uint64_t)(index) * sizeof(uint32_t)) > + > +#define K230_DDR_PHY_ATX_IMPEDANCE 0x00043 > +#define K230_DDR_PHY_TX_IMPEDANCE_CTRL1 0x10049 > +#define K230_DDR_PHY_VREF_IN_GLOBAL 0x200b2 > +#define K230_DDR_PHY_MICRO_CONT_MUX_SEL 0xd0000 > +#define K230_DDR_PHY_TRAINING_STATUS 0xd0004 > +#define K230_DDR_PHY_TRAINING_ACK 0xd0031 > +#define K230_DDR_PHY_TRAINING_MESSAGE 0xd0032 > +#define K230_DDR_PHY_TRAINING_TRIGGER 0xd0099 > + > +static void complete_phy_training(QTestState *qts) > +{ > + qtest_writel(qts, > + K230_DDR_PHY_CSR(K230_DDR_PHY_MICRO_CONT_MUX_SEL), 1); > + qtest_writel(qts, K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_TRIGGER), 9); > + qtest_writel(qts, K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_TRIGGER), 1); > + qtest_writel(qts, K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_TRIGGER), 0); > +} > + > +static void test_reset_and_register_access(void) > +{ > + QTestState *qts = qtest_init("-machine k230"); > + > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_MSTR), > + ==, 0x01040000); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_STAT), > + ==, 0x00000000); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_DRAMTMG4), > + ==, 0x05040405); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_DFIMISC), > + ==, 0x00000001); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_SWCTL), > + ==, 0x00000001); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_SWSTAT), > + ==, 0x00000001); > + > + g_assert_cmphex(qtest_readl(qts, > + K230_DDR_PHY_CSR(K230_DDR_PHY_ATX_IMPEDANCE)), > + ==, 0x03ff); > + g_assert_cmphex(qtest_readl(qts, > + K230_DDR_PHY_CSR(K230_DDR_PHY_TX_IMPEDANCE_CTRL1)), > + ==, 0x0fff); > + g_assert_cmphex(qtest_readl(qts, > + K230_DDR_PHY_CSR(K230_DDR_PHY_VREF_IN_GLOBAL)), > + ==, 0x0200); > + > + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_MSTR, 0x01040008); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_MSTR), > + ==, 0x01040008); > + > + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_STAT, 0xffffffff); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_STAT), > + ==, 0x00000000); > + > + qtest_writel(qts, K230_DDR_PHY_CSR(K230_DDR_PHY_VREF_IN_GLOBAL), > + 0xffffffff); > + g_assert_cmphex(qtest_readl(qts, > + K230_DDR_PHY_CSR(K230_DDR_PHY_VREF_IN_GLOBAL)), > + ==, 0x7fff); > + > + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_DRAMTMG4, 0); > + > + qtest_system_reset(qts); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_MSTR), > + ==, 0x01040000); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_DRAMTMG4), > + ==, 0x05040405); > + g_assert_cmphex(qtest_readl(qts, > + K230_DDR_PHY_CSR(K230_DDR_PHY_VREF_IN_GLOBAL)), > + ==, 0x0200); > + > + qtest_quit(qts); > +} > + > +static void test_software_update_handshake(void) > +{ > + QTestState *qts = qtest_init("-machine k230"); > + > + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_SWCTL, 0); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_SWSTAT), > + ==, 0); > + > + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_SWCTL, 1); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_SWSTAT), > + ==, 1); > + > + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_SWSTAT, 0); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_SWSTAT), > + ==, 1); > + > + qtest_quit(qts); > +} > + > +static void test_phy_ownership(void) > +{ > + QTestState *qts = qtest_init("-machine k230"); > + uint64_t atx = K230_DDR_PHY_CSR(K230_DDR_PHY_ATX_IMPEDANCE); > + uint64_t mux = K230_DDR_PHY_CSR(K230_DDR_PHY_MICRO_CONT_MUX_SEL); > + > + qtest_writel(qts, atx, 0x155); > + g_assert_cmphex(qtest_readl(qts, atx), ==, 0x155); > + > + qtest_writel(qts, mux, 1); > + qtest_writel(qts, atx, 0x2aa); > + g_assert_cmphex(qtest_readl(qts, atx), ==, 0x155); > + > + qtest_writel(qts, mux, 0); > + qtest_writel(qts, atx, 0x2aa); > + g_assert_cmphex(qtest_readl(qts, atx), ==, 0x2aa); > + > + qtest_quit(qts); > +} > + > +static void test_dfi_prerequisites(void) > +{ > + QTestState *qts = qtest_init("-machine k230"); > + > + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_DFIMISC, 0x20); > + > + g_assert_cmphex(qtest_readl(qts, > + K230_DDRC_BASE + K230_DDRC_DFISTAT) & > + K230_DDRC_DFISTAT_DFI_INIT_COMPLETE_MASK, > + ==, 0); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_STAT) & > + K230_DDRC_STAT_OPERATING_MODE_MASK, > + ==, 0); > + > + qtest_quit(qts); > +} > + > +static void test_dfi_complete_enable(void) > +{ > + QTestState *qts = qtest_init("-machine k230"); > + > + complete_phy_training(qts); > + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_DFIMISC, 0x20); > + > + g_assert_cmphex(qtest_readl(qts, > + K230_DDRC_BASE + K230_DDRC_DFISTAT) & > + K230_DDRC_DFISTAT_DFI_INIT_COMPLETE_MASK, > + ==, 1); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_STAT) & > + K230_DDRC_STAT_OPERATING_MODE_MASK, > + ==, 0); > + > + qtest_quit(qts); > +} > + > +static void test_training_and_dfi_handshake(void) > +{ > + QTestState *qts = qtest_init("-machine k230"); > + > + complete_phy_training(qts); > + > + g_assert_cmphex(qtest_readl(qts, > + K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_STATUS)), > + ==, 0); > + g_assert_cmphex(qtest_readl(qts, > + K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_MESSAGE)), > + ==, 0x07); > + > + qtest_writel(qts, K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_ACK), 0); > + g_assert_cmphex(qtest_readl(qts, > + K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_STATUS)), > + ==, 1); > + qtest_writel(qts, K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_ACK), 1); > + > + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_DFIMISC, 0x20); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_DFISTAT), > + ==, 1); > + > + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_DFIMISC, 0); > + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_DFIMISC, 1); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_STAT) & 0x7, > + ==, 1); > + > + qtest_quit(qts); > +} > + > +int main(int argc, char **argv) > +{ > + g_test_init(&argc, &argv, NULL); > + > + qtest_add_func("/k230-ddr/reset-and-register-access", > + test_reset_and_register_access); > + qtest_add_func("/k230-ddr/software-update-handshake", > + test_software_update_handshake); > + qtest_add_func("/k230-ddr/phy-ownership", test_phy_ownership); > + qtest_add_func("/k230-ddr/dfi-prerequisites", test_dfi_prerequisites); > + qtest_add_func("/k230-ddr/dfi-complete-enable", > + test_dfi_complete_enable); > + qtest_add_func("/k230-ddr/training-and-dfi-handshake", > + test_training_and_dfi_handshake); > + > + return g_test_run(); > +} > diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build > index 56ff860e21..dc110f72c8 100644 > --- a/tests/qtest/meson.build > +++ b/tests/qtest/meson.build > @@ -297,7 +297,8 @@ qtests_riscv64 = ['riscv-csr-test'] + \ > (config_all_devices.has_key('CONFIG_IOMMU_TESTDEV') and > config_all_devices.has_key('CONFIG_RISCV_IOMMU') ? > ['iommu-riscv-test'] : []) + \ > - (config_all_devices.has_key('CONFIG_K230') ? ['k230-wdt-test'] : []) > + (config_all_devices.has_key('CONFIG_K230') ? > + ['k230-ddr-test', 'k230-wdt-test'] : []) > > qtests_hexagon = ['boot-serial-test'] > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] tests/qtest: Add K230 DDR controller tests 2026-07-16 13:24 ` [PATCH 3/3] tests/qtest: Add K230 DDR controller tests Junze Cao 2026-07-22 20:16 ` Daniel Henrique Barboza @ 2026-07-23 8:42 ` Chao Liu 1 sibling, 0 replies; 10+ messages in thread From: Chao Liu @ 2026-07-23 8:42 UTC (permalink / raw) To: Junze Cao Cc: qemu-devel, qemu-riscv, pierrick.bouvier, palmer, alistair.francis, liwei1518, daniel.barboza, zhiwei_liu, farosas, lvivier, pbonzini On Thu, Jul 16, 2026 at 09:24:23PM +0800, Junze Cao wrote: > Add qtests for DDRC and PHY reset values, register access policy, the > software-update handshake, and PHY register ownership. > > Exercise PHY training and mailbox acknowledgement through the DFI > initialization sequence. Include negative coverage to ensure DFI cannot > complete before PHY training or enter Normal mode before completion is > enabled. > > Signed-off-by: Junze Cao <caojunze424@gmail.com> Suggested-by: Chao Liu <chao.liu@processmission.com> Thanks, Chao > --- > MAINTAINERS | 1 + > tests/qtest/k230-ddr-test.c | 226 ++++++++++++++++++++++++++++++++++++ > tests/qtest/meson.build | 3 +- > 3 files changed, 229 insertions(+), 1 deletion(-) > create mode 100644 tests/qtest/k230-ddr-test.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 1cb3ef6c02..ace7def55e 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1833,6 +1833,7 @@ F: include/hw/misc/k230_ddr.h > F: include/hw/riscv/k230.h > F: include/hw/watchdog/k230_wdt.h > F: tests/functional/riscv64/test_k230.py > +F: tests/qtest/k230-ddr-test.c > F: tests/qtest/k230-wdt-test.c > > RX Machines > diff --git a/tests/qtest/k230-ddr-test.c b/tests/qtest/k230-ddr-test.c > new file mode 100644 > index 0000000000..72362929bc > --- /dev/null > +++ b/tests/qtest/k230-ddr-test.c > @@ -0,0 +1,226 @@ > +/* > + * QTest testcase for the K230 DDR controller and PHY > + * > + * Exercises register access, reset, PHY ownership, training mailbox, and DFI > + * initialization. > + * > + * Copyright (c) 2026 Junze Cao <caojunze424@gmail.com> > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#include "qemu/osdep.h" > +#include "libqtest.h" > + > +#define K230_DDRC_BASE UINT64_C(0x98000000) > +#define K230_DDR_PHY_BASE UINT64_C(0x9a000000) > + > +#define K230_DDRC_MSTR 0x000 > +#define K230_DDRC_STAT 0x004 > +#define K230_DDRC_DRAMTMG4 0x110 > +#define K230_DDRC_DFIMISC 0x1b0 > +#define K230_DDRC_DFISTAT 0x1bc > +#define K230_DDRC_SWCTL 0x320 > +#define K230_DDRC_SWSTAT 0x324 > + > +#define K230_DDRC_STAT_OPERATING_MODE_MASK 0x7 > +#define K230_DDRC_DFISTAT_DFI_INIT_COMPLETE_MASK 0x1 > + > +#define K230_DDR_PHY_CSR(index) \ > + (K230_DDR_PHY_BASE + (uint64_t)(index) * sizeof(uint32_t)) > + > +#define K230_DDR_PHY_ATX_IMPEDANCE 0x00043 > +#define K230_DDR_PHY_TX_IMPEDANCE_CTRL1 0x10049 > +#define K230_DDR_PHY_VREF_IN_GLOBAL 0x200b2 > +#define K230_DDR_PHY_MICRO_CONT_MUX_SEL 0xd0000 > +#define K230_DDR_PHY_TRAINING_STATUS 0xd0004 > +#define K230_DDR_PHY_TRAINING_ACK 0xd0031 > +#define K230_DDR_PHY_TRAINING_MESSAGE 0xd0032 > +#define K230_DDR_PHY_TRAINING_TRIGGER 0xd0099 > + > +static void complete_phy_training(QTestState *qts) > +{ > + qtest_writel(qts, > + K230_DDR_PHY_CSR(K230_DDR_PHY_MICRO_CONT_MUX_SEL), 1); > + qtest_writel(qts, K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_TRIGGER), 9); > + qtest_writel(qts, K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_TRIGGER), 1); > + qtest_writel(qts, K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_TRIGGER), 0); > +} > + > +static void test_reset_and_register_access(void) > +{ > + QTestState *qts = qtest_init("-machine k230"); > + > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_MSTR), > + ==, 0x01040000); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_STAT), > + ==, 0x00000000); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_DRAMTMG4), > + ==, 0x05040405); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_DFIMISC), > + ==, 0x00000001); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_SWCTL), > + ==, 0x00000001); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_SWSTAT), > + ==, 0x00000001); > + > + g_assert_cmphex(qtest_readl(qts, > + K230_DDR_PHY_CSR(K230_DDR_PHY_ATX_IMPEDANCE)), > + ==, 0x03ff); > + g_assert_cmphex(qtest_readl(qts, > + K230_DDR_PHY_CSR(K230_DDR_PHY_TX_IMPEDANCE_CTRL1)), > + ==, 0x0fff); > + g_assert_cmphex(qtest_readl(qts, > + K230_DDR_PHY_CSR(K230_DDR_PHY_VREF_IN_GLOBAL)), > + ==, 0x0200); > + > + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_MSTR, 0x01040008); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_MSTR), > + ==, 0x01040008); > + > + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_STAT, 0xffffffff); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_STAT), > + ==, 0x00000000); > + > + qtest_writel(qts, K230_DDR_PHY_CSR(K230_DDR_PHY_VREF_IN_GLOBAL), > + 0xffffffff); > + g_assert_cmphex(qtest_readl(qts, > + K230_DDR_PHY_CSR(K230_DDR_PHY_VREF_IN_GLOBAL)), > + ==, 0x7fff); > + > + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_DRAMTMG4, 0); > + > + qtest_system_reset(qts); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_MSTR), > + ==, 0x01040000); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_DRAMTMG4), > + ==, 0x05040405); > + g_assert_cmphex(qtest_readl(qts, > + K230_DDR_PHY_CSR(K230_DDR_PHY_VREF_IN_GLOBAL)), > + ==, 0x0200); > + > + qtest_quit(qts); > +} > + > +static void test_software_update_handshake(void) > +{ > + QTestState *qts = qtest_init("-machine k230"); > + > + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_SWCTL, 0); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_SWSTAT), > + ==, 0); > + > + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_SWCTL, 1); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_SWSTAT), > + ==, 1); > + > + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_SWSTAT, 0); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_SWSTAT), > + ==, 1); > + > + qtest_quit(qts); > +} > + > +static void test_phy_ownership(void) > +{ > + QTestState *qts = qtest_init("-machine k230"); > + uint64_t atx = K230_DDR_PHY_CSR(K230_DDR_PHY_ATX_IMPEDANCE); > + uint64_t mux = K230_DDR_PHY_CSR(K230_DDR_PHY_MICRO_CONT_MUX_SEL); > + > + qtest_writel(qts, atx, 0x155); > + g_assert_cmphex(qtest_readl(qts, atx), ==, 0x155); > + > + qtest_writel(qts, mux, 1); > + qtest_writel(qts, atx, 0x2aa); > + g_assert_cmphex(qtest_readl(qts, atx), ==, 0x155); > + > + qtest_writel(qts, mux, 0); > + qtest_writel(qts, atx, 0x2aa); > + g_assert_cmphex(qtest_readl(qts, atx), ==, 0x2aa); > + > + qtest_quit(qts); > +} > + > +static void test_dfi_prerequisites(void) > +{ > + QTestState *qts = qtest_init("-machine k230"); > + > + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_DFIMISC, 0x20); > + > + g_assert_cmphex(qtest_readl(qts, > + K230_DDRC_BASE + K230_DDRC_DFISTAT) & > + K230_DDRC_DFISTAT_DFI_INIT_COMPLETE_MASK, > + ==, 0); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_STAT) & > + K230_DDRC_STAT_OPERATING_MODE_MASK, > + ==, 0); > + > + qtest_quit(qts); > +} > + > +static void test_dfi_complete_enable(void) > +{ > + QTestState *qts = qtest_init("-machine k230"); > + > + complete_phy_training(qts); > + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_DFIMISC, 0x20); > + > + g_assert_cmphex(qtest_readl(qts, > + K230_DDRC_BASE + K230_DDRC_DFISTAT) & > + K230_DDRC_DFISTAT_DFI_INIT_COMPLETE_MASK, > + ==, 1); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_STAT) & > + K230_DDRC_STAT_OPERATING_MODE_MASK, > + ==, 0); > + > + qtest_quit(qts); > +} > + > +static void test_training_and_dfi_handshake(void) > +{ > + QTestState *qts = qtest_init("-machine k230"); > + > + complete_phy_training(qts); > + > + g_assert_cmphex(qtest_readl(qts, > + K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_STATUS)), > + ==, 0); > + g_assert_cmphex(qtest_readl(qts, > + K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_MESSAGE)), > + ==, 0x07); > + > + qtest_writel(qts, K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_ACK), 0); > + g_assert_cmphex(qtest_readl(qts, > + K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_STATUS)), > + ==, 1); > + qtest_writel(qts, K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_ACK), 1); > + > + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_DFIMISC, 0x20); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_DFISTAT), > + ==, 1); > + > + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_DFIMISC, 0); > + qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_DFIMISC, 1); > + g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_STAT) & 0x7, > + ==, 1); > + > + qtest_quit(qts); > +} > + > +int main(int argc, char **argv) > +{ > + g_test_init(&argc, &argv, NULL); > + > + qtest_add_func("/k230-ddr/reset-and-register-access", > + test_reset_and_register_access); > + qtest_add_func("/k230-ddr/software-update-handshake", > + test_software_update_handshake); > + qtest_add_func("/k230-ddr/phy-ownership", test_phy_ownership); > + qtest_add_func("/k230-ddr/dfi-prerequisites", test_dfi_prerequisites); > + qtest_add_func("/k230-ddr/dfi-complete-enable", > + test_dfi_complete_enable); > + qtest_add_func("/k230-ddr/training-and-dfi-handshake", > + test_training_and_dfi_handshake); > + > + return g_test_run(); > +} > diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build > index 56ff860e21..dc110f72c8 100644 > --- a/tests/qtest/meson.build > +++ b/tests/qtest/meson.build > @@ -297,7 +297,8 @@ qtests_riscv64 = ['riscv-csr-test'] + \ > (config_all_devices.has_key('CONFIG_IOMMU_TESTDEV') and > config_all_devices.has_key('CONFIG_RISCV_IOMMU') ? > ['iommu-riscv-test'] : []) + \ > - (config_all_devices.has_key('CONFIG_K230') ? ['k230-wdt-test'] : []) > + (config_all_devices.has_key('CONFIG_K230') ? > + ['k230-ddr-test', 'k230-wdt-test'] : []) > > qtests_hexagon = ['boot-serial-test'] > > -- > 2.53.0 > ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2026-07-23 8:43 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-07-16 13:24 [PATCH 0/3] riscv: Add K230 DDR controller and PHY models Junze Cao 2026-07-16 13:24 ` [PATCH 1/3] hw/misc: " Junze Cao 2026-07-22 20:06 ` Daniel Henrique Barboza 2026-07-23 8:41 ` Chao Liu 2026-07-16 13:24 ` [PATCH 2/3] hw/riscv: Connect " Junze Cao 2026-07-22 20:08 ` Daniel Henrique Barboza 2026-07-23 8:42 ` Chao Liu 2026-07-16 13:24 ` [PATCH 3/3] tests/qtest: Add K230 DDR controller tests Junze Cao 2026-07-22 20:16 ` Daniel Henrique Barboza 2026-07-23 8:42 ` Chao Liu
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