[PATCH] PCI: Allow D3 for native Hotplug capable Root Ports on DT platforms

[PATCH] PCI: Allow D3 for native Hotplug capable Root Ports on DT platforms

[Manivannan Sadhasivam]

Commit eb3b5bf1a88d ("PCI: Whitelist native hotplug ports for runtime D3"),
prevented native Hotplug capable Root Ports from entering D3 citing issues
on old Intel SkyLake Xeon-SP platform.

But there is no reason to restrict D3 for native Hotplug capable Root
Ports on DT platforms. We recently enabled D3 on non-Hotplug capable
Root Ports on non-x86 platforms (specifically for DT platforms) in commit
a5fb3ff63287 ("PCI: Allow PCI bridges to go to D3Hot on all non-x86"). So
do the same for native Hotplug capable Root Ports as well.

To honor the above platform_pci_bridge_d3() check, allow passing this check
only for DT platforms, unlike a5fb3ff63287, which used !CONFIG_X86 check.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
---
 drivers/pci/pci.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 77b17b13ee61..d5038bb13837 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -3020,11 +3020,11 @@ bool pci_bridge_d3_possible(struct pci_dev *bridge)
 			return true;
 
 		/*
-		 * Hotplug ports handled natively by the OS were not validated
-		 * by vendors for runtime D3 at least until 2018 because there
-		 * was no OS support.
+		 * Do not allow D3 for native Hotplug ports on non-DT platforms
+		 * as they were not validated by vendors for runtime D3 at least
+		 * until 2018 because there was no OS support.
 		 */
-		if (bridge->is_pciehp)
+		if (bridge->is_pciehp && !of_have_populated_dt())
 			return false;
 
 		if (dmi_check_system(bridge_d3_blacklist))
-- 
2.43.0

Re: [PATCH] PCI: Allow D3 for native Hotplug capable Root Ports on DT platforms

[sashiko-bot]

> Commit eb3b5bf1a88d ("PCI: Whitelist native hotplug ports for runtime D3"),
> prevented native Hotplug capable Root Ports from entering D3 citing issues
> on old Intel SkyLake Xeon-SP platform.
> 
> But there is no reason to restrict D3 for native Hotplug capable Root
> Ports on DT platforms. We recently enabled D3 on non-Hotplug capable
> Root Ports on non-x86 platforms (specifically for DT platforms) in commit
> a5fb3ff63287 ("PCI: Allow PCI bridges to go to D3Hot on all non-x86"). So
> do the same for native Hotplug capable Root Ports as well.
> 
> To honor the above platform_pci_bridge_d3() check, allow passing this check
> only for DT platforms, unlike a5fb3ff63287, which used !CONFIG_X86 check.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>

Sashiko has reviewed this patch and found no issues. It looks great!

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260729071514.859778-1-manivannan.sadhasivam@oss.qualcomm.com?part=1

Re: [PATCH] PCI: Allow D3 for native Hotplug capable Root Ports on DT platforms

[Lukas Wunner]

On Wed, Jul 29, 2026 at 09:15:14AM +0200, Manivannan Sadhasivam wrote:
> Commit eb3b5bf1a88d ("PCI: Whitelist native hotplug ports for runtime D3"),
> prevented native Hotplug capable Root Ports from entering D3 citing issues
> on old Intel SkyLake Xeon-SP platform.
> 
> But there is no reason to restrict D3 for native Hotplug capable Root
> Ports on DT platforms. We recently enabled D3 on non-Hotplug capable
> Root Ports on non-x86 platforms (specifically for DT platforms) in commit
> a5fb3ff63287 ("PCI: Allow PCI bridges to go to D3Hot on all non-x86"). So
> do the same for native Hotplug capable Root Ports as well.
> 
> To honor the above platform_pci_bridge_d3() check, allow passing this check
> only for DT platforms, unlike a5fb3ff63287, which used !CONFIG_X86 check.

platform_pci_bridge_d3() acts as a "whitelist check":  If it returns true,
the port is allowed to go to D3hot/D3cold.  If it returns false, the
subsequent checks in pci_bridge_d3_possible() are free to decide the
port's fate as far as D3hot/D3cold allowance is concerned.

Thus, I don't think you need to worry about "honoring" a "false" return
value of platform_pci_bridge_d3().  (If I understand your commit message
correctly.)

> +++ b/drivers/pci/pci.c
> @@ -3020,11 +3020,11 @@ bool pci_bridge_d3_possible(struct pci_dev *bridge)
>  			return true;
>  
>  		/*
> -		 * Hotplug ports handled natively by the OS were not validated
> -		 * by vendors for runtime D3 at least until 2018 because there
> -		 * was no OS support.
> +		 * Do not allow D3 for native Hotplug ports on non-DT platforms
> +		 * as they were not validated by vendors for runtime D3 at least
> +		 * until 2018 because there was no OS support.
>  		 */
> -		if (bridge->is_pciehp)
> +		if (bridge->is_pciehp && !of_have_populated_dt())
>  			return false;

And so I'm wondering whether:

+		if (IS_ENABLED(CONFIG_X86) && bridge->is_pciehp)
 			return false;

would be more appropriate and more consistent with the subsequent check in
pci_bridge_d3_possible() that also uses IS_ENABLED(CONFIG_X86).  Basically
this would mean that we only special-case legacy x86 hardware, but assume
that anything else supports D3hot/D3cold for native hotplug bridges just
fine.  In particular, arm64 systems using ACPI.

Thanks,

Lukas

Re: [PATCH] PCI: Allow D3 for native Hotplug capable Root Ports on DT platforms

[Manivannan Sadhasivam]

On Wed, Jul 29, 2026 at 04:40:29PM +0200, Lukas Wunner wrote:
> On Wed, Jul 29, 2026 at 09:15:14AM +0200, Manivannan Sadhasivam wrote:
> > Commit eb3b5bf1a88d ("PCI: Whitelist native hotplug ports for runtime D3"),
> > prevented native Hotplug capable Root Ports from entering D3 citing issues
> > on old Intel SkyLake Xeon-SP platform.
> > 
> > But there is no reason to restrict D3 for native Hotplug capable Root
> > Ports on DT platforms. We recently enabled D3 on non-Hotplug capable
> > Root Ports on non-x86 platforms (specifically for DT platforms) in commit
> > a5fb3ff63287 ("PCI: Allow PCI bridges to go to D3Hot on all non-x86"). So
> > do the same for native Hotplug capable Root Ports as well.
> > 
> > To honor the above platform_pci_bridge_d3() check, allow passing this check
> > only for DT platforms, unlike a5fb3ff63287, which used !CONFIG_X86 check.
> 
> platform_pci_bridge_d3() acts as a "whitelist check":  If it returns true,
> the port is allowed to go to D3hot/D3cold.  If it returns false, the
> subsequent checks in pci_bridge_d3_possible() are free to decide the
> port's fate as far as D3hot/D3cold allowance is concerned.
> 
> Thus, I don't think you need to worry about "honoring" a "false" return
> value of platform_pci_bridge_d3().  (If I understand your commit message
> correctly.)
> 

Okay, thanks for clarifying. I was worried about ACPI based ARM64/RISC-V
platforms and was trying to be conservative.

> > +++ b/drivers/pci/pci.c
> > @@ -3020,11 +3020,11 @@ bool pci_bridge_d3_possible(struct pci_dev *bridge)
> >  			return true;
> >  
> >  		/*
> > -		 * Hotplug ports handled natively by the OS were not validated
> > -		 * by vendors for runtime D3 at least until 2018 because there
> > -		 * was no OS support.
> > +		 * Do not allow D3 for native Hotplug ports on non-DT platforms
> > +		 * as they were not validated by vendors for runtime D3 at least
> > +		 * until 2018 because there was no OS support.
> >  		 */
> > -		if (bridge->is_pciehp)
> > +		if (bridge->is_pciehp && !of_have_populated_dt())
> >  			return false;
> 
> And so I'm wondering whether:
> 
> +		if (IS_ENABLED(CONFIG_X86) && bridge->is_pciehp)
>  			return false;
> 
> would be more appropriate and more consistent with the subsequent check in
> pci_bridge_d3_possible() that also uses IS_ENABLED(CONFIG_X86).  Basically
> this would mean that we only special-case legacy x86 hardware, but assume
> that anything else supports D3hot/D3cold for native hotplug bridges just
> fine.  In particular, arm64 systems using ACPI.
> 

Okay sure.

- Mani

-- 
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