From: Zhao Liu <zhao1.liu@intel.com>
To: zhang_wei@open-hieco.net
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org,
"Michael S . Tsirkin" <mst@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Marcelo Tosatti <mtosatti@redhat.com>
Subject: Re: [PATCH v1 2/9] target/i386: Hide Intel cache CPUID leaves for Hygon
Date: Fri, 31 Jul 2026 15:03:41 +0800 [thread overview]
Message-ID: <amxIzcG2sSLLljng@intel.com> (raw)
In-Reply-To: <20260706055530.1752094-3-zhang_wei@open-hieco.net>
On Mon, Jul 06, 2026 at 01:55:23PM +0800, zhang_wei@open-hieco.net wrote:
> Date: Mon, 6 Jul 2026 13:55:23 +0800
> From: zhang_wei@open-hieco.net
> Subject: [PATCH v1 2/9] target/i386: Hide Intel cache CPUID leaves for Hygon
> X-Mailer: git-send-email 2.43.7
>
> From: Tina Zhang <zhang_wei@open-hieco.net>
>
> When x-vendor-cpuid-only is enabled, QEMU suppresses CPUID leaves 2
> and 4 for AuthenticAMD CPUs because those leaves describe Intel cache
> information. Hygon Dhyana uses the HygonGenuine vendor string, so it
> currently skips that filtering and can expose Intel cache leaves together
> with AMD/Hygon extended cache leaves.
>
> That is inconsistent guest-visible CPUID: Hygon Dhyana provides cache
> information through the extended cache leaves, so it should not also
> advertise the Intel cache descriptor and deterministic cache parameter
> leaves.
>
> Apply the same leaf 2 and leaf 4 filtering to Hygon CPUs when Hygon
> vendor ABI fixes are enabled. The property keeps the old CPUID output
> for pc-11.0 and older machine types.
>
> Signed-off-by: Tina Zhang <zhang_wei@open-hieco.net>
> ---
> target/i386/cpu.c | 19 +++++++++++++++++--
> 1 file changed, 17 insertions(+), 2 deletions(-)
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
next prev parent reply other threads:[~2026-07-31 7:03 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-06 5:55 [PATCH v1 0/9] target/i386: Fix Hygon vendor-specific CPU behavior zhang_wei
2026-07-06 5:55 ` [PATCH v1 1/9] target/i386: Sync AMD CPUID aliases for Hygon zhang_wei
2026-07-31 7:02 ` Zhao Liu
2026-07-31 7:50 ` Tina Zhang
2026-07-06 5:55 ` [PATCH v1 2/9] target/i386: Hide Intel cache CPUID leaves " zhang_wei
2026-07-31 7:03 ` Zhao Liu [this message]
2026-07-06 5:55 ` [PATCH v1 3/9] target/i386: Hide ARCH_CAPABILITIES " zhang_wei
2026-07-31 7:05 ` Zhao Liu
2026-07-06 5:55 ` [PATCH v1 4/9] target/i386/kvm: Use AMD MCE status encoding " zhang_wei
2026-07-31 7:06 ` Zhao Liu
2026-07-31 7:21 ` Tina Zhang
2026-07-06 5:55 ` [PATCH v1 5/9] target/i386/kvm: Use AMD PMU MSR paths " zhang_wei
2026-07-31 5:55 ` Zhao Liu
2026-07-31 7:18 ` Tina Zhang
2026-07-06 5:55 ` [PATCH v1 6/9] target/i386: Do not broadcast injected MCEs " zhang_wei
2026-07-06 5:55 ` [PATCH v1 7/9] hw/i386: Apply AMD IOMMU HT GPA hole to Hygon zhang_wei
2026-07-06 5:55 ` [PATCH v1 8/9] target/i386: Use AMD legacy cache fallback for Hygon zhang_wei
2026-07-31 7:08 ` Zhao Liu
2026-07-06 5:55 ` [PATCH v1 9/9] target/i386: Use AMD ucode-rev default " zhang_wei
2026-07-22 12:10 ` [PATCH v1 0/9] target/i386: Fix Hygon vendor-specific CPU behavior Tina Zhang
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