From: Zhao Liu <zhao1.liu@intel.com>
To: zhang_wei@open-hieco.net
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org,
"Michael S . Tsirkin" <mst@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Marcelo Tosatti <mtosatti@redhat.com>
Subject: Re: [PATCH v1 4/9] target/i386/kvm: Use AMD MCE status encoding for Hygon
Date: Fri, 31 Jul 2026 15:06:39 +0800 [thread overview]
Message-ID: <amxJf2elltpmBHFD@intel.com> (raw)
In-Reply-To: <20260706055530.1752094-5-zhang_wei@open-hieco.net>
> +/*
> + * Use AMD-style MCE status records for QEMU-injected memory failures on
> + * AMD and Hygon CPUs.
> + */
> +static bool kvm_mce_inject_uses_amd_status(const CPUX86State *env)
> +{
> + return IS_AMD_CPU(env) || IS_HYGON_CPU(env);
> +}
> +
> static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
> {
> CPUState *cs = CPU(cpu);
> @@ -707,7 +716,7 @@ static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
> uint64_t mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV;
> int flags = 0;
>
> - if (!IS_AMD_CPU(env)) {
> + if (!kvm_mce_inject_uses_amd_status(env)) {
Maybe we can check hygon directly here?
Regards,
Zhao
> status |= MCI_STATUS_S | MCI_STATUS_UC;
> if (code == BUS_MCEERR_AR) {
> status |= MCI_STATUS_AR | 0x134;
> --
> 2.43.7
>
>
next prev parent reply other threads:[~2026-07-31 7:06 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-06 5:55 [PATCH v1 0/9] target/i386: Fix Hygon vendor-specific CPU behavior zhang_wei
2026-07-06 5:55 ` [PATCH v1 1/9] target/i386: Sync AMD CPUID aliases for Hygon zhang_wei
2026-07-31 7:02 ` Zhao Liu
2026-07-31 7:50 ` Tina Zhang
2026-07-06 5:55 ` [PATCH v1 2/9] target/i386: Hide Intel cache CPUID leaves " zhang_wei
2026-07-31 7:03 ` Zhao Liu
2026-07-06 5:55 ` [PATCH v1 3/9] target/i386: Hide ARCH_CAPABILITIES " zhang_wei
2026-07-31 7:05 ` Zhao Liu
2026-07-06 5:55 ` [PATCH v1 4/9] target/i386/kvm: Use AMD MCE status encoding " zhang_wei
2026-07-31 7:06 ` Zhao Liu [this message]
2026-07-31 7:21 ` Tina Zhang
2026-07-06 5:55 ` [PATCH v1 5/9] target/i386/kvm: Use AMD PMU MSR paths " zhang_wei
2026-07-31 5:55 ` Zhao Liu
2026-07-31 7:18 ` Tina Zhang
2026-07-06 5:55 ` [PATCH v1 6/9] target/i386: Do not broadcast injected MCEs " zhang_wei
2026-07-06 5:55 ` [PATCH v1 7/9] hw/i386: Apply AMD IOMMU HT GPA hole to Hygon zhang_wei
2026-07-06 5:55 ` [PATCH v1 8/9] target/i386: Use AMD legacy cache fallback for Hygon zhang_wei
2026-07-31 7:08 ` Zhao Liu
2026-07-06 5:55 ` [PATCH v1 9/9] target/i386: Use AMD ucode-rev default " zhang_wei
2026-07-22 12:10 ` [PATCH v1 0/9] target/i386: Fix Hygon vendor-specific CPU behavior Tina Zhang
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