* [PATCH] target/riscv: Restore register dump zero padding
@ 2026-08-13 3:24 Joel Stanley
2026-08-13 11:56 ` Anton Johansson via
2026-08-14 10:24 ` Max Chou
0 siblings, 2 replies; 4+ messages in thread
From: Joel Stanley @ 2026-08-13 3:24 UTC (permalink / raw)
To: Alistair Francis, Daniel Henrique Barboza
Cc: Weiwei Li, Liu Zhiwei, Chao Liu, Anton Johansson, qemu-riscv,
qemu-devel
The register values lost their leading zeroes when the underlying type
was changed, resulting in mismatched padding and harder to read output.
Print with a runtime field width based on MXL, so values are 16 hex
digits on rv64 and 8 on rv32, matching the csr and fp dump. This avoids
adding target_ulong back into the dump.
Fixes: c4e6bc63853c ("target/riscv: Fix size of gpr and gprh")
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
before:
mvendorid 0000000000000000
marchid 000000000000002a
mimpid 0000000000000000
mhartid 0000000000000000
mconfigptr 0000000000000000
x0/zero 0 x1/ra ffffffff803f10f6 x2/sp ff2000000000bc70 x3/gp ffffffff805c94c0
x4/tp ff60000000c78000 x5/t0 ffffffff803f132c x6/t1 0 x7/t2 20646e65205b2d2d
x8/s0 ff2000000000bc80 x9/s1 708 x10/a0 270f x11/a1 8
x12/a2 0 x13/a3 120 x14/a4 14992a1 x15/a5 ffffffffffffffff
x16/a6 fffff079 x17/a7 79 x18/s2 0 x19/s3 7d0
x20/s4 ffffffff805ca228 x21/s5 31 x22/s6 ff60000000e15000 x23/s7 ffffffff804228c8
x24/s8 0 x25/s9 ffffffff804e3e90 x26/s10 0 x27/s11 0
x28/t3 ff60000000c60f00 x29/t4 ff60000000c60f00 x30/t5 ff60000000c60000 x31/t6 ff2000000000bc28
fflags 0000000000000000
frm 0000000000000000
fcsr 0000000000000000
f0/ft0 ffffffff00000000 f1/ft1 ffffffff00000000 f2/ft2 ffffffff00000000 f3/ft3 ffffffff00000000
f4/ft4 ffffffff00000000 f5/ft5 ffffffff00000000 f6/ft6 ffffffff00000000 f7/ft7 ffffffff00000000
f8/fs0 ffffffff00000000 f9/fs1 ffffffff00000000 f10/fa0 ffffffff00000000 f11/fa1 ffffffff00000000
f12/fa2 ffffffff00000000 f13/fa3 ffffffff00000000 f14/fa4 ffffffff00000000 f15/fa5 ffffffff00000000
f16/fa6 ffffffff00000000 f17/fa7 ffffffff00000000 f18/fs2 ffffffff00000000 f19/fs3 ffffffff00000000
f20/fs4 ffffffff00000000 f21/fs5 ffffffff00000000 f22/fs6 ffffffff00000000 f23/fs7 ffffffff00000000
f24/fs8 ffffffff00000000 f25/fs9 ffffffff00000000 f26/fs10 ffffffff00000000 f27/fs11 ffffffff00000000
f28/ft8 ffffffff00000000 f29/ft9 ffffffff00000000 f30/ft10 ffffffff00000000 f31/ft11 ffffffff00000000
after:
mvendorid 0000000000000000
marchid 000000000000002a
mimpid 0000000000000000
mhartid 0000000000000000
mconfigptr 0000000000000000
x0/zero 0000000000000000 x1/ra ffffffff803f10f6 x2/sp ff2000000000bc70 x3/gp ffffffff805c94c0
x4/tp ff60000000c78000 x5/t0 ffffffff803f132c x6/t1 0000000000000000 x7/t2 20646e65205b2d2d
x8/s0 ff2000000000bc80 x9/s1 0000000000000e10 x10/a0 000000000000270f x11/a1 0000000000000008
x12/a2 0000000000000000 x13/a3 0000000000000120 x14/a4 0000000002575fd6 x15/a5 ffffffffffffffff
x16/a6 00000000fffff079 x17/a7 0000000000000079 x18/s2 0000000000000001 x19/s3 0000000000000ed8
x20/s4 ffffffff805ca228 x21/s5 0000000000000060 x22/s6 ff60000000e15000 x23/s7 ffffffff804228c8
x24/s8 0000000000000000 x25/s9 ffffffff804e3e90 x26/s10 0000000000000000 x27/s11 0000000000000000
x28/t3 ff60000000c60f00 x29/t4 ff60000000c60f00 x30/t5 ff60000000c60000 x31/t6 ff2000000000bc28
fflags 0000000000000000
frm 0000000000000000
fcsr 0000000000000000
f0/ft0 ffffffff00000000 f1/ft1 ffffffff00000000 f2/ft2 ffffffff00000000 f3/ft3 ffffffff00000000
f4/ft4 ffffffff00000000 f5/ft5 ffffffff00000000 f6/ft6 ffffffff00000000 f7/ft7 ffffffff00000000
f8/fs0 ffffffff00000000 f9/fs1 ffffffff00000000 f10/fa0 ffffffff00000000 f11/fa1 ffffffff00000000
f12/fa2 ffffffff00000000 f13/fa3 ffffffff00000000 f14/fa4 ffffffff00000000 f15/fa5 ffffffff00000000
f16/fa6 ffffffff00000000 f17/fa7 ffffffff00000000 f18/fs2 ffffffff00000000 f19/fs3 ffffffff00000000
f20/fs4 ffffffff00000000 f21/fs5 ffffffff00000000 f22/fs6 ffffffff00000000 f23/fs7 ffffffff00000000
f24/fs8 ffffffff00000000 f25/fs9 ffffffff00000000 f26/fs10 ffffffff00000000 f27/fs11 ffffffff00000000
f28/ft8 ffffffff00000000 f29/ft9 ffffffff00000000 f30/ft10 ffffffff00000000 f31/ft11 ffffffff00000000
I also wrote a patch to align the first column of register values, but
that creates the dilemma between aligning the numbers vs keeping the
spacing between the registers and their value within a row. Aside from
avoiding bikeshedding, it wastes more columns for an already wide
output, so opted not to 'fix' that.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
target/riscv/cpu.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 19b93f9c9794..c50dd5ee8771 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -650,6 +650,9 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
+ bool rv32 = riscv_cpu_is_32bit(cpu);
+ int width = rv32 ? 8 : 16;
+ uint64_t mask = rv32 ? UINT32_MAX : UINT64_MAX;
int i, j;
uint8_t *p;
@@ -664,7 +667,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, " %-13s %d\n", "elp", env->elp);
}
#endif
- qemu_fprintf(f, " %-13s %" PRIx64 "\n", "pc", env->pc);
+ qemu_fprintf(f, " %-13s %0*" PRIx64 "\n", "pc", width, env->pc & mask);
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
for (i = 0; i < ARRAY_SIZE(csr_ops); i++) {
int csrno = i;
@@ -691,8 +694,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
#endif
for (i = 0; i < 32; i++) {
- qemu_fprintf(f, " %-8s %" PRIx64,
- riscv_int_regnames[i], env->gpr[i]);
+ qemu_fprintf(f, " %-8s %0*" PRIx64,
+ riscv_int_regnames[i], width, env->gpr[i] & mask);
if ((i & 3) == 3) {
qemu_fprintf(f, "\n");
}
--
2.47.3
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] target/riscv: Restore register dump zero padding
2026-08-13 3:24 [PATCH] target/riscv: Restore register dump zero padding Joel Stanley
@ 2026-08-13 11:56 ` Anton Johansson via
2026-08-14 10:24 ` Max Chou
1 sibling, 0 replies; 4+ messages in thread
From: Anton Johansson via qemu development @ 2026-08-13 11:56 UTC (permalink / raw)
To: Joel Stanley
Cc: Alistair Francis, Daniel Henrique Barboza, Weiwei Li, Liu Zhiwei,
Chao Liu, qemu-riscv, qemu-devel
On 13/08/26, Joel Stanley wrote:
> The register values lost their leading zeroes when the underlying type
> was changed, resulting in mismatched padding and harder to read output.
>
> Print with a runtime field width based on MXL, so values are 16 hex
> digits on rv64 and 8 on rv32, matching the csr and fp dump. This avoids
> adding target_ulong back into the dump.
>
> Fixes: c4e6bc63853c ("target/riscv: Fix size of gpr and gprh")
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> before:
>
> mvendorid 0000000000000000
> marchid 000000000000002a
> mimpid 0000000000000000
> mhartid 0000000000000000
> mconfigptr 0000000000000000
> x0/zero 0 x1/ra ffffffff803f10f6 x2/sp ff2000000000bc70 x3/gp ffffffff805c94c0
> x4/tp ff60000000c78000 x5/t0 ffffffff803f132c x6/t1 0 x7/t2 20646e65205b2d2d
> x8/s0 ff2000000000bc80 x9/s1 708 x10/a0 270f x11/a1 8
> x12/a2 0 x13/a3 120 x14/a4 14992a1 x15/a5 ffffffffffffffff
> x16/a6 fffff079 x17/a7 79 x18/s2 0 x19/s3 7d0
> x20/s4 ffffffff805ca228 x21/s5 31 x22/s6 ff60000000e15000 x23/s7 ffffffff804228c8
> x24/s8 0 x25/s9 ffffffff804e3e90 x26/s10 0 x27/s11 0
> x28/t3 ff60000000c60f00 x29/t4 ff60000000c60f00 x30/t5 ff60000000c60000 x31/t6 ff2000000000bc28
> fflags 0000000000000000
> frm 0000000000000000
> fcsr 0000000000000000
> f0/ft0 ffffffff00000000 f1/ft1 ffffffff00000000 f2/ft2 ffffffff00000000 f3/ft3 ffffffff00000000
> f4/ft4 ffffffff00000000 f5/ft5 ffffffff00000000 f6/ft6 ffffffff00000000 f7/ft7 ffffffff00000000
> f8/fs0 ffffffff00000000 f9/fs1 ffffffff00000000 f10/fa0 ffffffff00000000 f11/fa1 ffffffff00000000
> f12/fa2 ffffffff00000000 f13/fa3 ffffffff00000000 f14/fa4 ffffffff00000000 f15/fa5 ffffffff00000000
> f16/fa6 ffffffff00000000 f17/fa7 ffffffff00000000 f18/fs2 ffffffff00000000 f19/fs3 ffffffff00000000
> f20/fs4 ffffffff00000000 f21/fs5 ffffffff00000000 f22/fs6 ffffffff00000000 f23/fs7 ffffffff00000000
> f24/fs8 ffffffff00000000 f25/fs9 ffffffff00000000 f26/fs10 ffffffff00000000 f27/fs11 ffffffff00000000
> f28/ft8 ffffffff00000000 f29/ft9 ffffffff00000000 f30/ft10 ffffffff00000000 f31/ft11 ffffffff00000000
>
> after:
>
> mvendorid 0000000000000000
> marchid 000000000000002a
> mimpid 0000000000000000
> mhartid 0000000000000000
> mconfigptr 0000000000000000
> x0/zero 0000000000000000 x1/ra ffffffff803f10f6 x2/sp ff2000000000bc70 x3/gp ffffffff805c94c0
> x4/tp ff60000000c78000 x5/t0 ffffffff803f132c x6/t1 0000000000000000 x7/t2 20646e65205b2d2d
> x8/s0 ff2000000000bc80 x9/s1 0000000000000e10 x10/a0 000000000000270f x11/a1 0000000000000008
> x12/a2 0000000000000000 x13/a3 0000000000000120 x14/a4 0000000002575fd6 x15/a5 ffffffffffffffff
> x16/a6 00000000fffff079 x17/a7 0000000000000079 x18/s2 0000000000000001 x19/s3 0000000000000ed8
> x20/s4 ffffffff805ca228 x21/s5 0000000000000060 x22/s6 ff60000000e15000 x23/s7 ffffffff804228c8
> x24/s8 0000000000000000 x25/s9 ffffffff804e3e90 x26/s10 0000000000000000 x27/s11 0000000000000000
> x28/t3 ff60000000c60f00 x29/t4 ff60000000c60f00 x30/t5 ff60000000c60000 x31/t6 ff2000000000bc28
> fflags 0000000000000000
> frm 0000000000000000
> fcsr 0000000000000000
> f0/ft0 ffffffff00000000 f1/ft1 ffffffff00000000 f2/ft2 ffffffff00000000 f3/ft3 ffffffff00000000
> f4/ft4 ffffffff00000000 f5/ft5 ffffffff00000000 f6/ft6 ffffffff00000000 f7/ft7 ffffffff00000000
> f8/fs0 ffffffff00000000 f9/fs1 ffffffff00000000 f10/fa0 ffffffff00000000 f11/fa1 ffffffff00000000
> f12/fa2 ffffffff00000000 f13/fa3 ffffffff00000000 f14/fa4 ffffffff00000000 f15/fa5 ffffffff00000000
> f16/fa6 ffffffff00000000 f17/fa7 ffffffff00000000 f18/fs2 ffffffff00000000 f19/fs3 ffffffff00000000
> f20/fs4 ffffffff00000000 f21/fs5 ffffffff00000000 f22/fs6 ffffffff00000000 f23/fs7 ffffffff00000000
> f24/fs8 ffffffff00000000 f25/fs9 ffffffff00000000 f26/fs10 ffffffff00000000 f27/fs11 ffffffff00000000
> f28/ft8 ffffffff00000000 f29/ft9 ffffffff00000000 f30/ft10 ffffffff00000000 f31/ft11 ffffffff00000000
>
> I also wrote a patch to align the first column of register values, but
> that creates the dilemma between aligning the numbers vs keeping the
> spacing between the registers and their value within a row. Aside from
> avoiding bikeshedding, it wastes more columns for an already wide
> output, so opted not to 'fix' that.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> target/riscv/cpu.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
Nice, thank you!:)
Reviewed-by: Anton Johansson <anjo@rev.ng>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] target/riscv: Restore register dump zero padding
@ 2026-08-13 11:56 ` Anton Johansson via
0 siblings, 0 replies; 4+ messages in thread
From: Anton Johansson via @ 2026-08-13 11:56 UTC (permalink / raw)
To: Joel Stanley
Cc: Alistair Francis, Daniel Henrique Barboza, Weiwei Li, Liu Zhiwei,
Chao Liu, qemu-riscv, qemu-devel
On 13/08/26, Joel Stanley wrote:
> The register values lost their leading zeroes when the underlying type
> was changed, resulting in mismatched padding and harder to read output.
>
> Print with a runtime field width based on MXL, so values are 16 hex
> digits on rv64 and 8 on rv32, matching the csr and fp dump. This avoids
> adding target_ulong back into the dump.
>
> Fixes: c4e6bc63853c ("target/riscv: Fix size of gpr and gprh")
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> before:
>
> mvendorid 0000000000000000
> marchid 000000000000002a
> mimpid 0000000000000000
> mhartid 0000000000000000
> mconfigptr 0000000000000000
> x0/zero 0 x1/ra ffffffff803f10f6 x2/sp ff2000000000bc70 x3/gp ffffffff805c94c0
> x4/tp ff60000000c78000 x5/t0 ffffffff803f132c x6/t1 0 x7/t2 20646e65205b2d2d
> x8/s0 ff2000000000bc80 x9/s1 708 x10/a0 270f x11/a1 8
> x12/a2 0 x13/a3 120 x14/a4 14992a1 x15/a5 ffffffffffffffff
> x16/a6 fffff079 x17/a7 79 x18/s2 0 x19/s3 7d0
> x20/s4 ffffffff805ca228 x21/s5 31 x22/s6 ff60000000e15000 x23/s7 ffffffff804228c8
> x24/s8 0 x25/s9 ffffffff804e3e90 x26/s10 0 x27/s11 0
> x28/t3 ff60000000c60f00 x29/t4 ff60000000c60f00 x30/t5 ff60000000c60000 x31/t6 ff2000000000bc28
> fflags 0000000000000000
> frm 0000000000000000
> fcsr 0000000000000000
> f0/ft0 ffffffff00000000 f1/ft1 ffffffff00000000 f2/ft2 ffffffff00000000 f3/ft3 ffffffff00000000
> f4/ft4 ffffffff00000000 f5/ft5 ffffffff00000000 f6/ft6 ffffffff00000000 f7/ft7 ffffffff00000000
> f8/fs0 ffffffff00000000 f9/fs1 ffffffff00000000 f10/fa0 ffffffff00000000 f11/fa1 ffffffff00000000
> f12/fa2 ffffffff00000000 f13/fa3 ffffffff00000000 f14/fa4 ffffffff00000000 f15/fa5 ffffffff00000000
> f16/fa6 ffffffff00000000 f17/fa7 ffffffff00000000 f18/fs2 ffffffff00000000 f19/fs3 ffffffff00000000
> f20/fs4 ffffffff00000000 f21/fs5 ffffffff00000000 f22/fs6 ffffffff00000000 f23/fs7 ffffffff00000000
> f24/fs8 ffffffff00000000 f25/fs9 ffffffff00000000 f26/fs10 ffffffff00000000 f27/fs11 ffffffff00000000
> f28/ft8 ffffffff00000000 f29/ft9 ffffffff00000000 f30/ft10 ffffffff00000000 f31/ft11 ffffffff00000000
>
> after:
>
> mvendorid 0000000000000000
> marchid 000000000000002a
> mimpid 0000000000000000
> mhartid 0000000000000000
> mconfigptr 0000000000000000
> x0/zero 0000000000000000 x1/ra ffffffff803f10f6 x2/sp ff2000000000bc70 x3/gp ffffffff805c94c0
> x4/tp ff60000000c78000 x5/t0 ffffffff803f132c x6/t1 0000000000000000 x7/t2 20646e65205b2d2d
> x8/s0 ff2000000000bc80 x9/s1 0000000000000e10 x10/a0 000000000000270f x11/a1 0000000000000008
> x12/a2 0000000000000000 x13/a3 0000000000000120 x14/a4 0000000002575fd6 x15/a5 ffffffffffffffff
> x16/a6 00000000fffff079 x17/a7 0000000000000079 x18/s2 0000000000000001 x19/s3 0000000000000ed8
> x20/s4 ffffffff805ca228 x21/s5 0000000000000060 x22/s6 ff60000000e15000 x23/s7 ffffffff804228c8
> x24/s8 0000000000000000 x25/s9 ffffffff804e3e90 x26/s10 0000000000000000 x27/s11 0000000000000000
> x28/t3 ff60000000c60f00 x29/t4 ff60000000c60f00 x30/t5 ff60000000c60000 x31/t6 ff2000000000bc28
> fflags 0000000000000000
> frm 0000000000000000
> fcsr 0000000000000000
> f0/ft0 ffffffff00000000 f1/ft1 ffffffff00000000 f2/ft2 ffffffff00000000 f3/ft3 ffffffff00000000
> f4/ft4 ffffffff00000000 f5/ft5 ffffffff00000000 f6/ft6 ffffffff00000000 f7/ft7 ffffffff00000000
> f8/fs0 ffffffff00000000 f9/fs1 ffffffff00000000 f10/fa0 ffffffff00000000 f11/fa1 ffffffff00000000
> f12/fa2 ffffffff00000000 f13/fa3 ffffffff00000000 f14/fa4 ffffffff00000000 f15/fa5 ffffffff00000000
> f16/fa6 ffffffff00000000 f17/fa7 ffffffff00000000 f18/fs2 ffffffff00000000 f19/fs3 ffffffff00000000
> f20/fs4 ffffffff00000000 f21/fs5 ffffffff00000000 f22/fs6 ffffffff00000000 f23/fs7 ffffffff00000000
> f24/fs8 ffffffff00000000 f25/fs9 ffffffff00000000 f26/fs10 ffffffff00000000 f27/fs11 ffffffff00000000
> f28/ft8 ffffffff00000000 f29/ft9 ffffffff00000000 f30/ft10 ffffffff00000000 f31/ft11 ffffffff00000000
>
> I also wrote a patch to align the first column of register values, but
> that creates the dilemma between aligning the numbers vs keeping the
> spacing between the registers and their value within a row. Aside from
> avoiding bikeshedding, it wastes more columns for an already wide
> output, so opted not to 'fix' that.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> target/riscv/cpu.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
Nice, thank you!:)
Reviewed-by: Anton Johansson <anjo@rev.ng>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] target/riscv: Restore register dump zero padding
2026-08-13 3:24 [PATCH] target/riscv: Restore register dump zero padding Joel Stanley
2026-08-13 11:56 ` Anton Johansson via
@ 2026-08-14 10:24 ` Max Chou
1 sibling, 0 replies; 4+ messages in thread
From: Max Chou @ 2026-08-14 10:24 UTC (permalink / raw)
To: Joel Stanley
Cc: Alistair Francis, Daniel Henrique Barboza, Weiwei Li, Liu Zhiwei,
Chao Liu, Anton Johansson, qemu-riscv, qemu-devel
On 2026-08-13 12:54, Joel Stanley wrote:
> The register values lost their leading zeroes when the underlying type
> was changed, resulting in mismatched padding and harder to read output.
>
> Print with a runtime field width based on MXL, so values are 16 hex
> digits on rv64 and 8 on rv32, matching the csr and fp dump. This avoids
> adding target_ulong back into the dump.
>
> Fixes: c4e6bc63853c ("target/riscv: Fix size of gpr and gprh")
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> before:
>
> mvendorid 0000000000000000
> marchid 000000000000002a
> mimpid 0000000000000000
> mhartid 0000000000000000
> mconfigptr 0000000000000000
> x0/zero 0 x1/ra ffffffff803f10f6 x2/sp ff2000000000bc70 x3/gp ffffffff805c94c0
> x4/tp ff60000000c78000 x5/t0 ffffffff803f132c x6/t1 0 x7/t2 20646e65205b2d2d
> x8/s0 ff2000000000bc80 x9/s1 708 x10/a0 270f x11/a1 8
> x12/a2 0 x13/a3 120 x14/a4 14992a1 x15/a5 ffffffffffffffff
> x16/a6 fffff079 x17/a7 79 x18/s2 0 x19/s3 7d0
> x20/s4 ffffffff805ca228 x21/s5 31 x22/s6 ff60000000e15000 x23/s7 ffffffff804228c8
> x24/s8 0 x25/s9 ffffffff804e3e90 x26/s10 0 x27/s11 0
> x28/t3 ff60000000c60f00 x29/t4 ff60000000c60f00 x30/t5 ff60000000c60000 x31/t6 ff2000000000bc28
> fflags 0000000000000000
> frm 0000000000000000
> fcsr 0000000000000000
> f0/ft0 ffffffff00000000 f1/ft1 ffffffff00000000 f2/ft2 ffffffff00000000 f3/ft3 ffffffff00000000
> f4/ft4 ffffffff00000000 f5/ft5 ffffffff00000000 f6/ft6 ffffffff00000000 f7/ft7 ffffffff00000000
> f8/fs0 ffffffff00000000 f9/fs1 ffffffff00000000 f10/fa0 ffffffff00000000 f11/fa1 ffffffff00000000
> f12/fa2 ffffffff00000000 f13/fa3 ffffffff00000000 f14/fa4 ffffffff00000000 f15/fa5 ffffffff00000000
> f16/fa6 ffffffff00000000 f17/fa7 ffffffff00000000 f18/fs2 ffffffff00000000 f19/fs3 ffffffff00000000
> f20/fs4 ffffffff00000000 f21/fs5 ffffffff00000000 f22/fs6 ffffffff00000000 f23/fs7 ffffffff00000000
> f24/fs8 ffffffff00000000 f25/fs9 ffffffff00000000 f26/fs10 ffffffff00000000 f27/fs11 ffffffff00000000
> f28/ft8 ffffffff00000000 f29/ft9 ffffffff00000000 f30/ft10 ffffffff00000000 f31/ft11 ffffffff00000000
>
> after:
>
> mvendorid 0000000000000000
> marchid 000000000000002a
> mimpid 0000000000000000
> mhartid 0000000000000000
> mconfigptr 0000000000000000
> x0/zero 0000000000000000 x1/ra ffffffff803f10f6 x2/sp ff2000000000bc70 x3/gp ffffffff805c94c0
> x4/tp ff60000000c78000 x5/t0 ffffffff803f132c x6/t1 0000000000000000 x7/t2 20646e65205b2d2d
> x8/s0 ff2000000000bc80 x9/s1 0000000000000e10 x10/a0 000000000000270f x11/a1 0000000000000008
> x12/a2 0000000000000000 x13/a3 0000000000000120 x14/a4 0000000002575fd6 x15/a5 ffffffffffffffff
> x16/a6 00000000fffff079 x17/a7 0000000000000079 x18/s2 0000000000000001 x19/s3 0000000000000ed8
> x20/s4 ffffffff805ca228 x21/s5 0000000000000060 x22/s6 ff60000000e15000 x23/s7 ffffffff804228c8
> x24/s8 0000000000000000 x25/s9 ffffffff804e3e90 x26/s10 0000000000000000 x27/s11 0000000000000000
> x28/t3 ff60000000c60f00 x29/t4 ff60000000c60f00 x30/t5 ff60000000c60000 x31/t6 ff2000000000bc28
> fflags 0000000000000000
> frm 0000000000000000
> fcsr 0000000000000000
> f0/ft0 ffffffff00000000 f1/ft1 ffffffff00000000 f2/ft2 ffffffff00000000 f3/ft3 ffffffff00000000
> f4/ft4 ffffffff00000000 f5/ft5 ffffffff00000000 f6/ft6 ffffffff00000000 f7/ft7 ffffffff00000000
> f8/fs0 ffffffff00000000 f9/fs1 ffffffff00000000 f10/fa0 ffffffff00000000 f11/fa1 ffffffff00000000
> f12/fa2 ffffffff00000000 f13/fa3 ffffffff00000000 f14/fa4 ffffffff00000000 f15/fa5 ffffffff00000000
> f16/fa6 ffffffff00000000 f17/fa7 ffffffff00000000 f18/fs2 ffffffff00000000 f19/fs3 ffffffff00000000
> f20/fs4 ffffffff00000000 f21/fs5 ffffffff00000000 f22/fs6 ffffffff00000000 f23/fs7 ffffffff00000000
> f24/fs8 ffffffff00000000 f25/fs9 ffffffff00000000 f26/fs10 ffffffff00000000 f27/fs11 ffffffff00000000
> f28/ft8 ffffffff00000000 f29/ft9 ffffffff00000000 f30/ft10 ffffffff00000000 f31/ft11 ffffffff00000000
>
> I also wrote a patch to align the first column of register values, but
> that creates the dilemma between aligning the numbers vs keeping the
> spacing between the registers and their value within a row. Aside from
> avoiding bikeshedding, it wastes more columns for an already wide
> output, so opted not to 'fix' that.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> target/riscv/cpu.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
Reviewed-by: Max Chou <max.chou@sifive.com>
Thanks,
rnax
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2026-08-13 3:24 [PATCH] target/riscv: Restore register dump zero padding Joel Stanley
2026-08-13 11:56 ` Anton Johansson via qemu development
2026-08-13 11:56 ` Anton Johansson via
2026-08-14 10:24 ` Max Chou
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