From: Yao Zi <me@ziyao.cc>
To: Troy Mitchell <troy.mitchell@linux.spacemit.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney@redhat.com>, Yixun Lan <dlan@kernel.org>,
Inochi Amaoto <inochiama@outlook.com>,
Alex Elder <elder@riscstar.com>, Haylen Chu <heylenay@4d2.org>
Cc: linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org,
spacemit@lists.linux.dev, linux-kernel@vger.kernel.org,
Yao Zi <me@ziyao.cc>
Subject: Re: [PATCH 1/2] clk: spacemit: re-enable PLLs after init
Date: Tue, 4 Aug 2026 08:10:14 +0000 [thread overview]
Message-ID: <anGeZk0-YShccqwE@pie> (raw)
In-Reply-To: <20260804-k3-pll5-pll8-1800mhz-v1-1-a3a75866ce32@linux.spacemit.com>
On Tue, Aug 04, 2026 at 12:02:55AM -0700, Troy Mitchell wrote:
> The PLL and PLLA init callbacks gate off and reprogram a PLL when its
> firmware configuration is absent from the rate table. However, they
> leave the PLL gated off after updating the registers.
I don't think this patch makes sense.
If this PLL is essential for some components of the systems to work,
there's no chance to re-program it safely after the kernel gets started,
since all the PLLs in K1 and K3 are specified as CLK_SET_RATE_GATE.
If the essential clocks could be re-parented glitchlessly, registering
a notifier and re-parenting it before the PLL disables might be a
solution. In this case, we need to delay the operation in
ccu_pll*_init() until clock registration fully completes.
Otherwise, re-enabling the PLL seems totally extra here, they could be
enabled on the fly when it's going to be used.
> Re-enable the PLL to complete the sequence and propagate any lock
> timeout to clock registration.
Regards,
Yao Zi
> Fixes: 1b72c59db0ad ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
> Fixes: 3a086236c600 ("clk: spacemit: ccu_pll: add plla type clock")
> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
WARNING: multiple messages have this Message-ID (diff)
From: Yao Zi <me@ziyao.cc>
To: Troy Mitchell <troy.mitchell@linux.spacemit.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney@redhat.com>, Yixun Lan <dlan@kernel.org>,
Inochi Amaoto <inochiama@outlook.com>,
Alex Elder <elder@riscstar.com>, Haylen Chu <heylenay@4d2.org>
Cc: linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org,
spacemit@lists.linux.dev, linux-kernel@vger.kernel.org,
Yao Zi <me@ziyao.cc>
Subject: Re: [PATCH 1/2] clk: spacemit: re-enable PLLs after init
Date: Tue, 4 Aug 2026 08:10:14 +0000 [thread overview]
Message-ID: <anGeZk0-YShccqwE@pie> (raw)
In-Reply-To: <20260804-k3-pll5-pll8-1800mhz-v1-1-a3a75866ce32@linux.spacemit.com>
On Tue, Aug 04, 2026 at 12:02:55AM -0700, Troy Mitchell wrote:
> The PLL and PLLA init callbacks gate off and reprogram a PLL when its
> firmware configuration is absent from the rate table. However, they
> leave the PLL gated off after updating the registers.
I don't think this patch makes sense.
If this PLL is essential for some components of the systems to work,
there's no chance to re-program it safely after the kernel gets started,
since all the PLLs in K1 and K3 are specified as CLK_SET_RATE_GATE.
If the essential clocks could be re-parented glitchlessly, registering
a notifier and re-parenting it before the PLL disables might be a
solution. In this case, we need to delay the operation in
ccu_pll*_init() until clock registration fully completes.
Otherwise, re-enabling the PLL seems totally extra here, they could be
enabled on the fly when it's going to be used.
> Re-enable the PLL to complete the sequence and propagate any lock
> timeout to clock registration.
Regards,
Yao Zi
> Fixes: 1b72c59db0ad ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
> Fixes: 3a086236c600 ("clk: spacemit: ccu_pll: add plla type clock")
> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
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next prev parent reply other threads:[~2026-08-04 8:10 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-04 7:02 [PATCH 0/2] clk: spacemit: fix PLL init and add K3 1.8 GHz rates Troy Mitchell
2026-08-04 7:02 ` Troy Mitchell
2026-08-04 7:02 ` [PATCH 1/2] clk: spacemit: re-enable PLLs after init Troy Mitchell
2026-08-04 7:02 ` Troy Mitchell
2026-08-04 8:10 ` Yao Zi [this message]
2026-08-04 8:10 ` Yao Zi
2026-08-10 8:42 ` Troy Mitchell
2026-08-10 8:42 ` Troy Mitchell
2026-08-04 7:02 ` [PATCH 2/2] clk: spacemit: k3: add 1.8 GHz PLL5 and PLL8 rates Troy Mitchell
2026-08-04 7:02 ` Troy Mitchell
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