Re: [PATCH v4 3/4] cxl/hdm: Make switch decoder target parsing endian-safe

[Alison Schofield <alison.schofield@intel.com>]

On Wed, Jul 22, 2026 at 02:07:49AM +0100, Jonathan Cameron wrote:
> On Mon, 20 Jul 2026 18:59:39 -0700
> Alison Schofield <alison.schofield@intel.com> wrote:
> 
> > Switch decoder target IDs are stored one per byte, starting with
> > target 0 in the least significant byte. The current code accesses
> > those bytes in memory order, which only matches register order on
> > little-endian hosts.
> > 
> > On big-endian hosts, the target IDs are reversed and the decoder is
> > associated with the wrong downstream ports.
> > 
> > Extract each target ID from the register value with an explicit shift
> > and mask so the target mapping is independent of host endianness.
> > 
> > Fixes: d17d0540a0db ("cxl/core/hdm: Add CXL standard decoder enumeration to the core")
> > Reviewed-by: Richard Cheng <icheng@nvidia.com>
> > Reviewed-by: Li Ming <ming.li@zohomail.com>
> > Signed-off-by: Alison Schofield <alison.schofield@intel.com>
> 
> Suggestion for explicitly handling the endian issue inline.

Done in v5.


> I'm also fine if you stick with what you have here.
> 
> Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
>
Dropped all the Reviewed-by: tags for that change though. :(