Re: [PATCH v2 3/3] drm/i915/lt_phy: program DDI_CLK_VALFREQ with DDI clock frequency

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Wed, Aug 12, 2026 at 09:20:12AM +0530, Nautiyal, Ankit K wrote:
> 
> On 8/11/2026 11:28 PM, Suraj Kandpal wrote:
> > DDI_CLK_VALFREQ is programmed with the port clock, which for DP is the
> > symbol clock computed assuming 8b/10b encoding (link_rate / 10). For
> > DP 128b/132b (UHBR) rates and for HDMI FRL the port clock needs to
> > be modified.
> > On silicon DDI_CLK_VALFREQ is a scratch register with no
> > functional impact, so the bug is not observed.
> > Use intel_ddi_link_symbol_clock() to write the correct DDI clock in
> > kHz
> > 
> > Fixes: 5ec58d714935 ("drm/i915/lt_phy: Add .enable_clock hook on DDI")

Next time, please be mindful about the -fixes, stable, and customer trees
and keep new helper in the same patch as the fixes.

Thanks,
Rodrigo.

> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> 
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> 
> 
> > ---
> >   drivers/gpu/drm/i915/display/intel_lt_phy.c | 6 ++++--
> >   1 file changed, 4 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > index 8fc6d230493f..86492651b01d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > @@ -1976,7 +1976,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> >   		 * Change. We handle this step in bxt_set_cdclk().
> >   		 */
> >   		/* 10. Program DDI_CLK_VALFREQ to match intended DDI clock frequency. */
> > -		intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
> > +		intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
> > +			       intel_ddi_link_symbol_clock(encoder, port_clock));
> >   		/* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */
> >   		intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> > @@ -2023,7 +2024,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> >   			     lane_phy_pulse_status,
> >   			     lane_phy_pulse_status);
> >   	} else {
> > -		intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
> > +		intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
> > +			       intel_ddi_link_symbol_clock(encoder, port_clock));
> >   	}
> >   	/*