Re: [PATCH v2 2/3] drm/i915/cx0: program DDI_CLK_VALFREQ with DDI clock frequency

["Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>]

On 8/11/2026 11:28 PM, Suraj Kandpal wrote:
> DDI_CLK_VALFREQ is programmed with the port clock, which for DP is the
> symbol clock computed assuming 8b/10b encoding (link_rate / 10). For
> DP 128b/132b (UHBR) rates and for HDMI FRL the port clock needs to
> be modfied.
> On silicon DDI_CLK_VALFREQ is a scratch register with no
> functional impact, so the bug is not observed.
> Use intel_ddi_link_symbol_clock() to write the correct DDI clock in
> kHz.

Perhaps can be re-phrased as :

DDI_CLK_VALFREQ does not configure hardware, it only records the 
frequency software intends to set, so there is no functional impact.

Patch LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


>
> Fixes: 51390cc0e00a ("drm/i915/mtl: Add Support for C10 PHY message bus and pll programming")
> Fixes: 73fc3abcb797 ("drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll")
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_cx0_phy.c | 5 +++--
>   1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 452062417ce9..dbebd7210848 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -3233,7 +3233,8 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
>   	 * 8. Program DDI_CLK_VALFREQ to match intended DDI
>   	 * clock frequency.
>   	 */
> -	intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
> +	intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
> +		       intel_ddi_link_symbol_clock(encoder, port_clock));
>   
>   	/*
>   	 * 9. Set PORT_CLOCK_CTL register PCLK PLL Request
> @@ -3406,7 +3407,7 @@ void intel_mtl_tbt_pll_enable_clock(struct intel_encoder *encoder, int port_cloc
>   	 * clock frequency.
>   	 */
>   	intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
> -		       port_clock);
> +		       intel_ddi_link_symbol_clock(encoder, port_clock));
>   }
>   
>   void intel_mtl_pll_enable(struct intel_encoder *encoder,