From: Max Chou <max.chou@sifive.com>
To: Molly Chen <xiaoou@iscas.ac.cn>
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com,
zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com,
Chao Liu <chao.liu@processmission.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH v2 02/18] target/riscv: Add packed SIMD helper framework
Date: Sun, 16 Aug 2026 23:49:31 +0800 [thread overview]
Message-ID: <aoHbEVwVvB9BMSpW@sifive.com> (raw)
In-Reply-To: <e3775ec9235fa974e9a318edf1836cdaab197e27.1784280142.git.xiaoou@iscas.ac.cn>
On 2026-07-17 10:06, Molly Chen wrote:
> Signed-off-by: Molly Chen <xiaoou@iscas.ac.cn>
> ---
> target/riscv/tcg/meson.build | 3 +-
> target/riscv/tcg/psimd_helper.c | 1656 +++++++++++++++++++++++++++++++
> 2 files changed, 1658 insertions(+), 1 deletion(-)
> create mode 100644 target/riscv/tcg/psimd_helper.c
>
...
> riscv_system_ss.add(files(
> diff --git a/target/riscv/tcg/psimd_helper.c b/target/riscv/tcg/psimd_helper.c
> new file mode 100644
> index 00000000000..2948bbb2a86
> --- /dev/null
> +++ b/target/riscv/tcg/psimd_helper.c
...
> +#define GEN_PSIMD_VAR_USHLR(NAME, RTYPE, ETYPE, WTYPE, EXTRACT, INSERT, \
> + ELEMS, BITS, SAT_FN) \
> +RTYPE HELPER(NAME)(CPURISCVState *env, RTYPE rs1, RTYPE rs2) \
> +{ \
> + RTYPE rd = 0; \
> + int elems = ELEMS(rd); \
> + int sat = 0; \
> + int8_t shamt = (int8_t)(rs2 & 0xff); \
> + \
> + for (int i = 0; i < elems; i++) { \
> + ETYPE e1 = (ETYPE)EXTRACT(rs1, i); \
> + ETYPE res; \
> + \
> + if (shamt >= 0) { \
> + WTYPE shifted = (shamt >= (BITS)) ? \
> + ((WTYPE)e1 << (BITS)) : \
> + ((WTYPE)e1 << shamt); \
> + res = SAT_FN(shifted, &sat); \
> + } else { \
> + int right = -shamt; \
> + if (right > (BITS)) { \
> + res = 0; \
Here may has an issue that a rounding right shift past the element
width does not degenerate to zero -- it saturates to the rounding of
the element's MSB.
According to the P ext isa spec:
"The SSHLR instruction performs an unsigned variable shift of `rs1`
using the signed shift amount in `rs2[7:0]`. Right shifts are
rounded, and left shifts saturate to the signed 32-bit range."
if sshamt < 0:
// arithmetic right shift with rounding
x = zero_extend(64, s1) @ 0b0 // 65-bit
y = (sshamt <= -32) ? x[64:32]
: (x >> (0 - shamt)[4:0])[32:0]
X[rd] = (y + 1)[32:1]
The operation Sail code shows that every right shift at or beyond
the element width collapses to the same x[64:32], which is the
element's MSB, and then still gets the (y + 1) >> 1 rounding.
PSSHLR.HS and PSSHLR.WS have the identical construct at the 16- and
32-bit boundaries.
Maybe we could fix it liked:
} else { \
int right = MIN(-shamt, (BITS)); \
WTYPE rounded = ((WTYPE)e1 >> (right - 1)) + 1; \
res = (ETYPE)(rounded >> 1); \
} \
rnax
> + } else { \
> + WTYPE rounded = ((WTYPE)e1 >> (right - 1)) + 1; \
> + res = (ETYPE)(rounded >> 1); \
> + } \
> + } \
next prev parent reply other threads:[~2026-08-16 15:49 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-17 10:06 [PATCH v2 00/18] target/riscv: Add support for RISC-V P Molly Chen
2026-07-17 10:06 ` [PATCH v2 01/18] target/riscv: Add packed SIMD extension state Molly Chen
2026-07-26 19:32 ` Daniel Henrique Barboza
2026-07-27 6:13 ` Nutty.Liu
2026-07-29 8:43 ` Chao Liu
2026-07-17 10:06 ` [PATCH v2 02/18] target/riscv: Add packed SIMD helper framework Molly Chen
2026-07-26 19:53 ` Daniel Henrique Barboza
2026-07-27 6:16 ` Nutty.Liu
2026-07-29 9:01 ` Chao Liu
2026-08-16 15:49 ` Max Chou [this message]
2026-07-17 10:06 ` [PATCH v2 03/18] target/riscv: Add packed SIMD arithmetic instructions Molly Chen
2026-07-26 22:05 ` Daniel Henrique Barboza
2026-07-29 6:17 ` Nutty.Liu
2026-07-29 9:27 ` Chao Liu
2026-08-16 16:32 ` Max Chou
2026-07-17 10:06 ` [PATCH v2 04/18] target/riscv: Add packed SIMD averaging and rounding instructions Molly Chen
2026-07-27 18:58 ` Daniel Henrique Barboza
2026-07-17 10:06 ` [PATCH v2 05/18] target/riscv: Add packed SIMD absolute, difference, compare and mask instructions Molly Chen
2026-07-17 10:06 ` [PATCH v2 06/18] target/riscv: Add packed SIMD shift instructions Molly Chen
2026-07-17 10:07 ` [PATCH v2 07/18] target/riscv: Add packed SIMD exchange instructions Molly Chen
2026-07-17 10:07 ` [PATCH v2 08/18] target/riscv: Add packed SIMD horizontal reduction instructions Molly Chen
2026-07-17 10:07 ` [PATCH v2 09/18] target/riscv: Add packed SIMD pack, merge and count-leading instructions Molly Chen
2026-07-17 10:07 ` [PATCH v2 10/18] target/riscv: Add packed SIMD multiplication instructions Molly Chen
2026-07-17 10:07 ` [PATCH v2 11/18] target/riscv: Add packed SIMD multiply-accumulate instructions Molly Chen
2026-07-17 10:07 ` [PATCH v2 12/18] target/riscv: Add packed SIMD Q-format multiplication instructions Molly Chen
2026-07-17 10:07 ` [PATCH v2 13/18] target/riscv: Add packed SIMD Q-format MAC instructions Molly Chen
2026-07-17 10:07 ` [PATCH v2 14/18] target/riscv: Add packed SIMD two-way " Molly Chen
2026-07-17 10:07 ` [PATCH v2 15/18] target/riscv: Add packed SIMD four-way " Molly Chen
2026-07-17 10:07 ` [PATCH v2 16/18] target/riscv: Add packed SIMD load-replicate instructions Molly Chen
2026-07-17 10:07 ` [PATCH v2 17/18] target/riscv: Add packed SIMD RV32 only instructions Molly Chen
2026-07-17 10:07 ` [PATCH v2 18/18] target/riscv: Remove Zbkb dependency from P extension to align with the spec Molly Chen
2026-08-03 2:26 ` Chao Liu
2026-07-29 8:43 ` [PATCH v2 00/18] target/riscv: Add support for RISC-V P Chao Liu
2026-07-29 9:32 ` Chao Liu
2026-08-05 18:36 ` Daniel Henrique Barboza
2026-08-11 7:54 ` MOLLY CHEN
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