[PATCH 0/2] target/riscv: Handle [ms]status updates for rv128

[PATCH 0/2] target/riscv: Handle [ms]status updates for rv128

[frederic.petrot]

From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>

Correct sstatus update and allow support for rv128 in mstatus,
provided the cpu is an rv128.

Changes compared to v1:
- add cover letter
- add the Reviewed-by tags

Frédéric Pétrot (2):
  target/riscv: Fix sstatus update in rv128
  target/riscv: Allow UXL to be 3 in mstatus on rv128

 target/riscv/tcg/csr.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

-- 
2.43.0

[PATCH v2 1/2] target/riscv: Fix sstatus update in rv128

[frederic.petrot]

From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>

The sstatus register assignment was performed before the write
mask was fully constructed, leading to an incomplete update of
sstatus fields on the experimental rv128 target.

Move the sstatus write after the mask completion so the full
write mask is applied correctly.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/tcg/csr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
index ffd751caa5..9cc6297328 100644
--- a/target/riscv/tcg/csr.c
+++ b/target/riscv/tcg/csr.c
@@ -3998,7 +3998,7 @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
                                         Int128 *val)
 {
     uint64_t mask = sstatus_v1_10_mask;
-    uint64_t sstatus = env->mstatus & mask;
+    uint64_t sstatus;
     if (env->xl != MXL_RV32 || env->debugger) {
         mask |= SSTATUS64_UXL;
     }
@@ -4009,7 +4009,7 @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
     if (env_archcpu(env)->cfg.ext_zicfilp) {
         mask |= SSTATUS_SPELP;
     }
-
+    sstatus = env->mstatus & mask;
     *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus));
     return RISCV_EXCP_NONE;
 }
-- 
2.43.0

Re: [PATCH v2 1/2] target/riscv: Fix sstatus update in rv128

[Chao Liu via]

On Wed, Aug 19, 2026 at 12:56:54PM +0800, frederic.petrot@univ-grenoble-alpes.fr wrote:
> From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> 
> The sstatus register assignment was performed before the write
> mask was fully constructed, leading to an incomplete update of
> sstatus fields on the experimental rv128 target.
> 
> Move the sstatus write after the mask completion so the full
> write mask is applied correctly.
> 
> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> ---
>  target/riscv/tcg/csr.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
> index ffd751caa5..9cc6297328 100644
> --- a/target/riscv/tcg/csr.c
> +++ b/target/riscv/tcg/csr.c
> @@ -3998,7 +3998,7 @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
>                                          Int128 *val)
>  {
>      uint64_t mask = sstatus_v1_10_mask;
> -    uint64_t sstatus = env->mstatus & mask;
> +    uint64_t sstatus;
>      if (env->xl != MXL_RV32 || env->debugger) {
>          mask |= SSTATUS64_UXL;
>      }
> @@ -4009,7 +4009,7 @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
>      if (env_archcpu(env)->cfg.ext_zicfilp) {
>          mask |= SSTATUS_SPELP;
>      }
> -
> +    sstatus = env->mstatus & mask;
>      *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus));
>      return RISCV_EXCP_NONE;
>  }
> -- 
> 2.43.0
> 

Re: [PATCH v2 1/2] target/riscv: Fix sstatus update in rv128

[Chao Liu via qemu development]

On Wed, Aug 19, 2026 at 12:56:54PM +0800, frederic.petrot@univ-grenoble-alpes.fr wrote:
> From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> 
> The sstatus register assignment was performed before the write
> mask was fully constructed, leading to an incomplete update of
> sstatus fields on the experimental rv128 target.
> 
> Move the sstatus write after the mask completion so the full
> write mask is applied correctly.
> 
> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> ---
>  target/riscv/tcg/csr.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
> index ffd751caa5..9cc6297328 100644
> --- a/target/riscv/tcg/csr.c
> +++ b/target/riscv/tcg/csr.c
> @@ -3998,7 +3998,7 @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
>                                          Int128 *val)
>  {
>      uint64_t mask = sstatus_v1_10_mask;
> -    uint64_t sstatus = env->mstatus & mask;
> +    uint64_t sstatus;
>      if (env->xl != MXL_RV32 || env->debugger) {
>          mask |= SSTATUS64_UXL;
>      }
> @@ -4009,7 +4009,7 @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
>      if (env_archcpu(env)->cfg.ext_zicfilp) {
>          mask |= SSTATUS_SPELP;
>      }
> -
> +    sstatus = env->mstatus & mask;
>      *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus));
>      return RISCV_EXCP_NONE;
>  }
> -- 
> 2.43.0
> 

[PATCH v2 2/2] target/riscv: Allow UXL to be 3 in mstatus on rv128

[frederic.petrot]

From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>

Valid UXL field values for mstatus were restricted to fix a
reported issue, but this inadvertently broke the experimental
rv128 support where a value of 3 validly represents 128-bit
execution.

Update the mstatus write logic to permit UXL=3 when running on
an rv128 CPU.

Fixes: dcd028517749 ("target/riscv: Apply UXL WARL handling to vsstatus")
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
 target/riscv/tcg/csr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
index 9cc6297328..4c8959a33d 100644
--- a/target/riscv/tcg/csr.c
+++ b/target/riscv/tcg/csr.c
@@ -2014,8 +2014,8 @@ static uint64_t riscv_write_uxl(CPURISCVState *env, uint64_t val,
     RISCVMXL xl = riscv_cpu_mxl(env);
     uint64_t uxl = get_field(val, field);
 
-    if (uxl == MXL_RV128) {
-        uxl = xl == MXL_RV128 ? MXL_RV64 : xl;
+    if (xl != MXL_RV128 && uxl == MXL_RV128) {
+        uxl = xl;
         val = set_field(val, field, uxl);
     }
 
-- 
2.43.0

Re: [PATCH v2 2/2] target/riscv: Allow UXL to be 3 in mstatus on rv128

[Chao Liu via]

On Wed, Aug 19, 2026 at 12:56:55PM +0800, frederic.petrot@univ-grenoble-alpes.fr wrote:
> From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> 
> Valid UXL field values for mstatus were restricted to fix a
> reported issue, but this inadvertently broke the experimental
> rv128 support where a value of 3 validly represents 128-bit
> execution.
> 
> Update the mstatus write logic to permit UXL=3 when running on
> an rv128 CPU.
> 
> Fixes: dcd028517749 ("target/riscv: Apply UXL WARL handling to vsstatus")
> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> ---
>  target/riscv/tcg/csr.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
> index 9cc6297328..4c8959a33d 100644
> --- a/target/riscv/tcg/csr.c
> +++ b/target/riscv/tcg/csr.c
> @@ -2014,8 +2014,8 @@ static uint64_t riscv_write_uxl(CPURISCVState *env, uint64_t val,
>      RISCVMXL xl = riscv_cpu_mxl(env);
>      uint64_t uxl = get_field(val, field);
>  
> -    if (uxl == MXL_RV128) {
> -        uxl = xl == MXL_RV128 ? MXL_RV64 : xl;
> +    if (xl != MXL_RV128 && uxl == MXL_RV128) {
> +        uxl = xl;
>          val = set_field(val, field, uxl);
>      }
>  
> -- 
> 2.43.0
> 

Re: [PATCH v2 2/2] target/riscv: Allow UXL to be 3 in mstatus on rv128

[Chao Liu via qemu development]

On Wed, Aug 19, 2026 at 12:56:55PM +0800, frederic.petrot@univ-grenoble-alpes.fr wrote:
> From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> 
> Valid UXL field values for mstatus were restricted to fix a
> reported issue, but this inadvertently broke the experimental
> rv128 support where a value of 3 validly represents 128-bit
> execution.
> 
> Update the mstatus write logic to permit UXL=3 when running on
> an rv128 CPU.
> 
> Fixes: dcd028517749 ("target/riscv: Apply UXL WARL handling to vsstatus")
> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> ---
>  target/riscv/tcg/csr.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
> index 9cc6297328..4c8959a33d 100644
> --- a/target/riscv/tcg/csr.c
> +++ b/target/riscv/tcg/csr.c
> @@ -2014,8 +2014,8 @@ static uint64_t riscv_write_uxl(CPURISCVState *env, uint64_t val,
>      RISCVMXL xl = riscv_cpu_mxl(env);
>      uint64_t uxl = get_field(val, field);
>  
> -    if (uxl == MXL_RV128) {
> -        uxl = xl == MXL_RV128 ? MXL_RV64 : xl;
> +    if (xl != MXL_RV128 && uxl == MXL_RV128) {
> +        uxl = xl;
>          val = set_field(val, field, uxl);
>      }
>  
> -- 
> 2.43.0
> 

Re: [PATCH 0/2] target/riscv: Handle [ms]status updates for rv128

[Philippe Mathieu-Daudé]

Hi Frédéric,

On 19/8/26 12:56, frederic.petrot@univ-grenoble-alpes.fr wrote:
> From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> 
> Correct sstatus update and allow support for rv128 in mstatus,
> provided the cpu is an rv128.
> 
> Changes compared to v1:
> - add cover letter
> - add the Reviewed-by tags
> 
> Frédéric Pétrot (2):
>    target/riscv: Fix sstatus update in rv128
>    target/riscv: Allow UXL to be 3 in mstatus on rv128

How can we test this series?