[PATCH v2 0/3] arm64: dts: imx9x: Fix PCIe memory window overlap with System RAM

[PATCH v2 0/3] arm64: dts: imx9x: Fix PCIe memory window overlap with System RAM

[hongxing.zhu]

This patch series fix PCIe non-prefetchable memory window overlap with
system DRAM on i.MX9 series SoCs (imx95, imx94, and imx943).

The current address 0xe0000000 conflicts with DRAM regions. Sashiko
reports the potential issue in previous review:

The fix relocates the PCI bus address to 0x10000000, a reserved and safe
range. The other PCI bus address and window size remain unchanged.

Changes in v2:
Clarified that the adddress being corrected is the PCI bus address in
the commits.

Richard Zhu (3):
  arm64: dts: imx95: Avoid 32-bit PCIe window System RAM overlap
  arm64: dts: imx94: Avoid 32-bit pcie window system ram overlap
  arm64: dts: imx943: Avoid 32-bit PCIe window System RAM overlap

[PATCH v2 1/3] arm64: dts: imx95: Avoid 32-bit PCIe window System RAM
[PATCH v2 2/3] arm64: dts: imx94: Avoid 32-bit PCIe window System RAM
[PATCH v2 3/3] arm64: dts: imx943: Avoid 32-bit PCIe window System

arch/arm64/boot/dts/freescale/imx94.dtsi  | 2 +-
arch/arm64/boot/dts/freescale/imx943.dtsi | 2 +-
arch/arm64/boot/dts/freescale/imx95.dtsi  | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)

[PATCH v2 1/3] arm64: dts: imx95: Avoid 32-bit PCIe window System RAM overlap

[hongxing.zhu]

From: Richard Zhu <hongxing.zhu@nxp.com>

Move the PCIe non-prefetchable memory PCI bus address from 0xe0000000
to 0x10000000 to avoid overlap with DRAM. The 0x10000000 range is
reserved and safe to use.

Fixes: dbecf38e60d4e ("arm64: dts: imx95: Correct PCIe outbound address space configuration")
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx95.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index 38fc47024841f..0f03b85aaec17 100644
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -1948,7 +1948,7 @@ pcie0: pcie@4c300000 {
 			      <0 0x4c340000 0 0x4000>;
 			reg-names = "dbi", "config", "atu", "app";
 			ranges = <0x43000000 0x9 0x00000000 0x9 0x00000000 0x0 0xe0000000>,
-				 <0x82000000 0x0 0xe0000000 0x9 0xe0000000 0x0 0x10000000>,
+				 <0x82000000 0x0 0x10000000 0x9 0xe0000000 0x0 0x10000000>,
 				 <0x81000000 0x0 0x00000000 0x9 0xf0000000 0x0 0x00100000>;
 			#address-cells = <3>;
 			#size-cells = <2>;
@@ -2039,7 +2039,7 @@ pcie1: pcie@4c380000 {
 			      <0 0x4c3c0000 0 0x4000>;
 			reg-names = "dbi", "config", "atu", "app";
 			ranges = <0x43000000 0xa 0x00000000 0xa 0x00000000 0x0 0xe0000000>,
-				 <0x82000000 0x0 0xe0000000 0xa 0xe0000000 0x0 0x10000000>,
+				 <0x82000000 0x0 0x10000000 0xa 0xe0000000 0x0 0x10000000>,
 				 <0x81000000 0x0 0x00000000 0xa 0xf0000000 0x0 0x00100000>;
 			#address-cells = <3>;
 			#size-cells = <2>;

base-commit: eba4724641990bd9975ca10ababe726b6143f0b6
-- 
2.34.1

Re: [PATCH v2 1/3] arm64: dts: imx95: Avoid 32-bit PCIe window System RAM overlap

[Frank Li]

On Fri, Aug 21, 2026 at 01:43:32PM +0800, hongxing.zhu@oss.nxp.com wrote:
> From: Richard Zhu <hongxing.zhu@nxp.com>
>
> Move the PCIe non-prefetchable memory PCI bus address from 0xe0000000
> to 0x10000000 to avoid overlap with DRAM. The 0x10000000 range is
> reserved and safe to use.
>

If you agree, I put layerscape discussion link at here when apply

link: https://lore.kernel.org/imx/753fca23-c3eb-45e3-aeac-b7b248fa723a@app.fastmail.com/ [1]

Frank

> Fixes: dbecf38e60d4e ("arm64: dts: imx95: Correct PCIe outbound address space configuration")
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx95.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> index 38fc47024841f..0f03b85aaec17 100644
> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> @@ -1948,7 +1948,7 @@ pcie0: pcie@4c300000 {
>  			      <0 0x4c340000 0 0x4000>;
>  			reg-names = "dbi", "config", "atu", "app";
>  			ranges = <0x43000000 0x9 0x00000000 0x9 0x00000000 0x0 0xe0000000>,
> -				 <0x82000000 0x0 0xe0000000 0x9 0xe0000000 0x0 0x10000000>,
> +				 <0x82000000 0x0 0x10000000 0x9 0xe0000000 0x0 0x10000000>,
>  				 <0x81000000 0x0 0x00000000 0x9 0xf0000000 0x0 0x00100000>;
>  			#address-cells = <3>;
>  			#size-cells = <2>;
> @@ -2039,7 +2039,7 @@ pcie1: pcie@4c380000 {
>  			      <0 0x4c3c0000 0 0x4000>;
>  			reg-names = "dbi", "config", "atu", "app";
>  			ranges = <0x43000000 0xa 0x00000000 0xa 0x00000000 0x0 0xe0000000>,
> -				 <0x82000000 0x0 0xe0000000 0xa 0xe0000000 0x0 0x10000000>,
> +				 <0x82000000 0x0 0x10000000 0xa 0xe0000000 0x0 0x10000000>,
>  				 <0x81000000 0x0 0x00000000 0xa 0xf0000000 0x0 0x00100000>;
>  			#address-cells = <3>;
>  			#size-cells = <2>;
>
> base-commit: eba4724641990bd9975ca10ababe726b6143f0b6
> --
> 2.34.1
>
>

RE: [PATCH v2 1/3] arm64: dts: imx95: Avoid 32-bit PCIe window System RAM overlap

[Hongxing Zhu (OSS)]

> -----Original Message-----
> From: Frank Li (OSS) <frank.li@oss.nxp.com>
> Sent: Friday, August 21, 2026 10:47 PM
> To: Hongxing Zhu (OSS) <hongxing.zhu@oss.nxp.com>
> Cc: robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org; Frank Li
> <frank.li@nxp.com>; s.hauer@pengutronix.de; festevam@gmail.com;
> kernel@pengutronix.de; devicetree@vger.kernel.org; imx@lists.linux.dev; linux-
> arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux@ew.tq-
> group.com; Hongxing Zhu <hongxing.zhu@nxp.com>
> Subject: Re: [PATCH v2 1/3] arm64: dts: imx95: Avoid 32-bit PCIe window
> System RAM overlap
> 
> On Fri, Aug 21, 2026 at 01:43:32PM +0800, hongxing.zhu@oss.nxp.com wrote:
> > From: Richard Zhu <hongxing.zhu@nxp.com>
> >
> > Move the PCIe non-prefetchable memory PCI bus address from 0xe0000000
> > to 0x10000000 to avoid overlap with DRAM. The 0x10000000 range is
> > reserved and safe to use.
> >
> 
> If you agree, I put layerscape discussion link at here when apply
> 
> link: https://lore.kernel.org/imx/753fca23-c3eb-45e3-aeac-
> b7b248fa723a@app.fastmail.com/ [1]
I'm total agree with it. Thanks.
BTW, sorry to rely late.

Best Regards
Richard Zhu
> 
> Frank
> 
> > Fixes: dbecf38e60d4e ("arm64: dts: imx95: Correct PCIe outbound
> > address space configuration")
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/imx95.dtsi | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi
> > b/arch/arm64/boot/dts/freescale/imx95.dtsi
> > index 38fc47024841f..0f03b85aaec17 100644
> > --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> > @@ -1948,7 +1948,7 @@ pcie0: pcie@4c300000 {
> >  			      <0 0x4c340000 0 0x4000>;
> >  			reg-names = "dbi", "config", "atu", "app";
> >  			ranges = <0x43000000 0x9 0x00000000 0x9
> 0x00000000 0x0 0xe0000000>,
> > -				 <0x82000000 0x0 0xe0000000 0x9
> 0xe0000000 0x0 0x10000000>,
> > +				 <0x82000000 0x0 0x10000000 0x9
> 0xe0000000 0x0 0x10000000>,
> >  				 <0x81000000 0x0 0x00000000 0x9
> 0xf0000000 0x0 0x00100000>;
> >  			#address-cells = <3>;
> >  			#size-cells = <2>;
> > @@ -2039,7 +2039,7 @@ pcie1: pcie@4c380000 {
> >  			      <0 0x4c3c0000 0 0x4000>;
> >  			reg-names = "dbi", "config", "atu", "app";
> >  			ranges = <0x43000000 0xa 0x00000000 0xa
> 0x00000000 0x0 0xe0000000>,
> > -				 <0x82000000 0x0 0xe0000000 0xa
> 0xe0000000 0x0 0x10000000>,
> > +				 <0x82000000 0x0 0x10000000 0xa
> 0xe0000000 0x0 0x10000000>,
> >  				 <0x81000000 0x0 0x00000000 0xa
> 0xf0000000 0x0 0x00100000>;
> >  			#address-cells = <3>;
> >  			#size-cells = <2>;
> >
> > base-commit: eba4724641990bd9975ca10ababe726b6143f0b6
> > --
> > 2.34.1
> >
> >

[PATCH v2 2/3] arm64: dts: imx94: Avoid 32-bit PCIe window System RAM overlap

[hongxing.zhu]

From: Richard Zhu <hongxing.zhu@nxp.com>

Move the PCIe non-prefetchable memory PCI bus address from 0xe0000000
to 0x10000000 to avoid overlap with DRAM. The 0x10000000 range is
reserved and safe to use.

Fixes: ffccbd6804e88 ("arm64: dts: imx94: Correct PCIe outbound address space configuration")
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx94.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi
index 34833e62bd796..afaaf70417d23 100644
--- a/arch/arm64/boot/dts/freescale/imx94.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx94.dtsi
@@ -1379,7 +1379,7 @@ pcie0: pcie@4c300000 {
 			      <0 0x4c340000 0 0x4000>;
 			reg-names = "dbi", "config", "atu", "app";
 			ranges = <0x43000000 0x9 0x00000000 0x9 0x00000000 0x0 0xe0000000>,
-				 <0x82000000 0x0 0xe0000000 0x9 0xe0000000 0x0 0x10000000>,
+				 <0x82000000 0x0 0x10000000 0x9 0xe0000000 0x0 0x10000000>,
 				 <0x81000000 0x0 0x00000000 0x9 0xf0000000 0x0 0x00100000>;
 			#address-cells = <3>;
 			#size-cells = <2>;
-- 
2.34.1

[PATCH v2 3/3] arm64: dts: imx943: Avoid 32-bit PCIe window System RAM overlap

[hongxing.zhu]

From: Richard Zhu <hongxing.zhu@nxp.com>

Move the PCIe non-prefetchable memory PCI bus address from 0xe0000000
to 0x10000000 to avoid overlap with DRAM. The 0x10000000 range is
reserved and safe to use.

Fixes: 6de3a7d7a4f65 ("arm64: dts: imx943: Correct PCIe outbound address space configuration")
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx943.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
index 01152fd0efa5e..a564488d9cd7d 100644
--- a/arch/arm64/boot/dts/freescale/imx943.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
@@ -219,7 +219,7 @@ pcie1: pcie@4c380000 {
 			      <0 0x4c3c0000 0 0x4000>;
 			reg-names = "dbi", "config", "atu", "app";
 			ranges = <0x43000000 0xa 0x00000000 0xa 0x00000000 0x0 0xe0000000>,
-				 <0x82000000 0x0 0xe0000000 0xa 0xe0000000 0x0 0x10000000>,
+				 <0x82000000 0x0 0x10000000 0xa 0xe0000000 0x0 0x10000000>,
 				 <0x81000000 0x0 0x00000000 0xa 0xf0000000 0x0 0x00100000>;
 			#address-cells = <3>;
 			#size-cells = <2>;
-- 
2.34.1

Re: [PATCH v2 0/3] arm64: dts: imx9x: Fix PCIe memory window overlap with System RAM

[Frank.Li]

From: Frank Li <Frank.Li@nxp.com>


On Fri, 21 Aug 2026 13:43:31 +0800, hongxing.zhu@oss.nxp.com wrote:
> This patch series fix PCIe non-prefetchable memory window overlap with
> system DRAM on i.MX9 series SoCs (imx95, imx94, and imx943).
>
> The current address 0xe0000000 conflicts with DRAM regions. Sashiko
> reports the potential issue in previous review:
>
> The fix relocates the PCI bus address to 0x10000000, a reserved and safe
> range. The other PCI bus address and window size remain unchanged.
>
> [...]

Applied, thanks!

[1/3] arm64: dts: imx95: Avoid 32-bit PCIe window System RAM overlap
      commit: 9094eb07b3e236233dbaac61ed30cc65be9e9c6c
[2/3] arm64: dts: imx94: Avoid 32-bit PCIe window System RAM overlap
      commit: 775ebd246092294432895f8e9bd48e3f0a56714a
[3/3] arm64: dts: imx943: Avoid 32-bit PCIe window System RAM overlap
      commit: fff67007ad5403966092006867fe9926aaedda0d

Commit message add discuss link and "Avoid hit this as a P2P transfer[1]."

Best regards,
--
Frank Li <Frank.Li@nxp.com>