[PATCH 0/5] target/riscv: support Debug 0.13 and 1.0

[PATCH 0/5] target/riscv: support Debug 0.13 and 1.0

[Daniel Henrique Barboza]

Hi,

This short series adds support for Debug 0.13 and Debug 1.0.  The
motivation is simple: we need Debug 1.0 to complete tue upstreaming of
sdext, which is already fully reviewed and acked for awhile [1], and
then proceed with the upstreaming of the RISC-V Server Ref board
(currently on v8: [2]).

The work is based in section 1.2.1.2 "Incompatible Changes from 0.13 to
1.0" of the ratified 1.0 spec [3].  It ended being simpler than
anticipated because we don't implement most of the registers/bits that
are backwards incompatible.  I added doc changes to explain the
rationale used.

After this series:

- 'ext_sdtrig' refers to Debug 1.0.  The legacy 'debug' flag refers to
  Debug 0.13;
- setting both flags enables Debug 1.0, i.e. 'ext_sdtrig' takes
  precedence.

My hope is that this split will make it easier to to move away from
Debug 0.13 in the future once there's no more demand for it.

Patches based on master.

[1] https://lore.kernel.org/qemu-devel/cover.1775959096.git.chao.liu.zevorn@gmail.com/
[2] https://lore.kernel.org/qemu-devel/20260610214133.1882563-1-daniel.barboza@oss.qualcomm.com/
[3] https://docs.riscv.org/reference/debug/v1.0/_attachments/riscv-debug-specification.pdf

Daniel Henrique Barboza (5):
  target/riscv: split 'debug' and 'sdtrig' flags
  target/riscv/tcg/debug.c: add Debug 1.0 'pending' bit
  target/riscv/tcg/debug: adjust 'timing' bit for Debug 1.0
  target/riscv/tcg/debug: set tinfo version if sdtrig enabled
  docs/specs: add RISC-V CPU Debug support info

 docs/specs/index.rst              |  1 +
 docs/specs/riscv-debug.rst        | 68 +++++++++++++++++++++++++++++++
 target/riscv/cpu.c                | 21 +++++++---
 target/riscv/cpu_cfg_fields.h.inc |  1 +
 target/riscv/machine.c            |  2 +-
 target/riscv/tcg/csr.c            |  2 +-
 target/riscv/tcg/debug.c          | 51 +++++++++++++++++++++--
 target/riscv/tcg/debug.h          |  6 ++-
 target/riscv/tcg/tcg-cpu.c        |  3 +-
 9 files changed, 142 insertions(+), 13 deletions(-)
 create mode 100644 docs/specs/riscv-debug.rst

-- 
2.43.0

[PATCH 1/5] target/riscv: split 'debug' and 'sdtrig' flags

[Daniel Henrique Barboza]

We need to support modern debug extensions that happens to be
dependencies of other things that we want to support (e.g. a riscv
server spec board).  These extensions, namely sdext, depends on Debug
1.0.  At this moment we support Debug 0.13, and so it happens that 0.13
and 1.0 aren't backwards compatible, i.e. we need design changes to
support both.

The easier way is to deprecate the Debug 0.13 support, together with its
legacy 'debug' flag and call it a day.  But there's a demand to keep the
0.13 support around and this idea got scrapped.

We're going to support both 0.13 and 1.0, where the 'debug' flag will
refer to 0.13 and 'sdtrig' to 1.0.  We need to split both in distinct
flags first to handle the backend changes, so:

- add a new cpu->cfg.ext_sdtrig flag;
- all code that checks "if debug enabled" now checks for both debug and
  ext_sdtrig;
- amend riscv_isa_string_ext() to keep adding 'sdtrig' in riscv,isa if
  we have just the 'debug' flag enabled.

Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
 target/riscv/cpu.c                | 21 ++++++++++++++++-----
 target/riscv/cpu_cfg_fields.h.inc |  1 +
 target/riscv/machine.c            |  2 +-
 target/riscv/tcg/csr.c            |  2 +-
 target/riscv/tcg/tcg-cpu.c        |  3 ++-
 5 files changed, 21 insertions(+), 8 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5a82e6563b..db4f2b6459 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -247,7 +247,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
     ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
     ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
-    ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, debug),
+    ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, ext_sdtrig),
     ISA_INTERNAL_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0,
                                 has_priv_1_12),
     ISA_INTERNAL_EXT_DATA_ENTRY(sha, PRIV_VERSION_1_12_0, ext_sha),
@@ -1079,7 +1079,7 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
 
 #ifndef CONFIG_USER_ONLY
 #ifdef CONFIG_TCG
-    if (cpu->cfg.debug) {
+    if (cpu->cfg.debug || cpu->cfg.ext_sdtrig) {
         riscv_trigger_reset_hold(env);
     }
 #endif
@@ -1241,7 +1241,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     riscv_cpu_register_gdb_regs_for_features(cs);
 
 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
-    if (cpu->cfg.debug) {
+    if (cpu->cfg.debug || cpu->cfg.ext_sdtrig) {
         riscv_trigger_realize(&cpu->env);
     }
 #endif
@@ -1258,7 +1258,7 @@ static void riscv_cpu_unrealize(DeviceState *dev)
 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
     RISCVCPU *cpu = RISCV_CPU(dev);
 
-    if (cpu->cfg.debug) {
+    if (cpu->cfg.debug || cpu->cfg.ext_sdtrig) {
         riscv_trigger_unrealize(&cpu->env);
     }
 #endif
@@ -2834,6 +2834,11 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
 };
 
 static const Property riscv_cpu_properties[] = {
+    /*
+     * The 'debug' flag enables support for the legacy Debug
+     * 0.13 spec.  In case cpu->ext.ext_sdtrig is also enabled
+     * the CPU will enable Debug 1.0 instead.
+     */
     DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
     DEFINE_PROP_BOOL("big-endian", RISCVCPU, cfg.big_endian, false),
 
@@ -3055,7 +3060,13 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
     char *new = *isa_str;
 
     for (edata = isa_edata_arr; edata && edata->name; edata++) {
-        if (isa_ext_is_enabled(cpu, edata->ext_enable_offset)) {
+        if (isa_ext_is_enabled(cpu, edata->ext_enable_offset)
+            /*
+             * We've been adding 'sdtrig' in riscv,isa for
+             * Debug 0.13 for awhile.  Until we decide to
+             * move away from it we'll keep doing it.
+             */
+            || (!g_strcmp0(edata->name, "sdtrig") && cpu->cfg.debug)) {
             new = g_strconcat(old, "_", edata->name, NULL);
             g_free(old);
             old = new;
diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
index 9eb47af0a7..e32af40c90 100644
--- a/target/riscv/cpu_cfg_fields.h.inc
+++ b/target/riscv/cpu_cfg_fields.h.inc
@@ -105,6 +105,7 @@ BOOL_FIELD(ext_zvfbfmin)
 BOOL_FIELD(ext_zvfbfwma)
 BOOL_FIELD(ext_zvfh)
 BOOL_FIELD(ext_zvfhmin)
+BOOL_FIELD(ext_sdtrig)
 BOOL_FIELD(ext_smaia)
 BOOL_FIELD(ext_ssaia)
 BOOL_FIELD(ext_smctr)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 0ab613a298..a744462d48 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -228,7 +228,7 @@ static bool debug_needed(void *opaque)
 {
     RISCVCPU *cpu = opaque;
 
-    return cpu->cfg.debug;
+    return cpu->cfg.debug || cpu->cfg.ext_sdtrig;
 }
 
 static int debug_post_load(void *opaque, int version_id)
diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
index 36f2004bc5..850fbf32fc 100644
--- a/target/riscv/tcg/csr.c
+++ b/target/riscv/tcg/csr.c
@@ -804,7 +804,7 @@ static RISCVException have_mseccfg(CPURISCVState *env, int csrno)
 
 static RISCVException debug(CPURISCVState *env, int csrno)
 {
-    if (riscv_cpu_cfg(env)->debug) {
+    if (riscv_cpu_cfg(env)->debug || riscv_cpu_cfg(env)->ext_sdtrig) {
         return RISCV_EXCP_NONE;
     }
 
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 4af5cd9c73..02bbdaef8e 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -182,7 +182,8 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)
              ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED;
     }
 
-    if (cpu->cfg.debug && !icount_enabled()) {
+    if ((cpu->cfg.debug || cpu->cfg.ext_sdtrig)
+        && !icount_enabled()) {
         flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
     }
 #endif
-- 
2.43.0

[PATCH 2/5] target/riscv/tcg/debug.c: add Debug 1.0 'pending' bit

[Daniel Henrique Barboza]

We need to set the 'pending' bit when 'count' reaches 0, clearing it right
after the trigger fires.

This is 1.0 exclusive behavior so no changes are needed when running Debug
0.13.

Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
 target/riscv/tcg/debug.c | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c
index 3c0fe70101..2191928761 100644
--- a/target/riscv/tcg/debug.c
+++ b/target/riscv/tcg/debug.c
@@ -77,6 +77,11 @@ static int access_size[SIZE_NUM] = {
     [6 ... 15] = -1,
 };
 
+static bool debug_trigger_version_1_0(CPURISCVState *env)
+{
+    return riscv_cpu_cfg(env)->ext_sdtrig;
+}
+
 static inline target_ulong extract_trigger_type(CPURISCVState *env,
                                                 target_ulong tdata1)
 {
@@ -684,6 +689,17 @@ itrigger_set_count(CPURISCVState *env, int index, int value)
                                    ITRIGGER_COUNT, value);
 }
 
+static inline void
+itrigger_set_pending(CPURISCVState *env, int index, int val)
+{
+    if (!debug_trigger_version_1_0(env)) {
+        return;
+    }
+
+    env->tdata1[index] = set_field(env->tdata1[index],
+                                   ITRIGGER_PENDING, val);
+}
+
 static bool check_itrigger_priv(CPURISCVState *env, int index)
 {
     target_ulong tdata1 = env->tdata1[index];
@@ -735,8 +751,25 @@ void helper_itrigger_match(CPURISCVState *env)
         }
         itrigger_set_count(env, i, count--);
         if (!count) {
+            /*
+             * From the 1.0 spec: "When pending is set, the trigger
+             * fires just before any further instructions are executed
+             * in a mode where the trigger is enabled. As the trigger
+             * fires, pending is cleared."
+             *
+             * And: "This bit becomes set when count is decremented
+             * from 1 to 0. It is cleared when the trigger fires,
+             * which will happen just before executing the next
+             * instruction in one of the enabled modes".
+             *
+             * Note that itrigger_set_pending() is a no-op if we're
+             * running debug 0.13.
+             */
+            itrigger_set_pending(env, i, 1);
+
             env->itrigger_enabled = riscv_itrigger_enabled(env);
             do_trigger_action(env, i);
+            itrigger_set_pending(env, i, 0);
         }
     }
 }
-- 
2.43.0

[PATCH 3/5] target/riscv/tcg/debug: adjust 'timing' bit for Debug 1.0

[Daniel Henrique Barboza]

Version 1.0 changed the 'timing' bit.  It is now bit 18.

Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
 target/riscv/tcg/debug.c | 7 ++++++-
 target/riscv/tcg/debug.h | 3 ++-
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c
index 2191928761..8b23c8d045 100644
--- a/target/riscv/tcg/debug.c
+++ b/target/riscv/tcg/debug.c
@@ -584,10 +584,15 @@ static target_ulong type6_mcontrol6_validate(CPURISCVState *env,
     warn_always_zero_bit(ctrl, TYPE6_MATCH, "match");
     warn_always_zero_bit(ctrl, TYPE6_CHAIN, "chain");
     warn_always_zero_bit(ctrl, TYPE6_ACTION, "action");
-    warn_always_zero_bit(ctrl, TYPE6_TIMING, "timing");
     warn_always_zero_bit(ctrl, TYPE6_SELECT, "select");
     warn_always_zero_bit(ctrl, TYPE6_HIT, "hit");
 
+    if (debug_trigger_version_1_0(env)) {
+        warn_always_zero_bit(ctrl, TYPE6_TIMING, "timing");
+    } else {
+        warn_always_zero_bit(ctrl, TYPE6_TIMING_0_13, "timing");
+    }
+
     /* validate size encoding */
     size = extract32(ctrl, 16, 4);
     if (access_size[size] == -1) {
diff --git a/target/riscv/tcg/debug.h b/target/riscv/tcg/debug.h
index a25d099b37..eb635bc277 100644
--- a/target/riscv/tcg/debug.h
+++ b/target/riscv/tcg/debug.h
@@ -98,7 +98,8 @@ typedef enum {
 #define TYPE6_CHAIN     BIT(11)
 #define TYPE6_ACTION    (0xf << 12)
 #define TYPE6_SIZE      (0xf << 16)
-#define TYPE6_TIMING    BIT(20)
+#define TYPE6_TIMING       BIT(18)
+#define TYPE6_TIMING_0_13  BIT(20)
 #define TYPE6_SELECT    BIT(21)
 #define TYPE6_HIT       BIT(22)
 #define TYPE6_VU        BIT(23)
-- 
2.43.0

[PATCH 4/5] target/riscv/tcg/debug: set tinfo version if sdtrig enabled

[Daniel Henrique Barboza]

Set 'version' to 1 if we're running Debug 1.0.

Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
 target/riscv/tcg/debug.c | 11 ++++++++---
 target/riscv/tcg/debug.h |  3 +++
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c
index 8b23c8d045..06573c7b3f 100644
--- a/target/riscv/tcg/debug.c
+++ b/target/riscv/tcg/debug.c
@@ -957,9 +957,14 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
 
 target_ulong tinfo_csr_read(CPURISCVState *env)
 {
-    /* assume all triggers support the same types of triggers */
-    return BIT(TRIGGER_TYPE_AD_MATCH) |
-           BIT(TRIGGER_TYPE_AD_MATCH6);
+    target_ulong val = BIT(TRIGGER_TYPE_AD_MATCH) |
+                       BIT(TRIGGER_TYPE_AD_MATCH6);
+
+    if (debug_trigger_version_1_0(env)) {
+        val = deposit64(val, TINFO_VERSION_OFFSET, TINFO_VERSION_LEN, 1);
+    }
+
+    return val;
 }
 
 void riscv_cpu_debug_excp_handler(CPUState *cs)
diff --git a/target/riscv/tcg/debug.h b/target/riscv/tcg/debug.h
index eb635bc277..fcd92b768c 100644
--- a/target/riscv/tcg/debug.h
+++ b/target/riscv/tcg/debug.h
@@ -45,6 +45,9 @@ typedef enum {
     TRIGGER_TYPE_NUM
 } trigger_type_t;
 
+#define TINFO_VERSION_OFFSET 24
+#define TINFO_VERSION_LEN     8
+
 /* actions */
 typedef enum {
     DBG_ACTION_NONE = -1,           /* sentinel value */
-- 
2.43.0

[PATCH 5/5] docs/specs: add RISC-V CPU Debug support info

[Daniel Henrique Barboza]

Add documentation regarding how QEMU handles Debug versions 0.13 and
1.0.

Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
 docs/specs/index.rst       |  1 +
 docs/specs/riscv-debug.rst | 68 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 69 insertions(+)
 create mode 100644 docs/specs/riscv-debug.rst

diff --git a/docs/specs/index.rst b/docs/specs/index.rst
index b7909a108a..181773515d 100644
--- a/docs/specs/index.rst
+++ b/docs/specs/index.rst
@@ -38,5 +38,6 @@ guest hardware that is specific to QEMU.
    rocker
    riscv-iommu
    riscv-aia
+   riscv-debug
    aspeed-intc
    iommu-testdev
diff --git a/docs/specs/riscv-debug.rst b/docs/specs/riscv-debug.rst
new file mode 100644
index 0000000000..e6dcad7d38
--- /dev/null
+++ b/docs/specs/riscv-debug.rst
@@ -0,0 +1,68 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+.. _riscv-debug:
+
+RISC-V Debug support for RISC-V CPUs
+====================================
+
+Up until QEMU version 11.1 RISC-V CPUs historically supports Debug version
+0.13 via a "debug" flag that is enabled by default in the default rv64
+CPU.
+
+Starting on QEMU 11.2, RISC-V CPUs supports also Debug version 1.0, enabled
+via the "sdtrig" flag like a regular extension.  The default setting for rv64
+is still Debug 0.13 (debug = on, sdtrig = off),
+
+The "sdtrig" flag precedes "debug", i.e. if both are enabled the CPU will
+implement Debug 1.0.  In short:
+
+.. list-table:: "debug" and "sdtrig" flags and enabled Debug version
+   :widths: 25 25 25
+   :header-rows: 1
+
+   * - debug
+     - sdtrig
+     - Enabled Debug version
+   * - on
+     - off
+     - 0.13
+   * - on
+     - on
+     - 1.0
+   * - off
+     - on
+     - 1.0
+   * - off
+     - off
+     - All Debug versions disabled
+
+
+Debug 0.13 to 1.0 code/design changes
+-------------------------------------
+
+The effort done in QEMU version 11.2 to support Debug versions 0.13 and
+1.0 together was based in section 1.2.1.2 "Incompatible Changes from 0.13
+to 1.0" from the ratified `1.0 spec`_.  Here's how the proposed changes in
+that section were implemented in QEMU 11.2:
+
+Changes that aren't applicable due to either being SBI related or not present/supported in QEMU:
+    * "Make haltsum0 optional if there is only one hart."
+    * "System bus autoincrement only happens if an access actually takes place (sbdata0)."
+    * "Require debugger to poll dmactive after lowering it."
+
+Already implemented in the legacy Debug 0.13 base code:
+    * "When a selected trigger is disabled, tdata2 and tdata3 can be written with any value supported by any of the types this trigger supports."
+    * "tcontrol fields only apply to breakpoint traps, not any trap."
+
+All "hitN" fields are hardwired 0 thus no changes made:
+    * "If version is greater than 0, then hit0 (previously called mcontrol6.hit) now contains 0 when a trigger fires more than one instruction after the instruction that matched. (This information is now reflected in hit1.)"
+
+QEMU doesn't support encoding sizes greater than 64 bit so no change made:
+    * "If version is greater than 0, then the encodings of size for sizes greater than 64 bit have changed."
+
+Changes made in the 0.13 codebase to support Debug 1.0:
+    * "Add pending to icount."
+    * "If version is greater than 0, then bit 20 of mcontrol6 is no longer used for timing information. (Previously the bit was called mcontrol6.timing.)"
+
+
+.. _1.0 spec: https://docs.riscv.org/reference/debug/v1.0/_attachments/riscv-debug-specification.pdf
-- 
2.43.0

Re: [PATCH 0/5] target/riscv: support Debug 0.13 and 1.0

[Daniel Henrique Barboza]

Ping


This is the series I talked about in our call last night/earlier today.

The v9 of the riscv-server-ref work was rebased on top of it, along with Chao's
sdext patches.  As soon as we get this queued I think I'll re-send Chao's
work next.


Cheers,
Daniel

On 8/5/2026 3:25 PM, Daniel Henrique Barboza wrote:
> Hi,
> 
> This short series adds support for Debug 0.13 and Debug 1.0.  The
> motivation is simple: we need Debug 1.0 to complete tue upstreaming of
> sdext, which is already fully reviewed and acked for awhile [1], and
> then proceed with the upstreaming of the RISC-V Server Ref board
> (currently on v8: [2]).
> 
> The work is based in section 1.2.1.2 "Incompatible Changes from 0.13 to
> 1.0" of the ratified 1.0 spec [3].  It ended being simpler than
> anticipated because we don't implement most of the registers/bits that
> are backwards incompatible.  I added doc changes to explain the
> rationale used.
> 
> After this series:
> 
> - 'ext_sdtrig' refers to Debug 1.0.  The legacy 'debug' flag refers to
>    Debug 0.13;
> - setting both flags enables Debug 1.0, i.e. 'ext_sdtrig' takes
>    precedence.
> 
> My hope is that this split will make it easier to to move away from
> Debug 0.13 in the future once there's no more demand for it.
> 
> Patches based on master.
> 
> [1] https://lore.kernel.org/qemu-devel/cover.1775959096.git.chao.liu.zevorn@gmail.com/
> [2] https://lore.kernel.org/qemu-devel/20260610214133.1882563-1-daniel.barboza@oss.qualcomm.com/
> [3] https://docs.riscv.org/reference/debug/v1.0/_attachments/riscv-debug-specification.pdf
> 
> Daniel Henrique Barboza (5):
>    target/riscv: split 'debug' and 'sdtrig' flags
>    target/riscv/tcg/debug.c: add Debug 1.0 'pending' bit
>    target/riscv/tcg/debug: adjust 'timing' bit for Debug 1.0
>    target/riscv/tcg/debug: set tinfo version if sdtrig enabled
>    docs/specs: add RISC-V CPU Debug support info
> 
>   docs/specs/index.rst              |  1 +
>   docs/specs/riscv-debug.rst        | 68 +++++++++++++++++++++++++++++++
>   target/riscv/cpu.c                | 21 +++++++---
>   target/riscv/cpu_cfg_fields.h.inc |  1 +
>   target/riscv/machine.c            |  2 +-
>   target/riscv/tcg/csr.c            |  2 +-
>   target/riscv/tcg/debug.c          | 51 +++++++++++++++++++++--
>   target/riscv/tcg/debug.h          |  6 ++-
>   target/riscv/tcg/tcg-cpu.c        |  3 +-
>   9 files changed, 142 insertions(+), 13 deletions(-)
>   create mode 100644 docs/specs/riscv-debug.rst
> 

Re: [PATCH 0/5] target/riscv: support Debug 0.13 and 1.0

[Chao Liu]

Hi Daniel,

On Thu, Aug 20, 2026 at 08:01:39AM +0800, Daniel Henrique Barboza wrote:
> Ping
> 
> 
> This is the series I talked about in our call last night/earlier today.
> 
> The v9 of the riscv-server-ref work was rebased on top of it, along with Chao's
> sdext patches.  As soon as we get this queued I think I'll re-send Chao's
> work next.
Thanks for continuing to drive the sdext work. I don’t have much time to dedicate
to it at the moment, but I’ll do my best to help with the review.

Cheers,
Chao
> 
> 
> Cheers,
> Daniel
> 
> On 8/5/2026 3:25 PM, Daniel Henrique Barboza wrote:
> > Hi,
> > 
> > This short series adds support for Debug 0.13 and Debug 1.0.  The
> > motivation is simple: we need Debug 1.0 to complete tue upstreaming of
> > sdext, which is already fully reviewed and acked for awhile [1], and
> > then proceed with the upstreaming of the RISC-V Server Ref board
> > (currently on v8: [2]).
> > 
> > The work is based in section 1.2.1.2 "Incompatible Changes from 0.13 to
> > 1.0" of the ratified 1.0 spec [3].  It ended being simpler than
> > anticipated because we don't implement most of the registers/bits that
> > are backwards incompatible.  I added doc changes to explain the
> > rationale used.
> > 
> > After this series:
> > 
> > - 'ext_sdtrig' refers to Debug 1.0.  The legacy 'debug' flag refers to
> >    Debug 0.13;
> > - setting both flags enables Debug 1.0, i.e. 'ext_sdtrig' takes
> >    precedence.
> > 
> > My hope is that this split will make it easier to to move away from
> > Debug 0.13 in the future once there's no more demand for it.
> > 
> > Patches based on master.
> > 
> > [1] https://lore.kernel.org/qemu-devel/cover.1775959096.git.chao.liu.zevorn@gmail.com/
> > [2] https://lore.kernel.org/qemu-devel/20260610214133.1882563-1-daniel.barboza@oss.qualcomm.com/
> > [3] https://docs.riscv.org/reference/debug/v1.0/_attachments/riscv-debug-specification.pdf
> > 
> > Daniel Henrique Barboza (5):
> >    target/riscv: split 'debug' and 'sdtrig' flags
> >    target/riscv/tcg/debug.c: add Debug 1.0 'pending' bit
> >    target/riscv/tcg/debug: adjust 'timing' bit for Debug 1.0
> >    target/riscv/tcg/debug: set tinfo version if sdtrig enabled
> >    docs/specs: add RISC-V CPU Debug support info
> > 
> >   docs/specs/index.rst              |  1 +
> >   docs/specs/riscv-debug.rst        | 68 +++++++++++++++++++++++++++++++
> >   target/riscv/cpu.c                | 21 +++++++---
> >   target/riscv/cpu_cfg_fields.h.inc |  1 +
> >   target/riscv/machine.c            |  2 +-
> >   target/riscv/tcg/csr.c            |  2 +-
> >   target/riscv/tcg/debug.c          | 51 +++++++++++++++++++++--
> >   target/riscv/tcg/debug.h          |  6 ++-
> >   target/riscv/tcg/tcg-cpu.c        |  3 +-
> >   9 files changed, 142 insertions(+), 13 deletions(-)
> >   create mode 100644 docs/specs/riscv-debug.rst
> > 
> 

Re: [PATCH 1/5] target/riscv: split 'debug' and 'sdtrig' flags

[Alistair Francis]

On Wed, 2026-08-05 at 15:25 -0300, Daniel Henrique Barboza wrote:
> We need to support modern debug extensions that happens to be
> dependencies of other things that we want to support (e.g. a riscv
> server spec board).  These extensions, namely sdext, depends on Debug
> 1.0.  At this moment we support Debug 0.13, and so it happens that
> 0.13
> and 1.0 aren't backwards compatible, i.e. we need design changes to
> support both.
> 
> The easier way is to deprecate the Debug 0.13 support, together with
> its
> legacy 'debug' flag and call it a day.  But there's a demand to keep
> the
> 0.13 support around and this idea got scrapped.
> 
> We're going to support both 0.13 and 1.0, where the 'debug' flag will
> refer to 0.13 and 'sdtrig' to 1.0.  We need to split both in distinct
> flags first to handle the backend changes, so:
> 
> - add a new cpu->cfg.ext_sdtrig flag;
> - all code that checks "if debug enabled" now checks for both debug
> and
>   ext_sdtrig;
> - amend riscv_isa_string_ext() to keep adding 'sdtrig' in riscv,isa
> if
>   we have just the 'debug' flag enabled.
> 
> Signed-off-by: Daniel Henrique Barboza
> <daniel.barboza@oss.qualcomm.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c                | 21 ++++++++++++++++-----
>  target/riscv/cpu_cfg_fields.h.inc |  1 +
>  target/riscv/machine.c            |  2 +-
>  target/riscv/tcg/csr.c            |  2 +-
>  target/riscv/tcg/tcg-cpu.c        |  3 ++-
>  5 files changed, 21 insertions(+), 8 deletions(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 5a82e6563b..db4f2b6459 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -247,7 +247,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
>      ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
>      ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
> -    ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, debug),
> +    ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, ext_sdtrig),
>      ISA_INTERNAL_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0,
>                                  has_priv_1_12),
>      ISA_INTERNAL_EXT_DATA_ENTRY(sha, PRIV_VERSION_1_12_0, ext_sha),
> @@ -1079,7 +1079,7 @@ static void riscv_cpu_reset_hold(Object *obj,
> ResetType type)
>  
>  #ifndef CONFIG_USER_ONLY
>  #ifdef CONFIG_TCG
> -    if (cpu->cfg.debug) {
> +    if (cpu->cfg.debug || cpu->cfg.ext_sdtrig) {
>          riscv_trigger_reset_hold(env);
>      }
>  #endif
> @@ -1241,7 +1241,7 @@ static void riscv_cpu_realize(DeviceState *dev,
> Error **errp)
>      riscv_cpu_register_gdb_regs_for_features(cs);
>  
>  #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
> -    if (cpu->cfg.debug) {
> +    if (cpu->cfg.debug || cpu->cfg.ext_sdtrig) {
>          riscv_trigger_realize(&cpu->env);
>      }
>  #endif
> @@ -1258,7 +1258,7 @@ static void riscv_cpu_unrealize(DeviceState
> *dev)
>  #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
>      RISCVCPU *cpu = RISCV_CPU(dev);
>  
> -    if (cpu->cfg.debug) {
> +    if (cpu->cfg.debug || cpu->cfg.ext_sdtrig) {
>          riscv_trigger_unrealize(&cpu->env);
>      }
>  #endif
> @@ -2834,6 +2834,11 @@ RISCVCPUImpliedExtsRule
> *riscv_multi_ext_implied_rules[] = {
>  };
>  
>  static const Property riscv_cpu_properties[] = {
> +    /*
> +     * The 'debug' flag enables support for the legacy Debug
> +     * 0.13 spec.  In case cpu->ext.ext_sdtrig is also enabled
> +     * the CPU will enable Debug 1.0 instead.
> +     */
>      DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
>      DEFINE_PROP_BOOL("big-endian", RISCVCPU, cfg.big_endian, false),
>  
> @@ -3055,7 +3060,13 @@ static void riscv_isa_string_ext(RISCVCPU
> *cpu, char **isa_str,
>      char *new = *isa_str;
>  
>      for (edata = isa_edata_arr; edata && edata->name; edata++) {
> -        if (isa_ext_is_enabled(cpu, edata->ext_enable_offset)) {
> +        if (isa_ext_is_enabled(cpu, edata->ext_enable_offset)
> +            /*
> +             * We've been adding 'sdtrig' in riscv,isa for
> +             * Debug 0.13 for awhile.  Until we decide to
> +             * move away from it we'll keep doing it.
> +             */
> +            || (!g_strcmp0(edata->name, "sdtrig") && cpu-
> >cfg.debug)) {
>              new = g_strconcat(old, "_", edata->name, NULL);
>              g_free(old);
>              old = new;
> diff --git a/target/riscv/cpu_cfg_fields.h.inc
> b/target/riscv/cpu_cfg_fields.h.inc
> index 9eb47af0a7..e32af40c90 100644
> --- a/target/riscv/cpu_cfg_fields.h.inc
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -105,6 +105,7 @@ BOOL_FIELD(ext_zvfbfmin)
>  BOOL_FIELD(ext_zvfbfwma)
>  BOOL_FIELD(ext_zvfh)
>  BOOL_FIELD(ext_zvfhmin)
> +BOOL_FIELD(ext_sdtrig)
>  BOOL_FIELD(ext_smaia)
>  BOOL_FIELD(ext_ssaia)
>  BOOL_FIELD(ext_smctr)
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 0ab613a298..a744462d48 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -228,7 +228,7 @@ static bool debug_needed(void *opaque)
>  {
>      RISCVCPU *cpu = opaque;
>  
> -    return cpu->cfg.debug;
> +    return cpu->cfg.debug || cpu->cfg.ext_sdtrig;
>  }
>  
>  static int debug_post_load(void *opaque, int version_id)
> diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
> index 36f2004bc5..850fbf32fc 100644
> --- a/target/riscv/tcg/csr.c
> +++ b/target/riscv/tcg/csr.c
> @@ -804,7 +804,7 @@ static RISCVException have_mseccfg(CPURISCVState
> *env, int csrno)
>  
>  static RISCVException debug(CPURISCVState *env, int csrno)
>  {
> -    if (riscv_cpu_cfg(env)->debug) {
> +    if (riscv_cpu_cfg(env)->debug || riscv_cpu_cfg(env)->ext_sdtrig)
> {
>          return RISCV_EXCP_NONE;
>      }
>  
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 4af5cd9c73..02bbdaef8e 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -182,7 +182,8 @@ static TCGTBCPUState
> riscv_get_tb_cpu_state(CPUState *cs)
>               ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED;
>      }
>  
> -    if (cpu->cfg.debug && !icount_enabled()) {
> +    if ((cpu->cfg.debug || cpu->cfg.ext_sdtrig)
> +        && !icount_enabled()) {
>          flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env-
> >itrigger_enabled);
>      }
>  #endif

Re: [PATCH 2/5] target/riscv/tcg/debug.c: add Debug 1.0 'pending' bit

[Alistair Francis]

On Wed, 2026-08-05 at 15:25 -0300, Daniel Henrique Barboza wrote:
> We need to set the 'pending' bit when 'count' reaches 0, clearing it
> right
> after the trigger fires.
> 
> This is 1.0 exclusive behavior so no changes are needed when running
> Debug
> 0.13.
> 
> Signed-off-by: Daniel Henrique Barboza
> <daniel.barboza@oss.qualcomm.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/tcg/debug.c | 33 +++++++++++++++++++++++++++++++++
>  1 file changed, 33 insertions(+)
> 
> diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c
> index 3c0fe70101..2191928761 100644
> --- a/target/riscv/tcg/debug.c
> +++ b/target/riscv/tcg/debug.c
> @@ -77,6 +77,11 @@ static int access_size[SIZE_NUM] = {
>      [6 ... 15] = -1,
>  };
>  
> +static bool debug_trigger_version_1_0(CPURISCVState *env)
> +{
> +    return riscv_cpu_cfg(env)->ext_sdtrig;
> +}
> +
>  static inline target_ulong extract_trigger_type(CPURISCVState *env,
>                                                  target_ulong tdata1)
>  {
> @@ -684,6 +689,17 @@ itrigger_set_count(CPURISCVState *env, int
> index, int value)
>                                     ITRIGGER_COUNT, value);
>  }
>  
> +static inline void
> +itrigger_set_pending(CPURISCVState *env, int index, int val)
> +{
> +    if (!debug_trigger_version_1_0(env)) {
> +        return;
> +    }
> +
> +    env->tdata1[index] = set_field(env->tdata1[index],
> +                                   ITRIGGER_PENDING, val);
> +}
> +
>  static bool check_itrigger_priv(CPURISCVState *env, int index)
>  {
>      target_ulong tdata1 = env->tdata1[index];
> @@ -735,8 +751,25 @@ void helper_itrigger_match(CPURISCVState *env)
>          }
>          itrigger_set_count(env, i, count--);
>          if (!count) {
> +            /*
> +             * From the 1.0 spec: "When pending is set, the trigger
> +             * fires just before any further instructions are
> executed
> +             * in a mode where the trigger is enabled. As the
> trigger
> +             * fires, pending is cleared."
> +             *
> +             * And: "This bit becomes set when count is decremented
> +             * from 1 to 0. It is cleared when the trigger fires,
> +             * which will happen just before executing the next
> +             * instruction in one of the enabled modes".
> +             *
> +             * Note that itrigger_set_pending() is a no-op if we're
> +             * running debug 0.13.
> +             */
> +            itrigger_set_pending(env, i, 1);
> +
>              env->itrigger_enabled = riscv_itrigger_enabled(env);
>              do_trigger_action(env, i);
> +            itrigger_set_pending(env, i, 0);
>          }
>      }
>  }

Re: [PATCH 3/5] target/riscv/tcg/debug: adjust 'timing' bit for Debug 1.0

[Alistair Francis]

On Wed, 2026-08-05 at 15:25 -0300, Daniel Henrique Barboza wrote:
> Version 1.0 changed the 'timing' bit.  It is now bit 18.
> 
> Signed-off-by: Daniel Henrique Barboza
> <daniel.barboza@oss.qualcomm.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/tcg/debug.c | 7 ++++++-
>  target/riscv/tcg/debug.h | 3 ++-
>  2 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c
> index 2191928761..8b23c8d045 100644
> --- a/target/riscv/tcg/debug.c
> +++ b/target/riscv/tcg/debug.c
> @@ -584,10 +584,15 @@ static target_ulong
> type6_mcontrol6_validate(CPURISCVState *env,
>      warn_always_zero_bit(ctrl, TYPE6_MATCH, "match");
>      warn_always_zero_bit(ctrl, TYPE6_CHAIN, "chain");
>      warn_always_zero_bit(ctrl, TYPE6_ACTION, "action");
> -    warn_always_zero_bit(ctrl, TYPE6_TIMING, "timing");
>      warn_always_zero_bit(ctrl, TYPE6_SELECT, "select");
>      warn_always_zero_bit(ctrl, TYPE6_HIT, "hit");
>  
> +    if (debug_trigger_version_1_0(env)) {
> +        warn_always_zero_bit(ctrl, TYPE6_TIMING, "timing");
> +    } else {
> +        warn_always_zero_bit(ctrl, TYPE6_TIMING_0_13, "timing");
> +    }
> +
>      /* validate size encoding */
>      size = extract32(ctrl, 16, 4);
>      if (access_size[size] == -1) {
> diff --git a/target/riscv/tcg/debug.h b/target/riscv/tcg/debug.h
> index a25d099b37..eb635bc277 100644
> --- a/target/riscv/tcg/debug.h
> +++ b/target/riscv/tcg/debug.h
> @@ -98,7 +98,8 @@ typedef enum {
>  #define TYPE6_CHAIN     BIT(11)
>  #define TYPE6_ACTION    (0xf << 12)
>  #define TYPE6_SIZE      (0xf << 16)
> -#define TYPE6_TIMING    BIT(20)
> +#define TYPE6_TIMING       BIT(18)
> +#define TYPE6_TIMING_0_13  BIT(20)
>  #define TYPE6_SELECT    BIT(21)
>  #define TYPE6_HIT       BIT(22)
>  #define TYPE6_VU        BIT(23)

Re: [PATCH 4/5] target/riscv/tcg/debug: set tinfo version if sdtrig enabled

[Alistair Francis]

On Wed, 2026-08-05 at 15:25 -0300, Daniel Henrique Barboza wrote:
> Set 'version' to 1 if we're running Debug 1.0.
> 
> Signed-off-by: Daniel Henrique Barboza
> <daniel.barboza@oss.qualcomm.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/tcg/debug.c | 11 ++++++++---
>  target/riscv/tcg/debug.h |  3 +++
>  2 files changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c
> index 8b23c8d045..06573c7b3f 100644
> --- a/target/riscv/tcg/debug.c
> +++ b/target/riscv/tcg/debug.c
> @@ -957,9 +957,14 @@ void tdata_csr_write(CPURISCVState *env, int
> tdata_index, target_ulong val)
>  
>  target_ulong tinfo_csr_read(CPURISCVState *env)
>  {
> -    /* assume all triggers support the same types of triggers */
> -    return BIT(TRIGGER_TYPE_AD_MATCH) |
> -           BIT(TRIGGER_TYPE_AD_MATCH6);
> +    target_ulong val = BIT(TRIGGER_TYPE_AD_MATCH) |
> +                       BIT(TRIGGER_TYPE_AD_MATCH6);
> +
> +    if (debug_trigger_version_1_0(env)) {
> +        val = deposit64(val, TINFO_VERSION_OFFSET,
> TINFO_VERSION_LEN, 1);
> +    }
> +
> +    return val;
>  }
>  
>  void riscv_cpu_debug_excp_handler(CPUState *cs)
> diff --git a/target/riscv/tcg/debug.h b/target/riscv/tcg/debug.h
> index eb635bc277..fcd92b768c 100644
> --- a/target/riscv/tcg/debug.h
> +++ b/target/riscv/tcg/debug.h
> @@ -45,6 +45,9 @@ typedef enum {
>      TRIGGER_TYPE_NUM
>  } trigger_type_t;
>  
> +#define TINFO_VERSION_OFFSET 24
> +#define TINFO_VERSION_LEN     8
> +
>  /* actions */
>  typedef enum {
>      DBG_ACTION_NONE = -1,           /* sentinel value */

Re: [PATCH 5/5] docs/specs: add RISC-V CPU Debug support info

[Alistair Francis]

On Wed, 2026-08-05 at 15:25 -0300, Daniel Henrique Barboza wrote:
> Add documentation regarding how QEMU handles Debug versions 0.13 and
> 1.0.
> 
> Signed-off-by: Daniel Henrique Barboza
> <daniel.barboza@oss.qualcomm.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  docs/specs/index.rst       |  1 +
>  docs/specs/riscv-debug.rst | 68
> ++++++++++++++++++++++++++++++++++++++
>  2 files changed, 69 insertions(+)
>  create mode 100644 docs/specs/riscv-debug.rst
> 
> diff --git a/docs/specs/index.rst b/docs/specs/index.rst
> index b7909a108a..181773515d 100644
> --- a/docs/specs/index.rst
> +++ b/docs/specs/index.rst
> @@ -38,5 +38,6 @@ guest hardware that is specific to QEMU.
>     rocker
>     riscv-iommu
>     riscv-aia
> +   riscv-debug
>     aspeed-intc
>     iommu-testdev
> diff --git a/docs/specs/riscv-debug.rst b/docs/specs/riscv-debug.rst
> new file mode 100644
> index 0000000000..e6dcad7d38
> --- /dev/null
> +++ b/docs/specs/riscv-debug.rst
> @@ -0,0 +1,68 @@
> +.. SPDX-License-Identifier: GPL-2.0-or-later
> +
> +.. _riscv-debug:
> +
> +RISC-V Debug support for RISC-V CPUs
> +====================================
> +
> +Up until QEMU version 11.1 RISC-V CPUs historically supports Debug
> version
> +0.13 via a "debug" flag that is enabled by default in the default
> rv64
> +CPU.
> +
> +Starting on QEMU 11.2, RISC-V CPUs supports also Debug version 1.0,
> enabled
> +via the "sdtrig" flag like a regular extension.  The default setting
> for rv64
> +is still Debug 0.13 (debug = on, sdtrig = off),
> +
> +The "sdtrig" flag precedes "debug", i.e. if both are enabled the CPU
> will
> +implement Debug 1.0.  In short:
> +
> +.. list-table:: "debug" and "sdtrig" flags and enabled Debug version
> +   :widths: 25 25 25
> +   :header-rows: 1
> +
> +   * - debug
> +     - sdtrig
> +     - Enabled Debug version
> +   * - on
> +     - off
> +     - 0.13
> +   * - on
> +     - on
> +     - 1.0
> +   * - off
> +     - on
> +     - 1.0
> +   * - off
> +     - off
> +     - All Debug versions disabled
> +
> +
> +Debug 0.13 to 1.0 code/design changes
> +-------------------------------------
> +
> +The effort done in QEMU version 11.2 to support Debug versions 0.13
> and
> +1.0 together was based in section 1.2.1.2 "Incompatible Changes from
> 0.13
> +to 1.0" from the ratified `1.0 spec`_.  Here's how the proposed
> changes in
> +that section were implemented in QEMU 11.2:
> +
> +Changes that aren't applicable due to either being SBI related or
> not present/supported in QEMU:
> +    * "Make haltsum0 optional if there is only one hart."
> +    * "System bus autoincrement only happens if an access actually
> takes place (sbdata0)."
> +    * "Require debugger to poll dmactive after lowering it."
> +
> +Already implemented in the legacy Debug 0.13 base code:
> +    * "When a selected trigger is disabled, tdata2 and tdata3 can be
> written with any value supported by any of the types this trigger
> supports."
> +    * "tcontrol fields only apply to breakpoint traps, not any
> trap."
> +
> +All "hitN" fields are hardwired 0 thus no changes made:
> +    * "If version is greater than 0, then hit0 (previously called
> mcontrol6.hit) now contains 0 when a trigger fires more than one
> instruction after the instruction that matched. (This information is
> now reflected in hit1.)"
> +
> +QEMU doesn't support encoding sizes greater than 64 bit so no change
> made:
> +    * "If version is greater than 0, then the encodings of size for
> sizes greater than 64 bit have changed."
> +
> +Changes made in the 0.13 codebase to support Debug 1.0:
> +    * "Add pending to icount."
> +    * "If version is greater than 0, then bit 20 of mcontrol6 is no
> longer used for timing information. (Previously the bit was called
> mcontrol6.timing.)"
> +
> +
> +.. _1.0 spec:
> https://docs.riscv.org/reference/debug/v1.0/_attachments/riscv-debug-specification.pdf

Re: [PATCH 0/5] target/riscv: support Debug 0.13 and 1.0

[Alistair Francis]

On Wed, 2026-08-05 at 15:25 -0300, Daniel Henrique Barboza wrote:
> Hi,
> 
> This short series adds support for Debug 0.13 and Debug 1.0.  The
> motivation is simple: we need Debug 1.0 to complete tue upstreaming
> of
> sdext, which is already fully reviewed and acked for awhile [1], and
> then proceed with the upstreaming of the RISC-V Server Ref board
> (currently on v8: [2]).
> 
> The work is based in section 1.2.1.2 "Incompatible Changes from 0.13
> to
> 1.0" of the ratified 1.0 spec [3].  It ended being simpler than
> anticipated because we don't implement most of the registers/bits
> that
> are backwards incompatible.  I added doc changes to explain the
> rationale used.
> 
> After this series:
> 
> - 'ext_sdtrig' refers to Debug 1.0.  The legacy 'debug' flag refers
> to
>   Debug 0.13;
> - setting both flags enables Debug 1.0, i.e. 'ext_sdtrig' takes
>   precedence.
> 
> My hope is that this split will make it easier to to move away from
> Debug 0.13 in the future once there's no more demand for it.
> 
> Patches based on master.
> 
> [1]
> https://lore.kernel.org/qemu-devel/cover.1775959096.git.chao.liu.zevorn@gmail.com/
> [2]
> https://lore.kernel.org/qemu-devel/20260610214133.1882563-1-daniel.barboza@oss.qualcomm.com/
> [3]
> https://docs.riscv.org/reference/debug/v1.0/_attachments/riscv-debug-specification.pdf
> 
> Daniel Henrique Barboza (5):
>   target/riscv: split 'debug' and 'sdtrig' flags
>   target/riscv/tcg/debug.c: add Debug 1.0 'pending' bit
>   target/riscv/tcg/debug: adjust 'timing' bit for Debug 1.0
>   target/riscv/tcg/debug: set tinfo version if sdtrig enabled
>   docs/specs: add RISC-V CPU Debug support info

Thanks!

Applied to riscv-to-apply.next

Alistair

> 
>  docs/specs/index.rst              |  1 +
>  docs/specs/riscv-debug.rst        | 68
> +++++++++++++++++++++++++++++++
>  target/riscv/cpu.c                | 21 +++++++---
>  target/riscv/cpu_cfg_fields.h.inc |  1 +
>  target/riscv/machine.c            |  2 +-
>  target/riscv/tcg/csr.c            |  2 +-
>  target/riscv/tcg/debug.c          | 51 +++++++++++++++++++++--
>  target/riscv/tcg/debug.h          |  6 ++-
>  target/riscv/tcg/tcg-cpu.c        |  3 +-
>  9 files changed, 142 insertions(+), 13 deletions(-)
>  create mode 100644 docs/specs/riscv-debug.rst