From: Mostafa Saleh <smostafa@google.com>
To: Tao Tang <tangtao1634@phytium.com.cn>
Cc: "Eric Auger" <eric.auger@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
"Chen Baozi" <chenbaozi@phytium.com.cn>,
"Pierrick Bouvier" <pierrick.bouvier@oss.qualcomm.com>,
"Philippe Mathieu-Daudé" <philmd@mailo.com>,
"Chao Liu" <chao.liu@processmission.com>,
"Jim MacArthur" <jim.macarthur@linaro.org>
Subject: Re: [RFC v5 20/28] hw/arm/smmuv3: Route IRQ and GERROR handling by SEC_SID
Date: Tue, 1 Sep 2026 14:33:22 +0000 [thread overview]
Message-ID: <apbiMt6x_PUrhluf@google.com> (raw)
In-Reply-To: <20260813162558.2808607-5-tangtao1634@phytium.com.cn>
On Fri, Aug 14, 2026 at 12:25:58AM +0800, Tao Tang wrote:
> Interrupt and global error handling currently always selects the
> Non-secure register bank, even when the event or command originates
> from the Secure programming interface. This splits CMDQ_CONS.ERR from
> GERROR.CMDQ_ERR and prevents Secure software from acknowledging the
> error through S_GERRORN.
>
> Pass SEC_SID through the IRQ and GERROR helpers and all queue call
> sites so interrupt enable checks, global error reporting, and
> acknowledgement use the originating programming-interface bank.
>
> Signed-off-by: Tao Tang <tangtao1634@phytium.com.cn>
> ---
> hw/arm/smmuv3.c | 20 +++++++++++---------
> 1 file changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
> index b36bc4a54e0..d69fc0898af 100644
> --- a/hw/arm/smmuv3.c
> +++ b/hw/arm/smmuv3.c
> @@ -49,11 +49,11 @@
> *
> * @irq: irq type
> * @gerror_mask: mask of gerrors to toggle (relevant if @irq is GERROR)
> + * @sec_sid: security state of the programming interface
> */
> static void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq,
> - uint32_t gerror_mask)
> + uint32_t gerror_mask, SMMUSecSID sec_sid)
> {
> - SMMUSecSID sec_sid = SMMU_SEC_SID_NS;
> SMMUv3RegBank *bank = smmuv3_bank(s, sec_sid);
>
> bool pulse = false;
> @@ -90,9 +90,9 @@ static void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq,
> }
> }
>
> -static void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t new_gerrorn)
> +static void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t new_gerrorn,
> + SMMUSecSID sec_sid)
> {
> - SMMUSecSID sec_sid = SMMU_SEC_SID_NS;
> SMMUv3RegBank *bank = smmuv3_bank(s, sec_sid);
> uint32_t pending = bank->gerror ^ bank->gerrorn;
> uint32_t toggled = bank->gerrorn ^ new_gerrorn;
> @@ -173,7 +173,7 @@ static MemTxResult smmuv3_write_eventq(SMMUv3State *s, SMMUSecSID sec_sid,
> }
>
> if (!smmuv3_q_empty(q)) {
> - smmuv3_trigger_irq(s, SMMU_IRQ_EVTQ, 0);
> + smmuv3_trigger_irq(s, SMMU_IRQ_EVTQ, 0, sec_sid);
> }
> return MEMTX_OK;
> }
> @@ -187,7 +187,8 @@ void smmuv3_propagate_event(SMMUv3State *s, Evt *evt, SMMUSecSID sec_sid)
> QEMU_LOCK_GUARD(&s->mutex);
> r = smmuv3_write_eventq(s, sec_sid, evt);
> if (r != MEMTX_OK) {
> - smmuv3_trigger_irq(s, SMMU_IRQ_GERROR, R_GERROR_EVENTQ_ABT_ERR_MASK);
> + smmuv3_trigger_irq(s, SMMU_IRQ_GERROR,
> + R_GERROR_EVENTQ_ABT_ERR_MASK, sec_sid);
> }
> }
>
> @@ -1645,7 +1646,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error **errp, SMMUSecSID sec_sid)
> switch (type) {
> case SMMU_CMD_SYNC:
> if (CMD_SYNC_CS(&cmd) & CMD_SYNC_SIG_IRQ) {
> - smmuv3_trigger_irq(s, SMMU_IRQ_CMD_SYNC, 0);
> + smmuv3_trigger_irq(s, SMMU_IRQ_CMD_SYNC, 0, sec_sid);
> }
> break;
> case SMMU_CMD_PREFETCH_CONFIG:
> @@ -1879,7 +1880,8 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error **errp, SMMUSecSID sec_sid)
> if (cmd_error) {
> trace_smmuv3_cmdq_consume_error(smmu_cmd_string(type), cmd_error);
> smmu_write_cmdq_err(s, cmd_error, sec_sid);
> - smmuv3_trigger_irq(s, SMMU_IRQ_GERROR, R_GERROR_CMDQ_ERR_MASK);
> + smmuv3_trigger_irq(s, SMMU_IRQ_GERROR,
> + R_GERROR_CMDQ_ERR_MASK, sec_sid);
Won't we need a new line for the secure smmu instead of sharing
the same one in this function "qemu_irq_pulse(s->irq[irq])"?
The spec says:
The SMMU has the following interrupt sources. Depending on the
implementation, each interrupt source asserts a wired interrupt
output that is unique to the source, or sends an MSI, or both.
- Event queue
- Secure Event queue
The way I read it, they have to be different.
Thanks,
Mostafa
> }
>
> trace_smmuv3_cmdq_consume_out(Q_PROD(q), Q_CONS(q),
> @@ -1996,7 +1998,7 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset,
> bank->irq_ctrl = data;
> break;
> case A_GERRORN:
> - smmuv3_write_gerrorn(s, data);
> + smmuv3_write_gerrorn(s, data, reg_sec_sid);
> /*
> * By acknowledging the CMDQ_ERR, SW may notify cmds can
> * be processed again
> --
> 2.34.1
>
next prev parent reply other threads:[~2026-09-01 14:34 UTC|newest]
Thread overview: 94+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-13 16:15 [RFC v5 00/28] hw/arm/smmuv3: Support Secure state for SMMUv3 Tao Tang
2026-08-13 16:21 ` [RFC v5 23/28] hw/pci: Add sec-sid property to PCIDevice Tao Tang
2026-08-25 12:20 ` Jim MacArthur
2026-08-31 6:03 ` Eric Auger
2026-08-13 16:24 ` [RFC v5 01/28] hw/arm/smmuv3: Introduce secure registers Tao Tang
2026-08-18 14:21 ` Jim MacArthur
2026-08-13 16:24 ` [RFC v5 02/28] hw/arm/smmuv3: Introduce banked registers for SMMUv3 state Tao Tang
2026-08-21 9:52 ` Jim MacArthur
2026-08-21 16:03 ` Tao Tang
2026-08-13 16:24 ` [RFC v5 03/28] hw/arm/smmuv3: Thread SEC_SID through helper APIs Tao Tang
2026-08-21 10:09 ` Jim MacArthur
2026-09-01 13:48 ` Mostafa Saleh
2026-08-13 16:24 ` [RFC v5 04/28] hw/arm/smmuv3: Track SEC_SID in configs and events Tao Tang
2026-08-21 12:35 ` Jim MacArthur
2026-09-01 13:49 ` Mostafa Saleh
2026-08-13 16:24 ` [RFC v5 05/28] hw/arm/smmu-common: Add security-aware address space selector Tao Tang
2026-08-20 22:17 ` Pierrick Bouvier
2026-08-27 8:20 ` Eric Auger
2026-09-01 13:50 ` Mostafa Saleh
2026-08-13 16:24 ` [RFC v5 06/28] hw/arm/smmuv3: Plumb transaction attributes into config helpers Tao Tang
2026-08-20 22:19 ` Pierrick Bouvier
2026-08-27 9:07 ` Eric Auger
2026-09-01 13:58 ` Mostafa Saleh
2026-08-13 16:24 ` [RFC v5 07/28] hw/arm/smmuv3: Reject secure STEs with stage-2 enabled Tao Tang
2026-08-20 22:19 ` Pierrick Bouvier
2026-08-27 12:09 ` Eric Auger
2026-09-01 14:01 ` Mostafa Saleh
2026-08-13 16:24 ` [RFC v5 08/28] hw/arm/smmu-common: Key configuration cache on SMMUDevice and SEC_SID Tao Tang
2026-08-21 15:01 ` Jim MacArthur
2026-09-01 14:06 ` Mostafa Saleh
2026-08-13 16:24 ` [RFC v5 09/28] hw/arm/smmu: Add PTE NS/NSTable helpers Tao Tang
2026-08-21 15:14 ` Jim MacArthur
2026-08-27 12:25 ` Eric Auger
2026-09-01 14:05 ` Mostafa Saleh
2026-08-13 16:24 ` [RFC v5 10/28] hw/arm/smmuv3: Store CD NSCFG in TT info Tao Tang
2026-08-21 15:16 ` Jim MacArthur
2026-09-01 14:07 ` Mostafa Saleh
2026-08-13 16:25 ` [RFC v5 11/28] hw/arm/smmu-common: Implement secure state handling in ptw Tao Tang
2026-08-20 22:26 ` Pierrick Bouvier
2026-08-27 15:13 ` Eric Auger
2026-09-01 14:09 ` Mostafa Saleh
2026-08-13 16:25 ` [RFC v5 12/28] hw/arm/smmuv3: Tag IOTLB cache keys with SEC_SID Tao Tang
2026-08-20 22:21 ` Pierrick Bouvier
2026-08-27 16:56 ` Eric Auger
2026-09-01 14:11 ` Mostafa Saleh
2026-08-13 16:25 ` [RFC v5 13/28] hw/arm/smmuv3: Pass sec_sid into cmdq consume path Tao Tang
2026-08-21 15:57 ` Jim MacArthur
2026-09-01 14:14 ` Mostafa Saleh
2026-08-13 16:25 ` [RFC v5 14/28] hw/arm/smmuv3: Make evtq producer use SEC_SID Tao Tang
2026-08-21 15:58 ` Jim MacArthur
2026-09-01 14:15 ` Mostafa Saleh
2026-08-13 16:25 ` [RFC v5 15/28] hw/arm/smmu: Make CMDQ invalidation security-state aware Tao Tang
2026-08-20 22:29 ` Pierrick Bouvier
2026-08-21 16:00 ` Tao Tang
2026-08-28 8:43 ` Eric Auger
2026-08-28 8:54 ` Eric Auger
2026-08-13 16:25 ` [RFC v5 16/28] hw/arm/smmuv3: Add access checks for GERROR_IRQ_CFG registers Tao Tang
2026-08-28 9:47 ` Eric Auger
2026-09-01 14:18 ` Mostafa Saleh
2026-08-13 16:25 ` [RFC v5 17/28] hw/arm/smmuv3: Add access checks for STRTAB_BASE and CR2 registers Tao Tang
2026-08-28 10:05 ` Eric Auger
2026-09-01 14:22 ` Mostafa Saleh
2026-08-13 16:25 ` [RFC v5 18/28] hw/arm/smmuv3: Add access checks for CMDQ and EVENTQ registers Tao Tang
2026-08-28 10:09 ` Eric Auger
2026-08-13 16:25 ` [RFC v5 19/28] hw/arm/smmuv3: Determine register bank from MMIO offset Tao Tang
2026-08-25 11:17 ` Jim MacArthur
2026-08-28 10:26 ` Eric Auger
2026-09-01 14:26 ` Mostafa Saleh
2026-08-13 16:25 ` [RFC v5 20/28] hw/arm/smmuv3: Route IRQ and GERROR handling by SEC_SID Tao Tang
2026-08-20 22:23 ` Pierrick Bouvier
2026-08-31 4:48 ` Eric Auger
2026-09-01 14:33 ` Mostafa Saleh [this message]
2026-08-13 16:26 ` [RFC v5 21/28] hw/arm/smmuv3: Implement SMMU_S_INIT register Tao Tang
2026-08-25 12:06 ` Jim MacArthur
2026-08-31 5:23 ` Eric Auger
2026-08-13 16:26 ` [RFC v5 22/28] hw/arm/smmuv3: Harden security checks in MMIO handlers Tao Tang
2026-08-25 12:18 ` Jim MacArthur
2026-08-31 5:56 ` Eric Auger
2026-08-13 16:26 ` [RFC v5 24/28] hw/arm/smmuv3: Select sec-sid from PCI property and validate SECURE_IMPL Tao Tang
2026-08-31 8:22 ` Eric Auger
2026-08-13 16:26 ` [RFC v5 25/28] hw/arm/smmuv3: Reject IOMMU notifiers for non-NS devices Tao Tang
2026-08-20 22:23 ` Pierrick Bouvier
2026-08-31 8:24 ` Eric Auger
2026-08-13 16:26 ` [RFC v5 26/28] hw/arm/smmuv3: Initialize the secure register bank Tao Tang
2026-08-25 13:39 ` Jim MacArthur
2026-08-31 8:37 ` Eric Auger
2026-08-13 16:26 ` [RFC v5 27/28] hw/arm/smmuv3: Add secure bank migration and secure-impl property Tao Tang
2026-08-25 13:50 ` Jim MacArthur
2026-08-31 8:51 ` Eric Auger
2026-08-13 16:26 ` [RFC v5 28/28] [NOT-MERGE] hw/arm/smmuv3: temporarily enable SEL2 bit and some other features Tao Tang
2026-08-31 8:54 ` Eric Auger
2026-08-20 22:16 ` [RFC v5 00/28] hw/arm/smmuv3: Support Secure state for SMMUv3 Pierrick Bouvier
2026-08-21 16:15 ` Tao Tang
2026-09-01 14:47 ` Mostafa Saleh
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