From: Zhao Liu <zhao1.liu@intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: qemu-devel@nongnu.org, Zhao Liu <zhao1.liu@intel.com>
Subject: Re: [PATCH 20/20] target/i386/tcg: optimize CCMP
Date: Wed, 2 Sep 2026 17:29:06 +0800 [thread overview]
Message-ID: <apfsYkfCVJAsOD5p@intel.com> (raw)
In-Reply-To: <20260825122921.431739-21-pbonzini@redhat.com>
On Tue, Aug 25, 2026 at 02:29:21PM +0200, Paolo Bonzini wrote:
> Date: Tue, 25 Aug 2026 14:29:21 +0200
> From: Paolo Bonzini <pbonzini@redhat.com>
> Subject: [PATCH 20/20] target/i386/tcg: optimize CCMP
> X-Mailer: git-send-email 2.55.0
>
> If possible, modify conditionally the input arguments to generate the
> flags requested by dfv; this way CCMP can use CC_OP_SUB* instead of having
> to compute the carry-out vector by hand. This happens relatively often
> for dfv=0, and also for dfv=sf for code produced by clang.
>
> Of the combinations that cannot be optimized, both GCC and clang generate
> dfv=zf. GCC also generates OS and OSZ.
>
> Do not bother doing this for CTEST; the savings are modest because it
> does not need complex code to compute the carry-out vector (CC_SRC
> is always 0). In addition, trivially replacing the arguments to the AND
> would only support dfv=0 (produced by -2 & 2) or dfv=S (produced by -2 &
> -2), because TEST cannot produce any value where CF or OF are not zero.
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> target/i386/tcg/emit.c.inc | 56 ++++++++++++++++++++++++++++++++++----
> 1 file changed, 51 insertions(+), 5 deletions(-)
>
> diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
> index 1144953abb1..7641b2fc104 100644
> --- a/target/i386/tcg/emit.c.inc
> +++ b/target/i386/tcg/emit.c.inc
> @@ -1749,6 +1749,53 @@ static void gen_dfv_movcond(DisasContext *s, X86DecodedInsn *decode, int cond, u
> decode->cc_dst, tcg_constant_tl(dst));
> }
>
> +static bool gen_ccmp_movcond(DisasContext *s, int cond, uint32_t dfv, MemOp ot)
> +{
> + target_ulong op0, op1, max_int;
> + if (cond == CCMP_T) {
> + return true;
> + }
should we return false for CCMP_F? Or...
> +}
> +
> static void gen_SUB(DisasContext *s, X86DecodedInsn *decode);
> static void gen_CMP(DisasContext *s, X86DecodedInsn *decode)
> {
> @@ -1757,16 +1804,15 @@ static void gen_CMP(DisasContext *s, X86DecodedInsn *decode)
> MemOp ot = decode->op[1].ot;
> TCGv cout;
>
> - switch (cond) {
> - case CCMP_T:
> + if (gen_ccmp_movcond(s, cond, dfv, ot)) {
> + /* Including CCMP_T, aka "normal" CMP. */
> gen_SUB(s, decode);
> return;
> - case CCMP_F:
> + }
> + if (cond == CCMP_F) {
> decode->cc_op = CC_OP_EFLAGS;
> decode->cc_src = tcg_constant_tl(dfv);
> return;
> - default:
> - break;
> }
...check the CCMP_F and return first:
if (cond == CCMP_F) {
...
return;
}
if (gen_ccmp_movcond(s, cond, dfv, ot)) {
...
return;
}
Thanks,
Zhao
next prev parent reply other threads:[~2026-09-02 9:30 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-25 12:29 [PATCH 00/20] target/i386/tcg: implement APX Paolo Bonzini
2026-08-25 12:29 ` [PATCH 01/20] target/i386/tcg: do not reuse cc_srcT Paolo Bonzini
2026-08-25 23:09 ` Richard Henderson
2026-08-25 12:29 ` [PATCH 02/20] target/i386/tcg: inline gen_ext_tl Paolo Bonzini
2026-08-25 23:09 ` Richard Henderson
2026-08-25 12:29 ` [PATCH 03/20] target/i386/tcg: simplify return value of gen_prepare_cc Paolo Bonzini
2026-08-25 12:29 ` [PATCH 04/20] target/i386/tcg: move check bits out of validate_vex Paolo Bonzini
2026-08-25 12:29 ` [PATCH 05/20] target/i386/tcg: add APX support to XSAVE/XRSTOR Paolo Bonzini
2026-09-08 2:10 ` Chang S. Bae
2026-08-25 12:29 ` [PATCH 06/20] target/i386/tcg: treat VEX as disabling high-byte registers Paolo Bonzini
2026-08-25 12:29 ` [PATCH 07/20] target/i386/tcg: add definition for REX2 prefix Paolo Bonzini
2026-09-08 2:10 ` Chang S. Bae
2026-08-25 12:29 ` [PATCH 08/20] target/i386/tcg: mark XSAVE* as not allowing REX2 Paolo Bonzini
2026-09-08 2:10 ` Chang S. Bae
2026-08-25 12:29 ` [PATCH 09/20] target/i386/tcg: decode REX2 prefix Paolo Bonzini
2026-09-08 2:10 ` Chang S. Bae
2026-08-25 12:29 ` [PATCH 10/20] target/i386/tcg: implement JMPABS instruction Paolo Bonzini
2026-08-26 14:30 ` Zhao Liu
2026-08-27 6:33 ` Paolo Bonzini
2026-08-25 12:29 ` [PATCH 11/20] target/i386/tcg: fetch modrm early Paolo Bonzini
2026-08-25 12:29 ` [PATCH 12/20] target/i386/tcg: move VEX validation early Paolo Bonzini
2026-08-28 8:32 ` Zhao Liu
2026-08-25 12:29 ` [PATCH 13/20] target/i386/tcg: extend VEX.vvvv parsing for APX Paolo Bonzini
2026-08-25 12:29 ` [PATCH 14/20] target/i386/tcg: decode EVEX prefix Paolo Bonzini
2026-08-28 9:10 ` Zhao Liu
2026-08-25 12:29 ` [PATCH 15/20] target/i386/tcg: add ZU writeback Paolo Bonzini
2026-08-25 12:29 ` [PATCH 16/20] target/i386/tcg: add decode functionality for APX Paolo Bonzini
2026-09-01 14:56 ` Zhao Liu
2026-09-02 6:55 ` Zhao Liu
2026-08-25 12:29 ` [PATCH 17/20] target/i386/tcg: implement CCMP/CTEST Paolo Bonzini
2026-09-02 6:06 ` Zhao Liu
2026-08-25 12:29 ` [PATCH 18/20] target/i386/tcg: decode APX instructions Paolo Bonzini
2026-09-02 7:27 ` Zhao Liu
2026-08-25 12:29 ` [PATCH 19/20] target/i386/tcg: mark APX as supported Paolo Bonzini
2026-09-02 9:15 ` Zhao Liu
2026-08-25 12:29 ` [PATCH 20/20] target/i386/tcg: optimize CCMP Paolo Bonzini
2026-09-02 9:29 ` Zhao Liu [this message]
2026-09-08 2:10 ` [PATCH 00/20] target/i386/tcg: implement APX Chang S. Bae
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