[PATCH v4 0/4] target/i386: Add Zhaoxin Shijidadao CPU model

[PATCH v4 0/4] target/i386: Add Zhaoxin Shijidadao CPU model

[Ewan Hai-oc]

Add CPU models for the Zhaoxin Shijidadao server (v1) and client (v2),
including their cache topology.  The matching KVM support for SM2, CCS,
RNG2, PHE2 and RSA is queued in the KVM next branch.

The series also adds YongFeng-v4 with the same five feature pairs.

TCG does not currently implement these instructions.  TCG_EXT4_FEATURES
remains zero, so QEMU filters the new bits from realized TCG CPUs.

The Shijidadao models expose CPUID leaf 0x1f.  A related fix for invalid
subleaf handling under TCG is available here:
https://lore.kernel.org/qemu-devel/20260609090046.2376016-1-ewanhai-oc@zhaoxin.com/

Changes since v3:
- Rebased to the 11.2 development tree.
- Added QEMU definitions for the five feature pairs now available
  through KVM.
- Enabled the new CPUID 0xC0000001 EDX feature pairs in the Shijidadao
  models and adjusted the server and client feature sets to match their
  respective silicon.
- Added YongFeng-v4 with the same feature set.

v3:
https://lore.kernel.org/all/20260109021028.83985-1-ewanhai-oc@zhaoxin.com/

KVM feature series:
https://lore.kernel.org/all/20260610023512.3690734-1-ewanhai-oc@zhaoxin.com/

Ewan Hai (4):
  target/i386: Add cache model for Zhaoxin Shijidadao vCPUs
  target/i386: Add Zhaoxin cryptographic CPUID features
  target/i386: Introduce Zhaoxin Shijidadao CPU model
  target/i386: Enable new cryptographic features in YongFeng-v4

 target/i386/cpu.c | 284 ++++++++++++++++++++++++++++++++++++++++++++--
 target/i386/cpu.h |  20 ++++
 2 files changed, 295 insertions(+), 9 deletions(-)

-- 
2.34.1

[PATCH v4 1/4] target/i386: Add cache model for Zhaoxin Shijidadao vCPUs

[Ewan Hai-oc]

Zhaoxin "Shijidadao" vCPUs require built-in cache enumeration in QEMU
to properly report CPUID leaf 0x4 and 0x80000005/0x80000006 when
'host-cache-info' is disabled.

This patch defines the L1/L2/L3 cache parameters for the Shijidadao
architecture, preparing for use in both client and server models.

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
---
 target/i386/cpu.c | 99 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 99 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e5ffb10d15..5408d851d1 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3512,6 +3512,105 @@ static const CPUCaches yongfeng_cache_info = {
     },
 };
 
+static const CPUCaches shijidadao_cache_info = {
+    .l1d_cache = &(CPUCacheInfo) {
+        /* CPUID 0x4.0x0.EAX */
+        .type = DATA_CACHE,
+        .level = 1,
+        .self_init = true,
+
+        /* CPUID 0x4.0x0.EBX */
+        .line_size = 64,
+        .partitions = 1,
+        .associativity = 8,
+
+        /* CPUID 0x4.0x0.ECX */
+        .sets = 64,
+
+        /* CPUID 0x4.0x0.EDX */
+        .no_invd_sharing = false,
+        .inclusive = false,
+        .complex_indexing = false,
+
+        /* CPUID 0x80000005.ECX */
+        .lines_per_tag = 1,
+        .size = 32 * KiB,
+
+        .share_level = CPU_TOPOLOGY_LEVEL_CORE,
+    },
+    .l1i_cache = &(CPUCacheInfo) {
+        /* CPUID 0x4.0x1.EAX */
+        .type = INSTRUCTION_CACHE,
+        .level = 1,
+        .self_init = true,
+
+        /* CPUID 0x4.0x1.EBX */
+        .line_size = 64,
+        .partitions = 1,
+        .associativity = 16,
+
+        /* CPUID 0x4.0x1.ECX */
+        .sets = 64,
+
+        /* CPUID 0x4.0x1.EDX */
+        .no_invd_sharing = false,
+        .inclusive = false,
+        .complex_indexing = false,
+
+        /* CPUID 0x80000005.EDX */
+        .lines_per_tag = 1,
+        .size = 64 * KiB,
+
+        .share_level = CPU_TOPOLOGY_LEVEL_CORE,
+    },
+    .l2_cache = &(CPUCacheInfo) {
+        /* CPUID 0x4.0x2.EAX */
+        .type = UNIFIED_CACHE,
+        .level = 2,
+        .self_init = true,
+
+        /* CPUID 0x4.0x2.EBX */
+        .line_size = 64,
+        .partitions = 1,
+        .associativity = 8,
+
+        /* CPUID 0x4.0x2.ECX */
+        .sets = 1024,
+
+        /* CPUID 0x4.0x2.EDX */
+        .no_invd_sharing = false,
+        .inclusive = true,
+        .complex_indexing = false,
+
+        /* CPUID 0x80000006.ECX */
+        .size = 512 * KiB,
+
+        .share_level = CPU_TOPOLOGY_LEVEL_CORE,
+    },
+    .l3_cache = &(CPUCacheInfo) {
+        /* CPUID 0x4.0x3.EAX */
+        .type = UNIFIED_CACHE,
+        .level = 3,
+        .self_init = true,
+
+        /* CPUID 0x4.0x3.EBX */
+        .line_size = 64,
+        .partitions = 1,
+        .associativity = 16,
+
+        /* CPUID 0x4.0x3.ECX */
+        .sets = 32768,
+
+        /* CPUID 0x4.0x3.EDX */
+        .no_invd_sharing = false,
+        .inclusive = true,
+        .complex_indexing = false,
+
+        .size = 32 * MiB,
+        .share_level = CPU_TOPOLOGY_LEVEL_DIE,
+    },
+};
+
 /* The following VMX features are not supported by KVM and are left out in the
  * CPU definitions:
  *
-- 
2.34.1

[PATCH v4 2/4] target/i386: Add Zhaoxin cryptographic CPUID features

[Ewan Hai-oc]

Add QEMU feature names and masks for the SM2, CCS, RNG2, PHE2 and RSA
feature pairs in CPUID 0xC0000001 EDX. The matching KVM support exposes
these bits through KVM_GET_SUPPORTED_CPUID.

TCG does not currently implement these instructions. Keep
TCG_EXT4_FEATURES at zero so QEMU filters the bits from realized TCG
CPUs.

Link: https://lore.kernel.org/all/20260610023512.3690734-1-ewanhai-oc@zhaoxin.com/
Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
---
 target/i386/cpu.c | 10 +++++-----
 target/i386/cpu.h | 20 ++++++++++++++++++++
 2 files changed, 25 insertions(+), 5 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 5408d851d1..1107d1243c 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1120,14 +1120,14 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
     [FEAT_C000_0001_EDX] = {
         .type = CPUID_FEATURE_WORD,
         .feat_names = {
-            NULL, NULL, "xstore", "xstore-en",
-            NULL, NULL, "xcrypt", "xcrypt-en",
+            "sm2", "sm2-en", "xstore", "xstore-en",
+            "ccs", "ccs-en", "xcrypt", "xcrypt-en",
             "ace2", "ace2-en", "phe", "phe-en",
             "pmm", "pmm-en", NULL, NULL,
             NULL, NULL, NULL, NULL,
-            NULL, NULL, NULL, NULL,
-            NULL, NULL, NULL, NULL,
-            NULL, NULL, NULL, NULL,
+            NULL, NULL, "rng2", "rng2-en",
+            NULL, "phe2", "phe2-en", "rsa",
+            "rsa-en", NULL, NULL, NULL,
         },
         .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
         .tcg_features = TCG_EXT4_FEATURES,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 641f3ee5c2..60327688f4 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1243,10 +1243,18 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
 /* CPUID[0x80000007].EDX flags: */
 #define CPUID_APM_INVTSC       (1U << 8)
 
+/* SM2 algorithm */
+#define CPUID_C000_0001_EDX_SM2                (1U << 0)
+/* SM2 enabled */
+#define CPUID_C000_0001_EDX_SM2_EN             (1U << 1)
 /* "rng" RNG present (xstore) */
 #define CPUID_C000_0001_EDX_XSTORE             (1U << 2)
 /* "rng_en" RNG enabled */
 #define CPUID_C000_0001_EDX_XSTORE_EN          (1U << 3)
+/* SM3 and SM4 algorithms */
+#define CPUID_C000_0001_EDX_CCS                (1U << 4)
+/* CCS enabled */
+#define CPUID_C000_0001_EDX_CCS_EN             (1U << 5)
 /* "ace" on-CPU crypto (xcrypt) */
 #define CPUID_C000_0001_EDX_XCRYPT             (1U << 6)
 /* "ace_en" on-CPU crypto enabled */
@@ -1263,6 +1271,18 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
 #define CPUID_C000_0001_EDX_PMM                (1U << 12)
 /* PMM enabled */
 #define CPUID_C000_0001_EDX_PMM_EN             (1U << 13)
+/* Random Number Generator v2 */
+#define CPUID_C000_0001_EDX_RNG2               (1U << 22)
+/* RNG2 enabled */
+#define CPUID_C000_0001_EDX_RNG2_EN            (1U << 23)
+/* PadLock Hash Engine v2 */
+#define CPUID_C000_0001_EDX_PHE2               (1U << 25)
+/* PHE2 enabled */
+#define CPUID_C000_0001_EDX_PHE2_EN            (1U << 26)
+/* Big-number arithmetic */
+#define CPUID_C000_0001_EDX_RSA                (1U << 27)
+/* RSA enabled */
+#define CPUID_C000_0001_EDX_RSA_EN             (1U << 28)
 
 #define CPUID_VENDOR_SZ     12
 #define CPUID_MODEL_ID_SZ   48
-- 
2.34.1

[PATCH v4 3/4] target/i386: Introduce Zhaoxin Shijidadao CPU model

[Ewan Hai-oc]

Introduce the Zhaoxin Shijidadao CPU model with two versions:

- v1 (alias: Shijidadao-Server) - Server variant with CORE_CAPABILITY
  and SPLIT_LOCK_DETECT support
- v2 (alias: Shijidadao-Client) - Client variant with different FMS
  (model=0x6b, stepping=1), with neither CORE_CAPABILITY features nor
  the ACE2 feature pair

Both versions include the SM2, CCS, RNG2, PHE2 and RSA feature pairs
exposed by KVM.

The model_id for both variants is 'Zhaoxin Shijidadao Processor'.

Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
---
 target/i386/cpu.c | 153 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 153 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1107d1243c..70904810b5 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7409,6 +7409,159 @@ static const X86CPUDefinition builtin_x86_defs[] = {
             { /* end of list */ }
         }
     },
+    {
+        .name = "Shijidadao",
+        .level = 0x1f,
+        .vendor = CPUID_VENDOR_ZHAOXIN1,
+        .family = 7,
+        .model = 0x7b,
+        .stepping = 0,
+        .cpuid_0x1f = true,
+        /* missing: CPUID_HT, CPUID_TM, CPUID_PBE */
+        .features[FEAT_1_EDX] =
+            CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+            CPUID_ACPI | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
+            CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
+            CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
+            CPUID_PSE | CPUID_DE | CPUID_VME | CPUID_FP87,
+        /*
+         * missing: CPUID_EXT_OSXSAVE, CPUID_EXT_XTPR, CPUID_EXT_TM2,
+         * CPUID_EXT_EST, CPUID_EXT_SMX, CPUID_EXT_VMX
+         */
+        .features[FEAT_1_ECX] =
+            CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
+            CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_TSC_DEADLINE_TIMER |
+            CPUID_EXT_POPCNT | CPUID_EXT_MOVBE | CPUID_EXT_X2APIC |
+            CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_PCID |
+            CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
+            CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
+        .features[FEAT_7_0_EBX] =
+            CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_RDSEED |
+            CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_SMEP |
+            CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_FSGSBASE,
+        /* missing: CPUID_7_0_ECX_OSPKE */
+        .features[FEAT_7_0_ECX] =
+            CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_UMIP,
+        .features[FEAT_7_0_EDX] =
+            CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL |
+            CPUID_7_0_EDX_CORE_CAPABILITY,
+        .features[FEAT_CORE_CAPABILITY] =
+            MSR_CORE_CAP_SPLIT_LOCK_DETECT,
+        .features[FEAT_8000_0001_EDX] =
+            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
+            CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
+        .features[FEAT_8000_0001_ECX] =
+            CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
+        .features[FEAT_8000_0007_EDX] = CPUID_APM_INVTSC,
+        /* missing: PARALLAX/PARALLAX_EN, TM3/TM3_EN */
+        .features[FEAT_C000_0001_EDX] =
+            CPUID_C000_0001_EDX_RSA_EN | CPUID_C000_0001_EDX_RSA |
+            CPUID_C000_0001_EDX_PHE2_EN | CPUID_C000_0001_EDX_PHE2 |
+            CPUID_C000_0001_EDX_RNG2_EN | CPUID_C000_0001_EDX_RNG2 |
+            CPUID_C000_0001_EDX_PMM_EN | CPUID_C000_0001_EDX_PMM |
+            CPUID_C000_0001_EDX_PHE_EN | CPUID_C000_0001_EDX_PHE |
+            CPUID_C000_0001_EDX_ACE2_EN | CPUID_C000_0001_EDX_ACE2 |
+            CPUID_C000_0001_EDX_XCRYPT_EN | CPUID_C000_0001_EDX_XCRYPT |
+            CPUID_C000_0001_EDX_CCS_EN | CPUID_C000_0001_EDX_CCS |
+            CPUID_C000_0001_EDX_XSTORE_EN | CPUID_C000_0001_EDX_XSTORE |
+            CPUID_C000_0001_EDX_SM2_EN | CPUID_C000_0001_EDX_SM2,
+        .features[FEAT_XSAVE] =
+            CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1 |
+            CPUID_XSAVE_XSAVES,
+        .features[FEAT_ARCH_CAPABILITIES] =
+            MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY |
+            MSR_ARCH_CAP_MDS_NO | MSR_ARCH_CAP_PSCHANGE_MC_NO |
+            MSR_ARCH_CAP_SSB_NO,
+        .features[FEAT_VMX_PROCBASED_CTLS] =
+            VMX_CPU_BASED_VIRTUAL_INTR_PENDING | VMX_CPU_BASED_HLT_EXITING |
+            VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_INVLPG_EXITING |
+            VMX_CPU_BASED_MWAIT_EXITING | VMX_CPU_BASED_RDPMC_EXITING |
+            VMX_CPU_BASED_RDTSC_EXITING | VMX_CPU_BASED_CR3_LOAD_EXITING |
+            VMX_CPU_BASED_CR3_STORE_EXITING | VMX_CPU_BASED_CR8_LOAD_EXITING |
+            VMX_CPU_BASED_CR8_STORE_EXITING | VMX_CPU_BASED_TPR_SHADOW |
+            VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_MOV_DR_EXITING |
+            VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
+            VMX_CPU_BASED_MONITOR_TRAP_FLAG | VMX_CPU_BASED_USE_MSR_BITMAPS |
+            VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
+            VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
+        /*
+         * missing: VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING,
+         * VMX_SECONDARY_EXEC_TSC_SCALING
+         */
+        .features[FEAT_VMX_SECONDARY_CTLS] =
+            VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
+            VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC |
+            VMX_SECONDARY_EXEC_RDTSCP | VMX_SECONDARY_EXEC_ENABLE_VPID |
+            VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
+            VMX_SECONDARY_EXEC_WBINVD_EXITING |
+            VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
+            VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
+            VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
+            VMX_SECONDARY_EXEC_RDRAND_EXITING |
+            VMX_SECONDARY_EXEC_ENABLE_INVPCID |
+            VMX_SECONDARY_EXEC_ENABLE_VMFUNC |
+            VMX_SECONDARY_EXEC_SHADOW_VMCS |
+            VMX_SECONDARY_EXEC_XSAVES      |
+            VMX_SECONDARY_EXEC_ENABLE_PML,
+        .features[FEAT_VMX_PINBASED_CTLS] =
+            VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING |
+            VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER |
+            VMX_PIN_BASED_POSTED_INTR,
+        .features[FEAT_VMX_EXIT_CTLS] =
+            VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE |
+            VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
+            VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
+            VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
+            VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
+        /* missing: VMX_VM_ENTRY_SMM, VMX_VM_ENTRY_DEACT_DUAL_MONITOR */
+        .features[FEAT_VMX_ENTRY_CTLS] =
+            VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE |
+            VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
+            VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER,
+        /*
+         * missing: MSR_VMX_MISC_ACTIVITY_SHUTDOWN,
+         * MSR_VMX_MISC_ACTIVITY_WAIT_SIPI
+         */
+        .features[FEAT_VMX_MISC] =
+            MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT |
+            MSR_VMX_MISC_VMWRITE_VMEXIT,
+        /* missing: MSR_VMX_EPT_UC */
+        .features[FEAT_VMX_EPT_VPID_CAPS] =
+            MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 |
+            MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB |
+            MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS |
+            MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
+            MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID |
+            MSR_VMX_EPT_INVVPID_ALL_CONTEXT | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
+            MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
+        .features[FEAT_VMX_BASIC] =
+            MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS,
+        .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
+        .xlevel = 0x80000008,
+        .model_id = "Zhaoxin Shijidadao Processor",
+        .cache_info = &shijidadao_cache_info,
+        .versions = (X86CPUVersionDefinition[]) {
+            {
+                .version = 1,
+                .alias = "Shijidadao-Server",
+            },
+            {
+                .version = 2,
+                .alias = "Shijidadao-Client",
+                .note = "client variant",
+                .props = (PropValue[]) {
+                    { "model", "0x6b" },
+                    { "stepping", "1" },
+                    { "ace2", "off" },
+                    { "ace2-en", "off" },
+                    { "core-capability", "off" },
+                    { "split-lock-detect", "off" },
+                    { /* end of list */ }
+                },
+            },
+            { /* end of list */ }
+        }
+    },
 };
 
 /*
-- 
2.34.1

[PATCH v4 4/4] target/i386: Enable new cryptographic features in YongFeng-v4

[Ewan Hai-oc]

Add YongFeng-v4 with the SM2, CCS, RNG2, PHE2 and RSA feature pairs
enabled.

Link: https://lore.kernel.org/all/20260610023512.3690734-1-ewanhai-oc@zhaoxin.com/
Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
---
 target/i386/cpu.c | 22 ++++++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 70904810b5..0e842d0c80 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7208,10 +7208,7 @@ static const X86CPUDefinition builtin_x86_defs[] = {
         .features[FEAT_8000_0001_ECX] =
             CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
         .features[FEAT_8000_0007_EDX] = CPUID_APM_INVTSC,
-        /*
-         * TODO: When the Linux kernel introduces other existing definitions
-         * for this leaf, remember to update the definitions here.
-         */
+        /* missing: PARALLAX/PARALLAX_EN, TM3/TM3_EN */
         .features[FEAT_C000_0001_EDX] =
             CPUID_C000_0001_EDX_PMM_EN | CPUID_C000_0001_EDX_PMM |
             CPUID_C000_0001_EDX_PHE_EN | CPUID_C000_0001_EDX_PHE |
@@ -7309,6 +7306,23 @@ static const X86CPUDefinition builtin_x86_defs[] = {
                     { /* end of list */ },
                 }
             },
+            {
+                .version = 4,
+                .note = "with additional cryptographic features",
+                .props = (PropValue[]) {
+                    { "sm2", "on" },
+                    { "sm2-en", "on" },
+                    { "ccs", "on" },
+                    { "ccs-en", "on" },
+                    { "rng2", "on" },
+                    { "rng2-en", "on" },
+                    { "phe2", "on" },
+                    { "phe2-en", "on" },
+                    { "rsa", "on" },
+                    { "rsa-en", "on" },
+                    { /* end of list */ },
+                }
+            },
             { /* end of list */ }
         }
     },
-- 
2.34.1

Re: [PATCH v4 2/4] target/i386: Add Zhaoxin cryptographic CPUID features

[Zhao Liu]

On Wed, Aug 26, 2026 at 04:48:36PM +0800, Ewan Hai-oc wrote:
> Date: Wed, 26 Aug 2026 16:48:36 +0800
> From: Ewan Hai-oc <ewanhai-oc@zhaoxin.com>
> Subject: [PATCH v4 2/4] target/i386: Add Zhaoxin cryptographic CPUID
>  features
> X-Mailer: git-send-email 2.34.1
> 
> Add QEMU feature names and masks for the SM2, CCS, RNG2, PHE2 and RSA
> feature pairs in CPUID 0xC0000001 EDX. The matching KVM support exposes
> these bits through KVM_GET_SUPPORTED_CPUID.
> 
> TCG does not currently implement these instructions. Keep
> TCG_EXT4_FEATURES at zero so QEMU filters the bits from realized TCG
> CPUs.
> 
> Link: https://lore.kernel.org/all/20260610023512.3690734-1-ewanhai-oc@zhaoxin.com/
> Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
> ---
>  target/i386/cpu.c | 10 +++++-----
>  target/i386/cpu.h | 20 ++++++++++++++++++++
>  2 files changed, 25 insertions(+), 5 deletions(-)

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

Re: [PATCH v4 3/4] target/i386: Introduce Zhaoxin Shijidadao CPU model

[Zhao Liu]

On Wed, Aug 26, 2026 at 04:48:37PM +0800, Ewan Hai-oc wrote:
> Date: Wed, 26 Aug 2026 16:48:37 +0800
> From: Ewan Hai-oc <ewanhai-oc@zhaoxin.com>
> Subject: [PATCH v4 3/4] target/i386: Introduce Zhaoxin Shijidadao CPU model
> X-Mailer: git-send-email 2.34.1
> 
> Introduce the Zhaoxin Shijidadao CPU model with two versions:
> 
> - v1 (alias: Shijidadao-Server) - Server variant with CORE_CAPABILITY
>   and SPLIT_LOCK_DETECT support
> - v2 (alias: Shijidadao-Client) - Client variant with different FMS
>   (model=0x6b, stepping=1), with neither CORE_CAPABILITY features nor
>   the ACE2 feature pair
> 
> Both versions include the SM2, CCS, RNG2, PHE2 and RSA feature pairs
> exposed by KVM.
> 
> The model_id for both variants is 'Zhaoxin Shijidadao Processor'.
> 
> Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
> ---
>  target/i386/cpu.c | 153 ++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 153 insertions(+)

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

Re: [PATCH v4 4/4] target/i386: Enable new cryptographic features in YongFeng-v4

[Zhao Liu]

On Wed, Aug 26, 2026 at 04:48:38PM +0800, Ewan Hai-oc wrote:
> Date: Wed, 26 Aug 2026 16:48:38 +0800
> From: Ewan Hai-oc <ewanhai-oc@zhaoxin.com>
> Subject: [PATCH v4 4/4] target/i386: Enable new cryptographic features in
>  YongFeng-v4
> X-Mailer: git-send-email 2.34.1
> 
> Add YongFeng-v4 with the SM2, CCS, RNG2, PHE2 and RSA feature pairs
> enabled.
> 
> Link: https://lore.kernel.org/all/20260610023512.3690734-1-ewanhai-oc@zhaoxin.com/
> Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
> ---
>  target/i386/cpu.c | 22 ++++++++++++++++++----
>  1 file changed, 18 insertions(+), 4 deletions(-)

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>