* [RFC PATCH 17/22] perf/events: arm64: ti: Add J7 DDR performance events
@ 2026-07-14 12:56 MANNURU VENKATESWARLU
2026-07-14 12:56 ` [RFC PATCH 18/22] perf/events: arm64: ti: Add AM62 " MANNURU VENKATESWARLU
` (5 more replies)
0 siblings, 6 replies; 7+ messages in thread
From: MANNURU VENKATESWARLU @ 2026-07-14 12:56 UTC (permalink / raw)
To: peterz, mingo, acme
Cc: linux-arm-kernel, linux-perf-users, n-francis, s-k6, bb,
v-mannuru
Add perf JSON event and metric definitions for the J7 family
DDR controller PMU covering J721E, J721S2, J7200 and J784S4.
Signed-off-by: MANNURU VENKATESWARLU <v-mannuru@ti.com>
---
.../pmu-events/arch/arm64/ti/j7/sys/ddrc.json | 240 ++++++++++++++++++
.../arch/arm64/ti/j7/sys/metrics.json | 34 +++
2 files changed, 274 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/ti/j7/sys/ddrc.json
create mode 100644 tools/perf/pmu-events/arch/arm64/ti/j7/sys/metrics.json
diff --git a/tools/perf/pmu-events/arch/arm64/ti/j7/sys/ddrc.json b/tools/perf/pmu-events/arch/arm64/ti/j7/sys/ddrc.json
new file mode 100644
index 0000000000000..7ed64c25500d4
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/ti/j7/sys/ddrc.json
@@ -0,0 +1,240 @@
+[
+ {
+ "BriefDescription": "Counts every Write command",
+ "EventCode": "0x00",
+ "EventName": "k3_ddr.write",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every Read command",
+ "EventCode": "0x01",
+ "EventName": "k3_ddr.read",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every read as a result of a RMW command",
+ "EventCode": "0x02",
+ "EventName": "k3_ddr.read_rmw",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every Activate command",
+ "EventCode": "0x03",
+ "EventName": "k3_ddr.activate",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every Precharge command",
+ "EventCode": "0x04",
+ "EventName": "k3_ddr.precharge",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every Precharge All command",
+ "EventCode": "0x05",
+ "EventName": "k3_ddr.precharge_all",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every Mode Register Read command",
+ "EventCode": "0x06",
+ "EventName": "k3_ddr.mode_reg_read",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every Mode Register Write command",
+ "EventCode": "0x07",
+ "EventName": "k3_ddr.mode_reg_write",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every Per Bank Refresh command",
+ "EventCode": "0x08",
+ "EventName": "k3_ddr.per_bank_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every Auto Refresh command",
+ "EventCode": "0x09",
+ "EventName": "k3_ddr.auto_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every ZQ Calib Long command",
+ "EventCode": "0x0a",
+ "EventName": "k3_ddr.zq_calib_long",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every ZQ Calib Short command",
+ "EventCode": "0x0b",
+ "EventName": "k3_ddr.zq_calib_short",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every Write-to-Read and Read-to-Write bus-turn-around",
+ "EventCode": "0x0c",
+ "EventName": "k3_ddr.bus_turn_around",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every Write-to-Write address collision",
+ "EventCode": "0x0d",
+ "EventName": "k3_ddr.write_write_collision",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every Write-to-Read address collision",
+ "EventCode": "0x0e",
+ "EventName": "k3_ddr.write_read_collision",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every Read-to-Write address collision",
+ "EventCode": "0x0f",
+ "EventName": "k3_ddr.read_write_collision",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every Read-to-Read address collision",
+ "EventCode": "0x10",
+ "EventName": "k3_ddr.read_read_collision",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every exit from Power-Down Self-Refresh mode",
+ "EventCode": "0x11",
+ "EventName": "k3_ddr.exit_power_down_self_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every entry into Power-Down Self-Refresh mode",
+ "EventCode": "0x12",
+ "EventName": "k3_ddr.entry_power_down_self_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller stays in Power-Down Self-Refresh mode",
+ "EventCode": "0x13",
+ "EventName": "k3_ddr.power_down_self_refresh_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every exit from Power-Down mode",
+ "EventCode": "0x14",
+ "EventName": "k3_ddr.exit_power_down",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every entry into Power-Down mode",
+ "EventCode": "0x15",
+ "EventName": "k3_ddr.entry_power_down",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller stays in Power-Down mode",
+ "EventCode": "0x16",
+ "EventName": "k3_ddr.power_down_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every exit from Self-Refresh mode",
+ "EventCode": "0x17",
+ "EventName": "k3_ddr.exit_self_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every entry into Self-Refresh mode",
+ "EventCode": "0x18",
+ "EventName": "k3_ddr.entry_self_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller stays in Self-Refresh mode",
+ "EventCode": "0x19",
+ "EventName": "k3_ddr.self_refresh_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller command queue is full",
+ "EventCode": "0x1c",
+ "EventName": "k3_ddr.command_queue_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller info FIFO is full",
+ "EventCode": "0x1d",
+ "EventName": "k3_ddr.info_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller write latency FIFO is full",
+ "EventCode": "0x1e",
+ "EventName": "k3_ddr.write_latency_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller port command FIFO is full",
+ "EventCode": "0x1f",
+ "EventName": "k3_ddr.port_command_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller write response FIFO is full",
+ "EventCode": "0x20",
+ "EventName": "k3_ddr.write_response_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller port write FIFO is full",
+ "EventCode": "0x21",
+ "EventName": "k3_ddr.port_write_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller core read FIFO is full",
+ "EventCode": "0x22",
+ "EventName": "k3_ddr.core_read_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller port read FIFO is full",
+ "EventCode": "0x23",
+ "EventName": "k3_ddr.port_read_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "J7"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/ti/j7/sys/metrics.json b/tools/perf/pmu-events/arch/arm64/ti/j7/sys/metrics.json
new file mode 100644
index 0000000000000..156b2c9dec185
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/ti/j7/sys/metrics.json
@@ -0,0 +1,34 @@
+[
+ {
+ "BriefDescription": "DDR memory read bandwidth in MB/s (32-bit bus, BL16)",
+ "MetricExpr": "(k3_ddr.read * 64) / (duration_time * 1e6)",
+ "MetricGroup": "ddr",
+ "MetricName": "k3_ddr_j7.read_bandwidth_mbytes_sec",
+ "ScaleUnit": "1MB/s",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "DDR memory write bandwidth in MB/s (32-bit bus, BL16)",
+ "MetricExpr": "(k3_ddr.write * 64) / (duration_time * 1e6)",
+ "MetricGroup": "ddr",
+ "MetricName": "k3_ddr_j7.write_bandwidth_mbytes_sec",
+ "ScaleUnit": "1MB/s",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Average DDR read requests per second",
+ "MetricExpr": "k3_ddr.read / duration_time",
+ "MetricGroup": "ddr",
+ "MetricName": "k3_ddr_j7.read_requests_per_sec",
+ "ScaleUnit": "1reads/sec",
+ "Compat": "J7"
+ },
+ {
+ "BriefDescription": "Average DDR write requests per second",
+ "MetricExpr": "k3_ddr.write / duration_time",
+ "MetricGroup": "ddr",
+ "MetricName": "k3_ddr_j7.write_requests_per_sec",
+ "ScaleUnit": "1writes/sec",
+ "Compat": "J7"
+ }
+]
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [RFC PATCH 18/22] perf/events: arm64: ti: Add AM62 DDR performance events
2026-07-14 12:56 [RFC PATCH 17/22] perf/events: arm64: ti: Add J7 DDR performance events MANNURU VENKATESWARLU
@ 2026-07-14 12:56 ` MANNURU VENKATESWARLU
2026-07-14 12:56 ` [RFC PATCH 19/22] perf/events: arm64: ti: Add AM62A " MANNURU VENKATESWARLU
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: MANNURU VENKATESWARLU @ 2026-07-14 12:56 UTC (permalink / raw)
To: peterz, mingo, acme
Cc: linux-arm-kernel, linux-perf-users, n-francis, s-k6, bb,
v-mannuru
From: Aarya Chaumal <a-chaumal@ti.com>
Add perf JSON event and metric definitions for the AM62
DDR controller PMU.
Signed-off-by: MANNURU VENKATESWARLU <v-mannuru@ti.com>
Signed-off-by: Aarya Chaumal <a-chaumal@ti.com>
---
.../arch/arm64/ti/am62/sys/ddrc.json | 240 ++++++++++++++++++
.../arch/arm64/ti/am62/sys/metrics.json | 34 +++
2 files changed, 274 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/ti/am62/sys/ddrc.json
create mode 100644 tools/perf/pmu-events/arch/arm64/ti/am62/sys/metrics.json
diff --git a/tools/perf/pmu-events/arch/arm64/ti/am62/sys/ddrc.json b/tools/perf/pmu-events/arch/arm64/ti/am62/sys/ddrc.json
new file mode 100644
index 0000000000000..4cc794477d1d9
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/ti/am62/sys/ddrc.json
@@ -0,0 +1,240 @@
+[
+ {
+ "BriefDescription": "Counts every Write command",
+ "EventCode": "0x00",
+ "EventName": "k3_ddr.write",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every Read command",
+ "EventCode": "0x01",
+ "EventName": "k3_ddr.read",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every read as a result of a RMW command",
+ "EventCode": "0x02",
+ "EventName": "k3_ddr.read_rmw",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every Activate command",
+ "EventCode": "0x03",
+ "EventName": "k3_ddr.activate",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every Precharge command",
+ "EventCode": "0x04",
+ "EventName": "k3_ddr.precharge",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every Precharge All command",
+ "EventCode": "0x05",
+ "EventName": "k3_ddr.precharge_all",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every Mode Register Read command",
+ "EventCode": "0x06",
+ "EventName": "k3_ddr.mode_reg_read",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every Mode Register Write command",
+ "EventCode": "0x07",
+ "EventName": "k3_ddr.mode_reg_write",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every Per Bank Refresh command",
+ "EventCode": "0x08",
+ "EventName": "k3_ddr.per_bank_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every Auto Refresh command",
+ "EventCode": "0x09",
+ "EventName": "k3_ddr.auto_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every ZQ Calib Long command",
+ "EventCode": "0x0a",
+ "EventName": "k3_ddr.zq_calib_long",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every ZQ Calib Short command",
+ "EventCode": "0x0b",
+ "EventName": "k3_ddr.zq_calib_short",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every Write-to-Read and Read-to-Write bus-turn-around",
+ "EventCode": "0x0c",
+ "EventName": "k3_ddr.bus_turn_around",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every Write-to-Write address collision",
+ "EventCode": "0x0d",
+ "EventName": "k3_ddr.write_write_collision",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every Write-to-Read address collision",
+ "EventCode": "0x0e",
+ "EventName": "k3_ddr.write_read_collision",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every Read-to-Write address collision",
+ "EventCode": "0x0f",
+ "EventName": "k3_ddr.read_write_collision",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every Read-to-Read address collision",
+ "EventCode": "0x10",
+ "EventName": "k3_ddr.read_read_collision",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every exit from Power-Down Self-Refresh mode",
+ "EventCode": "0x11",
+ "EventName": "k3_ddr.exit_power_down_self_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every entry into Power-Down Self-Refresh mode",
+ "EventCode": "0x12",
+ "EventName": "k3_ddr.entry_power_down_self_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller stays in Power-Down Self-Refresh mode",
+ "EventCode": "0x13",
+ "EventName": "k3_ddr.power_down_self_refresh_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every exit from Power-Down mode",
+ "EventCode": "0x14",
+ "EventName": "k3_ddr.exit_power_down",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every entry into Power-Down mode",
+ "EventCode": "0x15",
+ "EventName": "k3_ddr.entry_power_down",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller stays in Power-Down mode",
+ "EventCode": "0x16",
+ "EventName": "k3_ddr.power_down_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every exit from Self-Refresh mode",
+ "EventCode": "0x17",
+ "EventName": "k3_ddr.exit_self_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every entry into Self-Refresh mode",
+ "EventCode": "0x18",
+ "EventName": "k3_ddr.entry_self_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller stays in Self-Refresh mode",
+ "EventCode": "0x19",
+ "EventName": "k3_ddr.self_refresh_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller command queue is full",
+ "EventCode": "0x1c",
+ "EventName": "k3_ddr.command_queue_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller info FIFO is full",
+ "EventCode": "0x1d",
+ "EventName": "k3_ddr.info_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller write latency FIFO is full",
+ "EventCode": "0x1e",
+ "EventName": "k3_ddr.write_latency_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller port command FIFO is full",
+ "EventCode": "0x1f",
+ "EventName": "k3_ddr.port_command_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller write response FIFO is full",
+ "EventCode": "0x20",
+ "EventName": "k3_ddr.write_response_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller port write FIFO is full",
+ "EventCode": "0x21",
+ "EventName": "k3_ddr.port_write_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller core read FIFO is full",
+ "EventCode": "0x22",
+ "EventName": "k3_ddr.core_read_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller port read FIFO is full",
+ "EventCode": "0x23",
+ "EventName": "k3_ddr.port_read_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/ti/am62/sys/metrics.json b/tools/perf/pmu-events/arch/arm64/ti/am62/sys/metrics.json
new file mode 100644
index 0000000000000..6b8431f91eee3
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/ti/am62/sys/metrics.json
@@ -0,0 +1,34 @@
+[
+ {
+ "BriefDescription": "DDR memory read bandwidth in MB/s (16-bit bus, BL16)",
+ "MetricExpr": "(k3_ddr.read * 32) / (duration_time * 1e6)",
+ "MetricGroup": "ddr",
+ "MetricName": "k3_ddr_am62.read_bandwidth_mbytes_sec",
+ "ScaleUnit": "1MB/s",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "DDR memory write bandwidth in MB/s (16-bit bus, BL16)",
+ "MetricExpr": "(k3_ddr.write * 32) / (duration_time * 1e6)",
+ "MetricGroup": "ddr",
+ "MetricName": "k3_ddr_am62.write_bandwidth_mbytes_sec",
+ "ScaleUnit": "1MB/s",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Average DDR read requests per second",
+ "MetricExpr": "k3_ddr.read / duration_time",
+ "MetricGroup": "ddr",
+ "MetricName": "k3_ddr_am62.read_requests_per_sec",
+ "ScaleUnit": "1reads/sec",
+ "Compat": "AM62"
+ },
+ {
+ "BriefDescription": "Average DDR write requests per second",
+ "MetricExpr": "k3_ddr.write / duration_time",
+ "MetricGroup": "ddr",
+ "MetricName": "k3_ddr_am62.write_requests_per_sec",
+ "ScaleUnit": "1writes/sec",
+ "Compat": "AM62"
+ }
+]
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [RFC PATCH 19/22] perf/events: arm64: ti: Add AM62A DDR performance events
2026-07-14 12:56 [RFC PATCH 17/22] perf/events: arm64: ti: Add J7 DDR performance events MANNURU VENKATESWARLU
2026-07-14 12:56 ` [RFC PATCH 18/22] perf/events: arm64: ti: Add AM62 " MANNURU VENKATESWARLU
@ 2026-07-14 12:56 ` MANNURU VENKATESWARLU
2026-07-14 12:56 ` [RFC PATCH 20/22] perf/events: arm64: ti: Add AM62P " MANNURU VENKATESWARLU
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: MANNURU VENKATESWARLU @ 2026-07-14 12:56 UTC (permalink / raw)
To: peterz, mingo, acme
Cc: linux-arm-kernel, linux-perf-users, n-francis, s-k6, bb,
v-mannuru
From: Aarya Chaumal <a-chaumal@ti.com>
Add perf JSON event and metric definitions for the AM62A
DDR controller PMU.
Signed-off-by: MANNURU VENKATESWARLU <v-mannuru@ti.com>
Signed-off-by: Aarya Chaumal <a-chaumal@ti.com>
---
.../arch/arm64/ti/am62a/sys/ddrc.json | 240 ++++++++++++++++++
.../arch/arm64/ti/am62a/sys/metrics.json | 34 +++
2 files changed, 274 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/ti/am62a/sys/ddrc.json
create mode 100644 tools/perf/pmu-events/arch/arm64/ti/am62a/sys/metrics.json
diff --git a/tools/perf/pmu-events/arch/arm64/ti/am62a/sys/ddrc.json b/tools/perf/pmu-events/arch/arm64/ti/am62a/sys/ddrc.json
new file mode 100644
index 0000000000000..0322e3c4a73c4
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/ti/am62a/sys/ddrc.json
@@ -0,0 +1,240 @@
+[
+ {
+ "BriefDescription": "Counts every Write command",
+ "EventCode": "0x00",
+ "EventName": "k3_ddr.write",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every Read command",
+ "EventCode": "0x01",
+ "EventName": "k3_ddr.read",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every read as a result of a RMW command",
+ "EventCode": "0x02",
+ "EventName": "k3_ddr.read_rmw",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every Activate command",
+ "EventCode": "0x03",
+ "EventName": "k3_ddr.activate",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every Precharge command",
+ "EventCode": "0x04",
+ "EventName": "k3_ddr.precharge",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every Precharge All command",
+ "EventCode": "0x05",
+ "EventName": "k3_ddr.precharge_all",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every Mode Register Read command",
+ "EventCode": "0x06",
+ "EventName": "k3_ddr.mode_reg_read",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every Mode Register Write command",
+ "EventCode": "0x07",
+ "EventName": "k3_ddr.mode_reg_write",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every Per Bank Refresh command",
+ "EventCode": "0x08",
+ "EventName": "k3_ddr.per_bank_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every Auto Refresh command",
+ "EventCode": "0x09",
+ "EventName": "k3_ddr.auto_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every ZQ Calib Long command",
+ "EventCode": "0x0a",
+ "EventName": "k3_ddr.zq_calib_long",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every ZQ Calib Short command",
+ "EventCode": "0x0b",
+ "EventName": "k3_ddr.zq_calib_short",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every Write-to-Read and Read-to-Write bus-turn-around",
+ "EventCode": "0x0c",
+ "EventName": "k3_ddr.bus_turn_around",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every Write-to-Write address collision",
+ "EventCode": "0x0d",
+ "EventName": "k3_ddr.write_write_collision",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every Write-to-Read address collision",
+ "EventCode": "0x0e",
+ "EventName": "k3_ddr.write_read_collision",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every Read-to-Write address collision",
+ "EventCode": "0x0f",
+ "EventName": "k3_ddr.read_write_collision",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every Read-to-Read address collision",
+ "EventCode": "0x10",
+ "EventName": "k3_ddr.read_read_collision",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every exit from Power-Down Self-Refresh mode",
+ "EventCode": "0x11",
+ "EventName": "k3_ddr.exit_power_down_self_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every entry into Power-Down Self-Refresh mode",
+ "EventCode": "0x12",
+ "EventName": "k3_ddr.entry_power_down_self_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller stays in Power-Down Self-Refresh mode",
+ "EventCode": "0x13",
+ "EventName": "k3_ddr.power_down_self_refresh_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every exit from Power-Down mode",
+ "EventCode": "0x14",
+ "EventName": "k3_ddr.exit_power_down",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every entry into Power-Down mode",
+ "EventCode": "0x15",
+ "EventName": "k3_ddr.entry_power_down",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller stays in Power-Down mode",
+ "EventCode": "0x16",
+ "EventName": "k3_ddr.power_down_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every exit from Self-Refresh mode",
+ "EventCode": "0x17",
+ "EventName": "k3_ddr.exit_self_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every entry into Self-Refresh mode",
+ "EventCode": "0x18",
+ "EventName": "k3_ddr.entry_self_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller stays in Self-Refresh mode",
+ "EventCode": "0x19",
+ "EventName": "k3_ddr.self_refresh_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller command queue is full",
+ "EventCode": "0x1c",
+ "EventName": "k3_ddr.command_queue_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller info FIFO is full",
+ "EventCode": "0x1d",
+ "EventName": "k3_ddr.info_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller write latency FIFO is full",
+ "EventCode": "0x1e",
+ "EventName": "k3_ddr.write_latency_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller port command FIFO is full",
+ "EventCode": "0x1f",
+ "EventName": "k3_ddr.port_command_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller write response FIFO is full",
+ "EventCode": "0x20",
+ "EventName": "k3_ddr.write_response_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller port write FIFO is full",
+ "EventCode": "0x21",
+ "EventName": "k3_ddr.port_write_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller core read FIFO is full",
+ "EventCode": "0x22",
+ "EventName": "k3_ddr.core_read_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller port read FIFO is full",
+ "EventCode": "0x23",
+ "EventName": "k3_ddr.port_read_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62A"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/ti/am62a/sys/metrics.json b/tools/perf/pmu-events/arch/arm64/ti/am62a/sys/metrics.json
new file mode 100644
index 0000000000000..51f4c8a690828
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/ti/am62a/sys/metrics.json
@@ -0,0 +1,34 @@
+[
+ {
+ "BriefDescription": "DDR memory read bandwidth in MB/s (32-bit bus, BL16)",
+ "MetricExpr": "(k3_ddr.read * 64) / (duration_time * 1e6)",
+ "MetricGroup": "ddr",
+ "MetricName": "k3_ddr_am62a.read_bandwidth_mbytes_sec",
+ "ScaleUnit": "1MB/s",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "DDR memory write bandwidth in MB/s (32-bit bus, BL16)",
+ "MetricExpr": "(k3_ddr.write * 64) / (duration_time * 1e6)",
+ "MetricGroup": "ddr",
+ "MetricName": "k3_ddr_am62a.write_bandwidth_mbytes_sec",
+ "ScaleUnit": "1MB/s",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Average DDR read requests per second",
+ "MetricExpr": "k3_ddr.read / duration_time",
+ "MetricGroup": "ddr",
+ "MetricName": "k3_ddr_am62a.read_requests_per_sec",
+ "ScaleUnit": "1reads/sec",
+ "Compat": "AM62A"
+ },
+ {
+ "BriefDescription": "Average DDR write requests per second",
+ "MetricExpr": "k3_ddr.write / duration_time",
+ "MetricGroup": "ddr",
+ "MetricName": "k3_ddr_am62a.write_requests_per_sec",
+ "ScaleUnit": "1writes/sec",
+ "Compat": "AM62A"
+ }
+]
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [RFC PATCH 20/22] perf/events: arm64: ti: Add AM62P DDR performance events
2026-07-14 12:56 [RFC PATCH 17/22] perf/events: arm64: ti: Add J7 DDR performance events MANNURU VENKATESWARLU
2026-07-14 12:56 ` [RFC PATCH 18/22] perf/events: arm64: ti: Add AM62 " MANNURU VENKATESWARLU
2026-07-14 12:56 ` [RFC PATCH 19/22] perf/events: arm64: ti: Add AM62A " MANNURU VENKATESWARLU
@ 2026-07-14 12:56 ` MANNURU VENKATESWARLU
2026-07-14 12:56 ` [RFC PATCH 21/22] perf/events: arm64: ti: Add AM64 " MANNURU VENKATESWARLU
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: MANNURU VENKATESWARLU @ 2026-07-14 12:56 UTC (permalink / raw)
To: peterz, mingo, acme
Cc: linux-arm-kernel, linux-perf-users, n-francis, s-k6, bb,
v-mannuru
From: Aarya Chaumal <a-chaumal@ti.com>
Add perf JSON event and metric definitions for the AM62P
DDR controller PMU.
Signed-off-by: MANNURU VENKATESWARLU <v-mannuru@ti.com>
Signed-off-by: Aarya Chaumal <a-chaumal@ti.com>
---
.../arch/arm64/ti/am62p/sys/ddrc.json | 240 ++++++++++++++++++
.../arch/arm64/ti/am62p/sys/metrics.json | 34 +++
2 files changed, 274 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/ti/am62p/sys/ddrc.json
create mode 100644 tools/perf/pmu-events/arch/arm64/ti/am62p/sys/metrics.json
diff --git a/tools/perf/pmu-events/arch/arm64/ti/am62p/sys/ddrc.json b/tools/perf/pmu-events/arch/arm64/ti/am62p/sys/ddrc.json
new file mode 100644
index 0000000000000..72ff307d6bcfb
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/ti/am62p/sys/ddrc.json
@@ -0,0 +1,240 @@
+[
+ {
+ "BriefDescription": "Counts every Write command",
+ "EventCode": "0x00",
+ "EventName": "k3_ddr.write",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every Read command",
+ "EventCode": "0x01",
+ "EventName": "k3_ddr.read",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every read as a result of a RMW command",
+ "EventCode": "0x02",
+ "EventName": "k3_ddr.read_rmw",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every Activate command",
+ "EventCode": "0x03",
+ "EventName": "k3_ddr.activate",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every Precharge command",
+ "EventCode": "0x04",
+ "EventName": "k3_ddr.precharge",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every Precharge All command",
+ "EventCode": "0x05",
+ "EventName": "k3_ddr.precharge_all",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every Mode Register Read command",
+ "EventCode": "0x06",
+ "EventName": "k3_ddr.mode_reg_read",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every Mode Register Write command",
+ "EventCode": "0x07",
+ "EventName": "k3_ddr.mode_reg_write",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every Per Bank Refresh command",
+ "EventCode": "0x08",
+ "EventName": "k3_ddr.per_bank_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every Auto Refresh command",
+ "EventCode": "0x09",
+ "EventName": "k3_ddr.auto_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every ZQ Calib Long command",
+ "EventCode": "0x0a",
+ "EventName": "k3_ddr.zq_calib_long",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every ZQ Calib Short command",
+ "EventCode": "0x0b",
+ "EventName": "k3_ddr.zq_calib_short",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every Write-to-Read and Read-to-Write bus-turn-around",
+ "EventCode": "0x0c",
+ "EventName": "k3_ddr.bus_turn_around",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every Write-to-Write address collision",
+ "EventCode": "0x0d",
+ "EventName": "k3_ddr.write_write_collision",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every Write-to-Read address collision",
+ "EventCode": "0x0e",
+ "EventName": "k3_ddr.write_read_collision",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every Read-to-Write address collision",
+ "EventCode": "0x0f",
+ "EventName": "k3_ddr.read_write_collision",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every Read-to-Read address collision",
+ "EventCode": "0x10",
+ "EventName": "k3_ddr.read_read_collision",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every exit from Power-Down Self-Refresh mode",
+ "EventCode": "0x11",
+ "EventName": "k3_ddr.exit_power_down_self_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every entry into Power-Down Self-Refresh mode",
+ "EventCode": "0x12",
+ "EventName": "k3_ddr.entry_power_down_self_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller stays in Power-Down Self-Refresh mode",
+ "EventCode": "0x13",
+ "EventName": "k3_ddr.power_down_self_refresh_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every exit from Power-Down mode",
+ "EventCode": "0x14",
+ "EventName": "k3_ddr.exit_power_down",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every entry into Power-Down mode",
+ "EventCode": "0x15",
+ "EventName": "k3_ddr.entry_power_down",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller stays in Power-Down mode",
+ "EventCode": "0x16",
+ "EventName": "k3_ddr.power_down_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every exit from Self-Refresh mode",
+ "EventCode": "0x17",
+ "EventName": "k3_ddr.exit_self_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every entry into Self-Refresh mode",
+ "EventCode": "0x18",
+ "EventName": "k3_ddr.entry_self_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller stays in Self-Refresh mode",
+ "EventCode": "0x19",
+ "EventName": "k3_ddr.self_refresh_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller command queue is full",
+ "EventCode": "0x1c",
+ "EventName": "k3_ddr.command_queue_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller info FIFO is full",
+ "EventCode": "0x1d",
+ "EventName": "k3_ddr.info_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller write latency FIFO is full",
+ "EventCode": "0x1e",
+ "EventName": "k3_ddr.write_latency_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller port command FIFO is full",
+ "EventCode": "0x1f",
+ "EventName": "k3_ddr.port_command_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller write response FIFO is full",
+ "EventCode": "0x20",
+ "EventName": "k3_ddr.write_response_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller port write FIFO is full",
+ "EventCode": "0x21",
+ "EventName": "k3_ddr.port_write_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller core read FIFO is full",
+ "EventCode": "0x22",
+ "EventName": "k3_ddr.core_read_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller port read FIFO is full",
+ "EventCode": "0x23",
+ "EventName": "k3_ddr.port_read_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM62P"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/ti/am62p/sys/metrics.json b/tools/perf/pmu-events/arch/arm64/ti/am62p/sys/metrics.json
new file mode 100644
index 0000000000000..777d1a013632e
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/ti/am62p/sys/metrics.json
@@ -0,0 +1,34 @@
+[
+ {
+ "BriefDescription": "DDR memory read bandwidth in MB/s (32-bit bus, BL16)",
+ "MetricExpr": "(k3_ddr.read * 64) / (duration_time * 1e6)",
+ "MetricGroup": "ddr",
+ "MetricName": "k3_ddr_am62p.read_bandwidth_mbytes_sec",
+ "ScaleUnit": "1MB/s",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "DDR memory write bandwidth in MB/s (32-bit bus, BL16)",
+ "MetricExpr": "(k3_ddr.write * 64) / (duration_time * 1e6)",
+ "MetricGroup": "ddr",
+ "MetricName": "k3_ddr_am62p.write_bandwidth_mbytes_sec",
+ "ScaleUnit": "1MB/s",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Average DDR read requests per second",
+ "MetricExpr": "k3_ddr.read / duration_time",
+ "MetricGroup": "ddr",
+ "MetricName": "k3_ddr_am62p.read_requests_per_sec",
+ "ScaleUnit": "1reads/sec",
+ "Compat": "AM62P"
+ },
+ {
+ "BriefDescription": "Average DDR write requests per second",
+ "MetricExpr": "k3_ddr.write / duration_time",
+ "MetricGroup": "ddr",
+ "MetricName": "k3_ddr_am62p.write_requests_per_sec",
+ "ScaleUnit": "1writes/sec",
+ "Compat": "AM62P"
+ }
+]
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [RFC PATCH 21/22] perf/events: arm64: ti: Add AM64 DDR performance events
2026-07-14 12:56 [RFC PATCH 17/22] perf/events: arm64: ti: Add J7 DDR performance events MANNURU VENKATESWARLU
` (2 preceding siblings ...)
2026-07-14 12:56 ` [RFC PATCH 20/22] perf/events: arm64: ti: Add AM62P " MANNURU VENKATESWARLU
@ 2026-07-14 12:56 ` MANNURU VENKATESWARLU
2026-07-14 12:56 ` [RFC PATCH 22/22] tools/perf: jevents: Add k3_ddr to JSON unit table MANNURU VENKATESWARLU
2026-09-10 14:14 ` [RFC PATCH 17/22] perf/events: arm64: ti: Add J7 DDR performance events Arnaldo Carvalho de Melo
5 siblings, 0 replies; 7+ messages in thread
From: MANNURU VENKATESWARLU @ 2026-07-14 12:56 UTC (permalink / raw)
To: peterz, mingo, acme
Cc: linux-arm-kernel, linux-perf-users, n-francis, s-k6, bb,
v-mannuru
From: Aarya Chaumal <a-chaumal@ti.com>
Add perf JSON event and metric definitions for the AM64
DDR controller PMU.
Signed-off-by: MANNURU VENKATESWARLU <v-mannuru@ti.com>
Signed-off-by: Aarya Chaumal <a-chaumal@ti.com>
---
.../arch/arm64/ti/am64/sys/ddrc.json | 240 ++++++++++++++++++
.../arch/arm64/ti/am64/sys/metrics.json | 34 +++
2 files changed, 274 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/ti/am64/sys/ddrc.json
create mode 100644 tools/perf/pmu-events/arch/arm64/ti/am64/sys/metrics.json
diff --git a/tools/perf/pmu-events/arch/arm64/ti/am64/sys/ddrc.json b/tools/perf/pmu-events/arch/arm64/ti/am64/sys/ddrc.json
new file mode 100644
index 0000000000000..c3498dfa7feeb
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/ti/am64/sys/ddrc.json
@@ -0,0 +1,240 @@
+[
+ {
+ "BriefDescription": "Counts every Write command",
+ "EventCode": "0x00",
+ "EventName": "k3_ddr.write",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every Read command",
+ "EventCode": "0x01",
+ "EventName": "k3_ddr.read",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every read as a result of a RMW command",
+ "EventCode": "0x02",
+ "EventName": "k3_ddr.read_rmw",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every Activate command",
+ "EventCode": "0x03",
+ "EventName": "k3_ddr.activate",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every Precharge command",
+ "EventCode": "0x04",
+ "EventName": "k3_ddr.precharge",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every Precharge All command",
+ "EventCode": "0x05",
+ "EventName": "k3_ddr.precharge_all",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every Mode Register Read command",
+ "EventCode": "0x06",
+ "EventName": "k3_ddr.mode_reg_read",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every Mode Register Write command",
+ "EventCode": "0x07",
+ "EventName": "k3_ddr.mode_reg_write",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every Per Bank Refresh command",
+ "EventCode": "0x08",
+ "EventName": "k3_ddr.per_bank_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every Auto Refresh command",
+ "EventCode": "0x09",
+ "EventName": "k3_ddr.auto_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every ZQ Calib Long command",
+ "EventCode": "0x0a",
+ "EventName": "k3_ddr.zq_calib_long",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every ZQ Calib Short command",
+ "EventCode": "0x0b",
+ "EventName": "k3_ddr.zq_calib_short",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every Write-to-Read and Read-to-Write bus-turn-around",
+ "EventCode": "0x0c",
+ "EventName": "k3_ddr.bus_turn_around",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every Write-to-Write address collision",
+ "EventCode": "0x0d",
+ "EventName": "k3_ddr.write_write_collision",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every Write-to-Read address collision",
+ "EventCode": "0x0e",
+ "EventName": "k3_ddr.write_read_collision",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every Read-to-Write address collision",
+ "EventCode": "0x0f",
+ "EventName": "k3_ddr.read_write_collision",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every Read-to-Read address collision",
+ "EventCode": "0x10",
+ "EventName": "k3_ddr.read_read_collision",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every exit from Power-Down Self-Refresh mode",
+ "EventCode": "0x11",
+ "EventName": "k3_ddr.exit_power_down_self_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every entry into Power-Down Self-Refresh mode",
+ "EventCode": "0x12",
+ "EventName": "k3_ddr.entry_power_down_self_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller stays in Power-Down Self-Refresh mode",
+ "EventCode": "0x13",
+ "EventName": "k3_ddr.power_down_self_refresh_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every exit from Power-Down mode",
+ "EventCode": "0x14",
+ "EventName": "k3_ddr.exit_power_down",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every entry into Power-Down mode",
+ "EventCode": "0x15",
+ "EventName": "k3_ddr.entry_power_down",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller stays in Power-Down mode",
+ "EventCode": "0x16",
+ "EventName": "k3_ddr.power_down_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every exit from Self-Refresh mode",
+ "EventCode": "0x17",
+ "EventName": "k3_ddr.exit_self_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every entry into Self-Refresh mode",
+ "EventCode": "0x18",
+ "EventName": "k3_ddr.entry_self_refresh",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller stays in Self-Refresh mode",
+ "EventCode": "0x19",
+ "EventName": "k3_ddr.self_refresh_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller command queue is full",
+ "EventCode": "0x1c",
+ "EventName": "k3_ddr.command_queue_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller info FIFO is full",
+ "EventCode": "0x1d",
+ "EventName": "k3_ddr.info_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller write latency FIFO is full",
+ "EventCode": "0x1e",
+ "EventName": "k3_ddr.write_latency_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller port command FIFO is full",
+ "EventCode": "0x1f",
+ "EventName": "k3_ddr.port_command_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller write response FIFO is full",
+ "EventCode": "0x20",
+ "EventName": "k3_ddr.write_response_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller port write FIFO is full",
+ "EventCode": "0x21",
+ "EventName": "k3_ddr.port_write_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller core read FIFO is full",
+ "EventCode": "0x22",
+ "EventName": "k3_ddr.core_read_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Counts every cycle for which the DDR Controller port read FIFO is full",
+ "EventCode": "0x23",
+ "EventName": "k3_ddr.port_read_fifo_full_cycles",
+ "Unit": "k3_ddr",
+ "Compat": "AM64"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/ti/am64/sys/metrics.json b/tools/perf/pmu-events/arch/arm64/ti/am64/sys/metrics.json
new file mode 100644
index 0000000000000..1d8982c8f5bba
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/ti/am64/sys/metrics.json
@@ -0,0 +1,34 @@
+[
+ {
+ "BriefDescription": "DDR memory read bandwidth in MB/s (16-bit bus, BL16)",
+ "MetricExpr": "(k3_ddr.read * 32) / (duration_time * 1e6)",
+ "MetricGroup": "ddr",
+ "MetricName": "k3_ddr_am64.read_bandwidth_mbytes_sec",
+ "ScaleUnit": "1MB/s",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "DDR memory write bandwidth in MB/s (16-bit bus, BL16)",
+ "MetricExpr": "(k3_ddr.write * 32) / (duration_time * 1e6)",
+ "MetricGroup": "ddr",
+ "MetricName": "k3_ddr_am64.write_bandwidth_mbytes_sec",
+ "ScaleUnit": "1MB/s",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Average DDR read requests per second",
+ "MetricExpr": "k3_ddr.read / duration_time",
+ "MetricGroup": "ddr",
+ "MetricName": "k3_ddr_am64.read_requests_per_sec",
+ "ScaleUnit": "1reads/sec",
+ "Compat": "AM64"
+ },
+ {
+ "BriefDescription": "Average DDR write requests per second",
+ "MetricExpr": "k3_ddr.write / duration_time",
+ "MetricGroup": "ddr",
+ "MetricName": "k3_ddr_am64.write_requests_per_sec",
+ "ScaleUnit": "1writes/sec",
+ "Compat": "AM64"
+ }
+]
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [RFC PATCH 22/22] tools/perf: jevents: Add k3_ddr to JSON unit table
2026-07-14 12:56 [RFC PATCH 17/22] perf/events: arm64: ti: Add J7 DDR performance events MANNURU VENKATESWARLU
` (3 preceding siblings ...)
2026-07-14 12:56 ` [RFC PATCH 21/22] perf/events: arm64: ti: Add AM64 " MANNURU VENKATESWARLU
@ 2026-07-14 12:56 ` MANNURU VENKATESWARLU
2026-09-10 14:14 ` [RFC PATCH 17/22] perf/events: arm64: ti: Add J7 DDR performance events Arnaldo Carvalho de Melo
5 siblings, 0 replies; 7+ messages in thread
From: MANNURU VENKATESWARLU @ 2026-07-14 12:56 UTC (permalink / raw)
To: peterz, mingo, acme
Cc: linux-arm-kernel, linux-perf-users, n-francis, s-k6, bb,
v-mannuru
From: Aarya Chaumal <a-chaumal@ti.com>
Register k3_ddr as a known PMU unit in the jevents tool so
that the JSON event tables for TI K3 DDR controllers are picked
up correctly during the perf build.
Signed-off-by: MANNURU VENKATESWARLU <v-mannuru@ti.com>
Signed-off-by: Aarya Chaumal <a-chaumal@ti.com>
---
tools/perf/pmu-events/jevents.py | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py
index 376dc2d241621..274461e55c757 100755
--- a/tools/perf/pmu-events/jevents.py
+++ b/tools/perf/pmu-events/jevents.py
@@ -291,6 +291,7 @@ class JsonEvent:
'hisi_sccl,l3c': 'hisi_sccl,l3c',
'imx8_ddr': 'imx8_ddr',
'imx9_ddr': 'imx9_ddr',
+ 'k3_ddr': 'k3_ddr',
'L3PMC': 'amd_l3',
'DFPMC': 'amd_df',
'UMCPMC': 'amd_umc',
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [RFC PATCH 17/22] perf/events: arm64: ti: Add J7 DDR performance events
2026-07-14 12:56 [RFC PATCH 17/22] perf/events: arm64: ti: Add J7 DDR performance events MANNURU VENKATESWARLU
` (4 preceding siblings ...)
2026-07-14 12:56 ` [RFC PATCH 22/22] tools/perf: jevents: Add k3_ddr to JSON unit table MANNURU VENKATESWARLU
@ 2026-09-10 14:14 ` Arnaldo Carvalho de Melo
5 siblings, 0 replies; 7+ messages in thread
From: Arnaldo Carvalho de Melo @ 2026-09-10 14:14 UTC (permalink / raw)
To: MANNURU VENKATESWARLU
Cc: peterz, mingo, linux-arm-kernel, linux-perf-users, n-francis,
s-k6, bb
On Tue, Jul 14, 2026 at 06:26:30PM +0530, MANNURU VENKATESWARLU wrote:
> Add perf JSON event and metric definitions for the J7 family
> DDR controller PMU covering J721E, J721S2, J7200 and J784S4.
Can someone from ARM please take a look at this and provide some
Reviewed-by?
Thanks,
- Arnaldo
> Signed-off-by: MANNURU VENKATESWARLU <v-mannuru@ti.com>
> ---
> .../pmu-events/arch/arm64/ti/j7/sys/ddrc.json | 240 ++++++++++++++++++
> .../arch/arm64/ti/j7/sys/metrics.json | 34 +++
> 2 files changed, 274 insertions(+)
> create mode 100644 tools/perf/pmu-events/arch/arm64/ti/j7/sys/ddrc.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/ti/j7/sys/metrics.json
>
> diff --git a/tools/perf/pmu-events/arch/arm64/ti/j7/sys/ddrc.json b/tools/perf/pmu-events/arch/arm64/ti/j7/sys/ddrc.json
> new file mode 100644
> index 0000000000000..7ed64c25500d4
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/arm64/ti/j7/sys/ddrc.json
> @@ -0,0 +1,240 @@
> +[
> + {
> + "BriefDescription": "Counts every Write command",
> + "EventCode": "0x00",
> + "EventName": "k3_ddr.write",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every Read command",
> + "EventCode": "0x01",
> + "EventName": "k3_ddr.read",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every read as a result of a RMW command",
> + "EventCode": "0x02",
> + "EventName": "k3_ddr.read_rmw",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every Activate command",
> + "EventCode": "0x03",
> + "EventName": "k3_ddr.activate",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every Precharge command",
> + "EventCode": "0x04",
> + "EventName": "k3_ddr.precharge",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every Precharge All command",
> + "EventCode": "0x05",
> + "EventName": "k3_ddr.precharge_all",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every Mode Register Read command",
> + "EventCode": "0x06",
> + "EventName": "k3_ddr.mode_reg_read",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every Mode Register Write command",
> + "EventCode": "0x07",
> + "EventName": "k3_ddr.mode_reg_write",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every Per Bank Refresh command",
> + "EventCode": "0x08",
> + "EventName": "k3_ddr.per_bank_refresh",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every Auto Refresh command",
> + "EventCode": "0x09",
> + "EventName": "k3_ddr.auto_refresh",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every ZQ Calib Long command",
> + "EventCode": "0x0a",
> + "EventName": "k3_ddr.zq_calib_long",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every ZQ Calib Short command",
> + "EventCode": "0x0b",
> + "EventName": "k3_ddr.zq_calib_short",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every Write-to-Read and Read-to-Write bus-turn-around",
> + "EventCode": "0x0c",
> + "EventName": "k3_ddr.bus_turn_around",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every Write-to-Write address collision",
> + "EventCode": "0x0d",
> + "EventName": "k3_ddr.write_write_collision",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every Write-to-Read address collision",
> + "EventCode": "0x0e",
> + "EventName": "k3_ddr.write_read_collision",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every Read-to-Write address collision",
> + "EventCode": "0x0f",
> + "EventName": "k3_ddr.read_write_collision",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every Read-to-Read address collision",
> + "EventCode": "0x10",
> + "EventName": "k3_ddr.read_read_collision",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every exit from Power-Down Self-Refresh mode",
> + "EventCode": "0x11",
> + "EventName": "k3_ddr.exit_power_down_self_refresh",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every entry into Power-Down Self-Refresh mode",
> + "EventCode": "0x12",
> + "EventName": "k3_ddr.entry_power_down_self_refresh",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every cycle for which the DDR Controller stays in Power-Down Self-Refresh mode",
> + "EventCode": "0x13",
> + "EventName": "k3_ddr.power_down_self_refresh_cycles",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every exit from Power-Down mode",
> + "EventCode": "0x14",
> + "EventName": "k3_ddr.exit_power_down",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every entry into Power-Down mode",
> + "EventCode": "0x15",
> + "EventName": "k3_ddr.entry_power_down",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every cycle for which the DDR Controller stays in Power-Down mode",
> + "EventCode": "0x16",
> + "EventName": "k3_ddr.power_down_cycles",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every exit from Self-Refresh mode",
> + "EventCode": "0x17",
> + "EventName": "k3_ddr.exit_self_refresh",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every entry into Self-Refresh mode",
> + "EventCode": "0x18",
> + "EventName": "k3_ddr.entry_self_refresh",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every cycle for which the DDR Controller stays in Self-Refresh mode",
> + "EventCode": "0x19",
> + "EventName": "k3_ddr.self_refresh_cycles",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every cycle for which the DDR Controller command queue is full",
> + "EventCode": "0x1c",
> + "EventName": "k3_ddr.command_queue_full_cycles",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every cycle for which the DDR Controller info FIFO is full",
> + "EventCode": "0x1d",
> + "EventName": "k3_ddr.info_fifo_full_cycles",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every cycle for which the DDR Controller write latency FIFO is full",
> + "EventCode": "0x1e",
> + "EventName": "k3_ddr.write_latency_fifo_full_cycles",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every cycle for which the DDR Controller port command FIFO is full",
> + "EventCode": "0x1f",
> + "EventName": "k3_ddr.port_command_fifo_full_cycles",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every cycle for which the DDR Controller write response FIFO is full",
> + "EventCode": "0x20",
> + "EventName": "k3_ddr.write_response_fifo_full_cycles",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every cycle for which the DDR Controller port write FIFO is full",
> + "EventCode": "0x21",
> + "EventName": "k3_ddr.port_write_fifo_full_cycles",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every cycle for which the DDR Controller core read FIFO is full",
> + "EventCode": "0x22",
> + "EventName": "k3_ddr.core_read_fifo_full_cycles",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Counts every cycle for which the DDR Controller port read FIFO is full",
> + "EventCode": "0x23",
> + "EventName": "k3_ddr.port_read_fifo_full_cycles",
> + "Unit": "k3_ddr",
> + "Compat": "J7"
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/arm64/ti/j7/sys/metrics.json b/tools/perf/pmu-events/arch/arm64/ti/j7/sys/metrics.json
> new file mode 100644
> index 0000000000000..156b2c9dec185
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/arm64/ti/j7/sys/metrics.json
> @@ -0,0 +1,34 @@
> +[
> + {
> + "BriefDescription": "DDR memory read bandwidth in MB/s (32-bit bus, BL16)",
> + "MetricExpr": "(k3_ddr.read * 64) / (duration_time * 1e6)",
> + "MetricGroup": "ddr",
> + "MetricName": "k3_ddr_j7.read_bandwidth_mbytes_sec",
> + "ScaleUnit": "1MB/s",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "DDR memory write bandwidth in MB/s (32-bit bus, BL16)",
> + "MetricExpr": "(k3_ddr.write * 64) / (duration_time * 1e6)",
> + "MetricGroup": "ddr",
> + "MetricName": "k3_ddr_j7.write_bandwidth_mbytes_sec",
> + "ScaleUnit": "1MB/s",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Average DDR read requests per second",
> + "MetricExpr": "k3_ddr.read / duration_time",
> + "MetricGroup": "ddr",
> + "MetricName": "k3_ddr_j7.read_requests_per_sec",
> + "ScaleUnit": "1reads/sec",
> + "Compat": "J7"
> + },
> + {
> + "BriefDescription": "Average DDR write requests per second",
> + "MetricExpr": "k3_ddr.write / duration_time",
> + "MetricGroup": "ddr",
> + "MetricName": "k3_ddr_j7.write_requests_per_sec",
> + "ScaleUnit": "1writes/sec",
> + "Compat": "J7"
> + }
> +]
> --
> 2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread
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2026-07-14 12:56 [RFC PATCH 17/22] perf/events: arm64: ti: Add J7 DDR performance events MANNURU VENKATESWARLU
2026-07-14 12:56 ` [RFC PATCH 18/22] perf/events: arm64: ti: Add AM62 " MANNURU VENKATESWARLU
2026-07-14 12:56 ` [RFC PATCH 19/22] perf/events: arm64: ti: Add AM62A " MANNURU VENKATESWARLU
2026-07-14 12:56 ` [RFC PATCH 20/22] perf/events: arm64: ti: Add AM62P " MANNURU VENKATESWARLU
2026-07-14 12:56 ` [RFC PATCH 21/22] perf/events: arm64: ti: Add AM64 " MANNURU VENKATESWARLU
2026-07-14 12:56 ` [RFC PATCH 22/22] tools/perf: jevents: Add k3_ddr to JSON unit table MANNURU VENKATESWARLU
2026-09-10 14:14 ` [RFC PATCH 17/22] perf/events: arm64: ti: Add J7 DDR performance events Arnaldo Carvalho de Melo
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