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From: Yao Zi <me@ziyao.cc>
To: Nikita Shubin <nikita.shubin@maquefel.me>,
	u-boot@lists.u-boot-project.org
Cc: Yao Zi <me@ziyao.cc>, Tom Rini <trini@konsulko.com>,
	Michal Simek <michal.simek@amd.com>
Subject: Re: [PATCH v2 1/2] riscv: timer: Enable early timer for M‑mode
Date: Thu, 10 Sep 2026 12:23:39 +0000	[thread overview]
Message-ID: <aqKhS6_w0Fqt8vsV@pie> (raw)
In-Reply-To: <20260909-riscv_fix_early_timer_mmode-v2-1-563bff2a50c5@maquefel.me>

Hi Nikita,

Sorry for sending out this review late. My system crashed earlier this
day and I forgot this mail in the draft folder.

On Wed, Sep 09, 2026 at 09:30:59AM +0300, Nikita Shubin wrote:
> The generic RISC-V timer driver currently defines
> timer_early_get_count() only when CONFIG_IS_ENABLED(RISCV_SMODE),
> even though reading the TIME CSR is not inherently limited
> to S‑mode; it works in M‑mode as well when the CSR is implemented
> in hardware (e.g., with the Zicntr extension).
> 
> Moreover, timer_early_get_rate() is missing entirely for M‑mode,
> causing early timer functions to be unavailable on such systems.
> 
> Fix this by:
> - Moving timer_early_get_count() out of the RISCV_SMODE guard
>   so it is always available when CONFIG_TIMER_EARLY is set.
> - Adding M‑mode support to timer_early_get_rate(), returning
>   RISCV_MMODE_TIMER_FREQ when running in M‑mode
>   and RISCV_SMODE_TIMER_FREQ   in S‑mode.
> 
> This is also necessary because several functions
> (e.g., net_random_ethaddr() via get_ticks()) rely on
> timer_early_get_count() even if CONFIG_TIMER_EARLY is not
> enabled.
> 
> Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me>
> ---
>  drivers/timer/Kconfig       | 13 +++++++++++--
>  drivers/timer/riscv_timer.c | 12 +++++++++---
>  2 files changed, 20 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
> index 500a25638a9..12c194ff74a 100644
> --- a/drivers/timer/Kconfig
> +++ b/drivers/timer/Kconfig
> @@ -227,8 +227,17 @@ config RISCV_TIMER
>  	bool "RISC-V timer support"
>  	depends on TIMER && RISCV
>  	help
> -	  Select this to enable support for a generic RISC-V S-Mode timer
> -	  driver.
> +	  Enable support for the generic RISC-V timer driver using the TIME CSR.
> +
> +	  This driver works in S-mode and also in M-mode if the TIME CSR is
> +	  implemented in hardware (e.g., when the Zicntr extension is present).
> +	  In M-mode, the timer frequency must be provided via the macro
> +	  RISCV_MMODE_TIMER_FREQ; in S-mode, use RISCV_SMODE_TIMER_FREQ.

This doesn't seem correct. These two constants are only used for the
early timer implementation, and the non-early one looks up the rate from
FDT blob (/cpus/timebase-frequency).

> +	  On platforms that also enable CLINT/ACLINT MTIMER, both drivers
> +	  may provide early timer functions and cause linking conflicts. Ensure
> +	  that only one of them is selected, or adjust the configuration to avoid
> +	  duplicate symbols.

Won't this issue fixed by PATCH 2? And I think this paragraph is too
detailed to be included in the Kconfig help.

Regards,
Yao Zi

  reply	other threads:[~2026-09-10 12:23 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-09  6:30 [PATCH v2 0/2] riscv: timer: Fix M-mode early timer support Nikita Shubin
2026-09-09  6:30 ` [PATCH v2 1/2] riscv: timer: Enable early timer for M‑mode Nikita Shubin
2026-09-10 12:23   ` Yao Zi [this message]
2026-09-10 13:15     ` Nikita Shubin
2026-09-09  6:31 ` [PATCH v2 2/2] riscv: timer: Make RISCV_TIMER definitions weak Nikita Shubin
2026-09-10  4:13   ` Yao Zi
2026-09-10  5:03     ` Nikita Shubin

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