[PATCH v2 0/2] riscv: timer: Fix M-mode early timer support

[PATCH v2 0/2] riscv: timer: Fix M-mode early timer support

[Nikita Shubin]

This series addresses two issues with the generic RISC-V timer driver.

Patch 1 adds proper M‑mode support: timer_early_get_rate() is now defined
for M‑mode using RISCV_MMODE_TIMER_FREQ, and timer_early_get_count() is
no longer guarded by RISCV_SMODE, making it available whenever
CONFIG_TIMER_EARLY is enabled. This is necessary because functions like
net_random_ethaddr() rely on get_ticks() which uses timer_early_get_count().

Patch 2 marks timer_early_get_rate() and timer_early_get_count() as __weak
to prevent link conflicts with other drivers (e.g., ACLINT MTIMER) that may
also provide their own implementation.

Changes in v2:
- Updated Kconfig help text and driver comments to clarify M-mode support
- Simplified code a bit
- Added patch to make RISCV_TIMER definitions weak

Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me>
---
Changes in v2:
- Updated Kconfig help text and driver comments to clarify M-mode support
- Simplified code a bit
- Add patch to make timer_early_get_count() weak (optional)

- Link to v1: https://lore.kernel.org/r/20260904-riscv_fix_early_timer_mmode-v1-1-210e769b0ac2@maquefel.me

---
Nikita Shubin (2):
      riscv: timer: Enable early timer for M‑mode
      riscv: timer: Make RISCV_TIMER definitions weak

 drivers/timer/Kconfig       | 13 +++++++++++--
 drivers/timer/riscv_timer.c | 16 +++++++++++-----
 2 files changed, 22 insertions(+), 7 deletions(-)
---
base-commit: cc557af4553382f6f50e3ed62b9577054e7bc54f
change-id: 20260904-riscv_fix_early_timer_mmode-174f3ee4e106

Best regards,
-- 
Nikita Shubin

[PATCH v2 1/2] riscv: timer: Enable early timer for M‑mode

[Nikita Shubin]

The generic RISC-V timer driver currently defines
timer_early_get_count() only when CONFIG_IS_ENABLED(RISCV_SMODE),
even though reading the TIME CSR is not inherently limited
to S‑mode; it works in M‑mode as well when the CSR is implemented
in hardware (e.g., with the Zicntr extension).

Moreover, timer_early_get_rate() is missing entirely for M‑mode,
causing early timer functions to be unavailable on such systems.

Fix this by:
- Moving timer_early_get_count() out of the RISCV_SMODE guard
  so it is always available when CONFIG_TIMER_EARLY is set.
- Adding M‑mode support to timer_early_get_rate(), returning
  RISCV_MMODE_TIMER_FREQ when running in M‑mode
  and RISCV_SMODE_TIMER_FREQ   in S‑mode.

This is also necessary because several functions
(e.g., net_random_ethaddr() via get_ticks()) rely on
timer_early_get_count() even if CONFIG_TIMER_EARLY is not
enabled.

Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me>
---
 drivers/timer/Kconfig       | 13 +++++++++++--
 drivers/timer/riscv_timer.c | 12 +++++++++---
 2 files changed, 20 insertions(+), 5 deletions(-)

diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 500a25638a9..12c194ff74a 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -227,8 +227,17 @@ config RISCV_TIMER
 	bool "RISC-V timer support"
 	depends on TIMER && RISCV
 	help
-	  Select this to enable support for a generic RISC-V S-Mode timer
-	  driver.
+	  Enable support for the generic RISC-V timer driver using the TIME CSR.
+
+	  This driver works in S-mode and also in M-mode if the TIME CSR is
+	  implemented in hardware (e.g., when the Zicntr extension is present).
+	  In M-mode, the timer frequency must be provided via the macro
+	  RISCV_MMODE_TIMER_FREQ; in S-mode, use RISCV_SMODE_TIMER_FREQ.
+
+	  On platforms that also enable CLINT/ACLINT MTIMER, both drivers
+	  may provide early timer functions and cause linking conflicts. Ensure
+	  that only one of them is selected, or adjust the configuration to avoid
+	  duplicate symbols.
 
 config ROCKCHIP_TIMER
 	bool "Rockchip timer support"
diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index 1f4980ceb38..c2e617317aa 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c
@@ -7,7 +7,9 @@
  *
  * RISC-V architecturally-defined generic timer driver
  *
- * This driver provides generic timer support for S-mode U-Boot.
+ * This driver provides generic timer support for S-mode
+ * and M-Mode U-Boot if the TIME CSR is implemented in hardware
+ * (e.g., when the Zicntr extension is present).
  */
 
 #include <config.h>
@@ -33,14 +35,19 @@ static u64 notrace riscv_timer_get_count(struct udevice *dev)
 	return ((u64)hi << 32) | lo;
 }
 
-#if CONFIG_IS_ENABLED(RISCV_SMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
 /**
  * timer_early_get_rate() - Get the timer rate before driver model
  */
+#if IS_ENABLED(CONFIG_TIMER_EARLY)
 unsigned long notrace timer_early_get_rate(void)
 {
+#if CONFIG_IS_ENABLED(RISCV_SMODE)
 	return RISCV_SMODE_TIMER_FREQ;
+#elif CONFIG_IS_ENABLED(RISCV_MMODE)
+	return RISCV_MMODE_TIMER_FREQ;
+#endif
 }
+#endif
 
 /**
  * timer_early_get_count() - Get the timer count before driver model
@@ -50,7 +57,6 @@ u64 notrace timer_early_get_count(void)
 {
 	return riscv_timer_get_count(NULL);
 }
-#endif
 
 #if CONFIG_IS_ENABLED(RISCV_SMODE) && CONFIG_IS_ENABLED(BOOTSTAGE)
 ulong timer_get_boot_us(void)

-- 
2.54.0

[PATCH v2 2/2] riscv: timer: Make RISCV_TIMER definitions weak

[Nikita Shubin]

Mark timer_early_get_rate() and timer_early_get_count()
as __weak to avoid link conflict with other drivers
(e.g., ACLINT MTIMER) that also provide this function
when both are enabled.

Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me>
---
 drivers/timer/riscv_timer.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index c2e617317aa..58878445e4c 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c
@@ -39,7 +39,7 @@ static u64 notrace riscv_timer_get_count(struct udevice *dev)
  * timer_early_get_rate() - Get the timer rate before driver model
  */
 #if IS_ENABLED(CONFIG_TIMER_EARLY)
-unsigned long notrace timer_early_get_rate(void)
+unsigned long notrace __weak timer_early_get_rate(void)
 {
 #if CONFIG_IS_ENABLED(RISCV_SMODE)
 	return RISCV_SMODE_TIMER_FREQ;
@@ -53,7 +53,7 @@ unsigned long notrace timer_early_get_rate(void)
  * timer_early_get_count() - Get the timer count before driver model
  *
  */
-u64 notrace timer_early_get_count(void)
+u64 notrace __weak timer_early_get_count(void)
 {
 	return riscv_timer_get_count(NULL);
 }

-- 
2.54.0

Re: [PATCH v2 2/2] riscv: timer: Make RISCV_TIMER definitions weak

[Yao Zi]

On Wed, Sep 09, 2026 at 09:31:00AM +0300, Nikita Shubin wrote:
> Mark timer_early_get_rate() and timer_early_get_count()
> as __weak to avoid link conflict with other drivers
> (e.g., ACLINT MTIMER) that also provide this function
> when both are enabled.

So with only the first patch applied, building of
starfive_visionfive2_defconfig is still broken, isn't it? IOW this
breaks bisectability and should be avoided.

Best regards,
Yao Zi

Re: [PATCH v2 2/2] riscv: timer: Make RISCV_TIMER definitions weak

[Nikita Shubin]

Hi Yao Zi.

On Thu, 2026-09-10 at 04:13 +0000, Yao Zi wrote:
> On Wed, Sep 09, 2026 at 09:31:00AM +0300, Nikita Shubin wrote:
> > Mark timer_early_get_rate() and timer_early_get_count()
> > as __weak to avoid link conflict with other drivers
> > (e.g., ACLINT MTIMER) that also provide this function
> > when both are enabled.
> 
> So with only the first patch applied, building of
> starfive_visionfive2_defconfig is still broken, isn't it? IOW this
> breaks bisectability and should be avoided.

Indeed, sorry about that. Will be fixed.

> 
> Best regards,
> Yao Zi

Re: [PATCH v2 1/2] riscv: timer: Enable early timer for M‑mode

[Yao Zi]

Hi Nikita,

Sorry for sending out this review late. My system crashed earlier this
day and I forgot this mail in the draft folder.

On Wed, Sep 09, 2026 at 09:30:59AM +0300, Nikita Shubin wrote:
> The generic RISC-V timer driver currently defines
> timer_early_get_count() only when CONFIG_IS_ENABLED(RISCV_SMODE),
> even though reading the TIME CSR is not inherently limited
> to S‑mode; it works in M‑mode as well when the CSR is implemented
> in hardware (e.g., with the Zicntr extension).
> 
> Moreover, timer_early_get_rate() is missing entirely for M‑mode,
> causing early timer functions to be unavailable on such systems.
> 
> Fix this by:
> - Moving timer_early_get_count() out of the RISCV_SMODE guard
>   so it is always available when CONFIG_TIMER_EARLY is set.
> - Adding M‑mode support to timer_early_get_rate(), returning
>   RISCV_MMODE_TIMER_FREQ when running in M‑mode
>   and RISCV_SMODE_TIMER_FREQ   in S‑mode.
> 
> This is also necessary because several functions
> (e.g., net_random_ethaddr() via get_ticks()) rely on
> timer_early_get_count() even if CONFIG_TIMER_EARLY is not
> enabled.
> 
> Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me>
> ---
>  drivers/timer/Kconfig       | 13 +++++++++++--
>  drivers/timer/riscv_timer.c | 12 +++++++++---
>  2 files changed, 20 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
> index 500a25638a9..12c194ff74a 100644
> --- a/drivers/timer/Kconfig
> +++ b/drivers/timer/Kconfig
> @@ -227,8 +227,17 @@ config RISCV_TIMER
>  	bool "RISC-V timer support"
>  	depends on TIMER && RISCV
>  	help
> -	  Select this to enable support for a generic RISC-V S-Mode timer
> -	  driver.
> +	  Enable support for the generic RISC-V timer driver using the TIME CSR.
> +
> +	  This driver works in S-mode and also in M-mode if the TIME CSR is
> +	  implemented in hardware (e.g., when the Zicntr extension is present).
> +	  In M-mode, the timer frequency must be provided via the macro
> +	  RISCV_MMODE_TIMER_FREQ; in S-mode, use RISCV_SMODE_TIMER_FREQ.

This doesn't seem correct. These two constants are only used for the
early timer implementation, and the non-early one looks up the rate from
FDT blob (/cpus/timebase-frequency).

> +	  On platforms that also enable CLINT/ACLINT MTIMER, both drivers
> +	  may provide early timer functions and cause linking conflicts. Ensure
> +	  that only one of them is selected, or adjust the configuration to avoid
> +	  duplicate symbols.

Won't this issue fixed by PATCH 2? And I think this paragraph is too
detailed to be included in the Kconfig help.

Regards,
Yao Zi

Re: [PATCH v2 1/2] riscv: timer: Enable early timer for M‑mode

[Nikita Shubin]

Hi Yao Zi.

On Thu, 2026-09-10 at 12:23 +0000, Yao Zi wrote:
> Hi Nikita,
> 
> Sorry for sending out this review late. My system crashed earlier
> this
> day and I forgot this mail in the draft folder.

No problem, all comments have been taken into account and will be
corrected.

> 
> On Wed, Sep 09, 2026 at 09:30:59AM +0300, Nikita Shubin wrote:
> > The generic RISC-V timer driver currently defines
> > timer_early_get_count() only when CONFIG_IS_ENABLED(RISCV_SMODE),
> > even though reading the TIME CSR is not inherently limited
> > to S‑mode; it works in M‑mode as well when the CSR is implemented
> > in hardware (e.g., with the Zicntr extension).
> > 
> > Moreover, timer_early_get_rate() is missing entirely for M‑mode,
> > causing early timer functions to be unavailable on such systems.
> > 
> > Fix this by:
> > - Moving timer_early_get_count() out of the RISCV_SMODE guard
> >   so it is always available when CONFIG_TIMER_EARLY is set.
> > - Adding M‑mode support to timer_early_get_rate(), returning
> >   RISCV_MMODE_TIMER_FREQ when running in M‑mode
> >   and RISCV_SMODE_TIMER_FREQ   in S‑mode.
> > 
> > This is also necessary because several functions
> > (e.g., net_random_ethaddr() via get_ticks()) rely on
> > timer_early_get_count() even if CONFIG_TIMER_EARLY is not
> > enabled.
> > 
> > Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me>
> > ---
> >  drivers/timer/Kconfig       | 13 +++++++++++--
> >  drivers/timer/riscv_timer.c | 12 +++++++++---
> >  2 files changed, 20 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
> > index 500a25638a9..12c194ff74a 100644
> > --- a/drivers/timer/Kconfig
> > +++ b/drivers/timer/Kconfig
> > @@ -227,8 +227,17 @@ config RISCV_TIMER
> >  	bool "RISC-V timer support"
> >  	depends on TIMER && RISCV
> >  	help
> > -	  Select this to enable support for a generic RISC-V S-
> > Mode timer
> > -	  driver.
> > +	  Enable support for the generic RISC-V timer driver using
> > the TIME CSR.
> > +
> > +	  This driver works in S-mode and also in M-mode if the
> > TIME CSR is
> > +	  implemented in hardware (e.g., when the Zicntr extension
> > is present).
> > +	  In M-mode, the timer frequency must be provided via the
> > macro
> > +	  RISCV_MMODE_TIMER_FREQ; in S-mode, use
> > RISCV_SMODE_TIMER_FREQ.
> 
> This doesn't seem correct. These two constants are only used for the
> early timer implementation, and the non-early one looks up the rate
> from
> FDT blob (/cpus/timebase-frequency).
> 
> > +	  On platforms that also enable CLINT/ACLINT MTIMER, both
> > drivers
> > +	  may provide early timer functions and cause linking
> > conflicts. Ensure
> > +	  that only one of them is selected, or adjust the
> > configuration to avoid
> > +	  duplicate symbols.
> 
> Won't this issue fixed by PATCH 2? And I think this paragraph is too
> detailed to be included in the Kconfig help.
> 
> Regards,
> Yao Zi