[PATCH v4 0/2] riscv: timer: Fix M-mode early timer support

[PATCH v4 0/2] riscv: timer: Fix M-mode early timer support

[Nikita Shubin]

This series addresses two issues with the generic RISC-V timer driver.

Patch 1 marks timer_early_get_rate() and timer_early_get_count() as __weak
to prevent link conflicts with other drivers (e.g., ACLINT MTIMER) that may
also provide their own implementation.

Patch 2 adds proper M‑mode support: timer_early_get_rate() is now defined
for M‑mode using RISCV_MMODE_TIMER_FREQ, and timer_early_get_count() is
no longer guarded by RISCV_SMODE, making it available whenever
CONFIG_TIMER_EARLY is enabled. This is necessary because functions like
net_random_ethaddr() rely on get_ticks() which uses timer_early_get_count().

Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me>
---
Changes in v4:
- Change KConfig description for RISCV_TIMER: drop ACLINT warning as we
  define funcs as weak, rephrase note about macros and make int make it
  more compact.

- Link to v3: https://lore.kernel.org/r/20260910-riscv_fix_early_timer_mmode-v3-0-52b569fa1d6d@maquefel.me

Changes in v3:
- reoder patches so weak definitions come first

- Link to v2: https://lore.kernel.org/r/20260909-riscv_fix_early_timer_mmode-v2-0-563bff2a50c5@maquefel.me

Changes in v2:
- Updated Kconfig help text and driver comments to clarify M-mode support
- Simplified code a bit
- Add patch to make timer_early_get_count() weak (optional)

- Link to v1: https://lore.kernel.org/r/20260904-riscv_fix_early_timer_mmode-v1-1-210e769b0ac2@maquefel.me

---
Nikita Shubin (2):
      riscv: timer: Make RISCV_TIMER definitions weak
      riscv: timer: Enable early timer for M‑mode

 drivers/timer/Kconfig       |  9 +++++++--
 drivers/timer/riscv_timer.c | 16 +++++++++++-----
 2 files changed, 18 insertions(+), 7 deletions(-)
---
base-commit: cc557af4553382f6f50e3ed62b9577054e7bc54f
change-id: 20260904-riscv_fix_early_timer_mmode-174f3ee4e106

Best regards,
-- 
Nikita Shubin

[PATCH v4 1/2] riscv: timer: Make RISCV_TIMER definitions weak

[Nikita Shubin]

Mark timer_early_get_rate() and timer_early_get_count()
as __weak to avoid link conflict with other drivers
(e.g., ACLINT MTIMER) that also provide this function
when both are enabled.

Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me>
---
 drivers/timer/riscv_timer.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index 1f4980ceb38..eb7c78c3bdd 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c
@@ -37,7 +37,7 @@ static u64 notrace riscv_timer_get_count(struct udevice *dev)
 /**
  * timer_early_get_rate() - Get the timer rate before driver model
  */
-unsigned long notrace timer_early_get_rate(void)
+unsigned long notrace __weak timer_early_get_rate(void)
 {
 	return RISCV_SMODE_TIMER_FREQ;
 }
@@ -46,7 +46,7 @@ unsigned long notrace timer_early_get_rate(void)
  * timer_early_get_count() - Get the timer count before driver model
  *
  */
-u64 notrace timer_early_get_count(void)
+u64 notrace __weak timer_early_get_count(void)
 {
 	return riscv_timer_get_count(NULL);
 }

-- 
2.54.0

[PATCH v4 2/2] riscv: timer: Enable early timer for M‑mode

[Nikita Shubin]

The generic RISC-V timer driver currently defines
timer_early_get_count() only when CONFIG_IS_ENABLED(RISCV_SMODE),
even though reading the TIME CSR is not inherently limited
to S‑mode; it works in M‑mode as well when the CSR is implemented
in hardware (e.g., with the Zicntr extension).

Moreover, timer_early_get_rate() is missing entirely for M‑mode,
causing early timer functions to be unavailable on such systems.

Fix this by:
- Moving timer_early_get_count() out of the RISCV_SMODE guard
  so it is always available when CONFIG_TIMER_EARLY is set.
- Adding M‑mode support to timer_early_get_rate(), returning
  RISCV_MMODE_TIMER_FREQ when running in M‑mode
  and RISCV_SMODE_TIMER_FREQ in S‑mode.

This is also necessary because several functions
(e.g., net_random_ethaddr() via get_ticks()) rely on
timer_early_get_count() even if CONFIG_TIMER_EARLY is not
enabled.

Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me>
---
 drivers/timer/Kconfig       |  9 +++++++--
 drivers/timer/riscv_timer.c | 12 +++++++++---
 2 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 500a25638a9..2b912302053 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -227,8 +227,13 @@ config RISCV_TIMER
 	bool "RISC-V timer support"
 	depends on TIMER && RISCV
 	help
-	  Select this to enable support for a generic RISC-V S-Mode timer
-	  driver.
+	  Enable support for the generic RISC-V timer driver using the TIME CSR.
+
+	  This driver works in S-Mode and M-Mode if the TIME CSR is implemented
+	  in hardware (e.g., when the Zicntr extension is present).
+	  If CONFIG_TIMER_EARLY is also set, then timer frequency must be provided
+	  via the macros RISCV_SMODE_TIMER_FREQ/RISCV_MMODE_TIMER_FREQ for
+	  S-Mode/M-Mode respectively.
 
 config ROCKCHIP_TIMER
 	bool "Rockchip timer support"
diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index eb7c78c3bdd..72cfde57e93 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c
@@ -7,7 +7,9 @@
  *
  * RISC-V architecturally-defined generic timer driver
  *
- * This driver provides generic timer support for S-mode U-Boot.
+ * This driver provides generic timer support for S-mode
+ * and M-Mode U-Boot if the TIME CSR is implemented in hardware
+ * (e.g., when the Zicntr extension is present).
  */
 
 #include <config.h>
@@ -33,14 +35,19 @@ static u64 notrace riscv_timer_get_count(struct udevice *dev)
 	return ((u64)hi << 32) | lo;
 }
 
-#if CONFIG_IS_ENABLED(RISCV_SMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
+#if IS_ENABLED(CONFIG_TIMER_EARLY)
 /**
  * timer_early_get_rate() - Get the timer rate before driver model
  */
 unsigned long notrace __weak timer_early_get_rate(void)
 {
+#if CONFIG_IS_ENABLED(RISCV_SMODE)
 	return RISCV_SMODE_TIMER_FREQ;
+#elif CONFIG_IS_ENABLED(RISCV_MMODE)
+	return RISCV_MMODE_TIMER_FREQ;
+#endif
 }
+#endif
 
 /**
  * timer_early_get_count() - Get the timer count before driver model
@@ -50,7 +57,6 @@ u64 notrace __weak timer_early_get_count(void)
 {
 	return riscv_timer_get_count(NULL);
 }
-#endif
 
 #if CONFIG_IS_ENABLED(RISCV_SMODE) && CONFIG_IS_ENABLED(BOOTSTAGE)
 ulong timer_get_boot_us(void)

-- 
2.54.0

Re: [PATCH v4 2/2] riscv: timer: Enable early timer for M‑mode

[Yao Zi]

On Fri, Sep 11, 2026 at 10:14:06AM +0300, Nikita Shubin wrote:
> The generic RISC-V timer driver currently defines
> timer_early_get_count() only when CONFIG_IS_ENABLED(RISCV_SMODE),
> even though reading the TIME CSR is not inherently limited
> to S‑mode; it works in M‑mode as well when the CSR is implemented
> in hardware (e.g., with the Zicntr extension).
> 
> Moreover, timer_early_get_rate() is missing entirely for M‑mode,
> causing early timer functions to be unavailable on such systems.
> 
> Fix this by:
> - Moving timer_early_get_count() out of the RISCV_SMODE guard
>   so it is always available when CONFIG_TIMER_EARLY is set.
> - Adding M‑mode support to timer_early_get_rate(), returning
>   RISCV_MMODE_TIMER_FREQ when running in M‑mode
>   and RISCV_SMODE_TIMER_FREQ in S‑mode.
> 
> This is also necessary because several functions
> (e.g., net_random_ethaddr() via get_ticks()) rely on
> timer_early_get_count() even if CONFIG_TIMER_EARLY is not
> enabled.

Is this description correct? net_random_ethaddr() does invoke
get_ticks(), but the latter only delegates the work to
timer_early_get_count() when CONFIG_TIMER_EARLY is enabled and gd->timer
hasn't been initialized,

	uint64_t notrace get_ticks(void)
	{
		u64 count;
		int ret;

		if (!gd->timer) {
			int ret;

			if (IS_ENABLED(CONFIG_TIMER_EARLY))
				return timer_early_get_count();
	...


> Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me>

Otherwise this patch looks good to me.

Best regards,
Yao Zi

Re: [PATCH v4 2/2] riscv: timer: Enable early timer for M‑mode

[Nikita Shubin]

On Fri, 2026-09-11 at 08:27 +0000, Yao Zi wrote:
> On Fri, Sep 11, 2026 at 10:14:06AM +0300, Nikita Shubin wrote:
> > The generic RISC-V timer driver currently defines
> > timer_early_get_count() only when CONFIG_IS_ENABLED(RISCV_SMODE),
> > even though reading the TIME CSR is not inherently limited
> > to S‑mode; it works in M‑mode as well when the CSR is implemented
> > in hardware (e.g., with the Zicntr extension).
> > 
> > Moreover, timer_early_get_rate() is missing entirely for M‑mode,
> > causing early timer functions to be unavailable on such systems.
> > 
> > Fix this by:
> > - Moving timer_early_get_count() out of the RISCV_SMODE guard
> >   so it is always available when CONFIG_TIMER_EARLY is set.
> > - Adding M‑mode support to timer_early_get_rate(), returning
> >   RISCV_MMODE_TIMER_FREQ when running in M‑mode
> >   and RISCV_SMODE_TIMER_FREQ in S‑mode.
> > 
> > This is also necessary because several functions
> > (e.g., net_random_ethaddr() via get_ticks()) rely on
> > timer_early_get_count() even if CONFIG_TIMER_EARLY is not
> > enabled.
> 
> Is this description correct? net_random_ethaddr() does invoke
> get_ticks(), but the latter only delegates the work to
> timer_early_get_count() when CONFIG_TIMER_EARLY is enabled and gd-
> >timer
> hasn't been initialized,
> 
> 	uint64_t notrace get_ticks(void)
> 	{
> 		u64 count;
> 		int ret;
> 
> 		if (!gd->timer) {
> 			int ret;
> 
> 			if (IS_ENABLED(CONFIG_TIMER_EARLY))
> 				return timer_early_get_count();
> 	...
> 
> 
> > Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me>

Totally correct as this i how i came into fixing the RISCV TIMER, as 
if (IS_ENABLED(CONFIG_TIMER_EARLY)) doesn't protect us from linking
error if timer_early_get_count() is missing (unless i am missing
something).

It could be simply avoided by turning on any kind of ACLINT/CLINT
MTIMER (everybody has one of some sort) - but why i need it if i can
rely on RISCV TIMER in SPL stage ?

It seems no RISC-V board is currently using BOOTP/TFTP boot in SPL.

> 
> Otherwise this patch looks good to me.
> 
> Best regards,
> Yao Zi

Re: [PATCH v4 2/2] riscv: timer: Enable early timer for M‑mode

[Yao Zi]

On Fri, Sep 11, 2026 at 11:36:35AM +0300, Nikita Shubin wrote:
> On Fri, 2026-09-11 at 08:27 +0000, Yao Zi wrote:
> > On Fri, Sep 11, 2026 at 10:14:06AM +0300, Nikita Shubin wrote:
> > > The generic RISC-V timer driver currently defines
> > > timer_early_get_count() only when CONFIG_IS_ENABLED(RISCV_SMODE),
> > > even though reading the TIME CSR is not inherently limited
> > > to S‑mode; it works in M‑mode as well when the CSR is implemented
> > > in hardware (e.g., with the Zicntr extension).
> > > 
> > > Moreover, timer_early_get_rate() is missing entirely for M‑mode,
> > > causing early timer functions to be unavailable on such systems.
> > > 
> > > Fix this by:
> > > - Moving timer_early_get_count() out of the RISCV_SMODE guard
> > >   so it is always available when CONFIG_TIMER_EARLY is set.
> > > - Adding M‑mode support to timer_early_get_rate(), returning
> > >   RISCV_MMODE_TIMER_FREQ when running in M‑mode
> > >   and RISCV_SMODE_TIMER_FREQ in S‑mode.
> > > 
> > > This is also necessary because several functions
> > > (e.g., net_random_ethaddr() via get_ticks()) rely on
> > > timer_early_get_count() even if CONFIG_TIMER_EARLY is not
> > > enabled.
> > 
> > Is this description correct? net_random_ethaddr() does invoke
> > get_ticks(), but the latter only delegates the work to
> > timer_early_get_count() when CONFIG_TIMER_EARLY is enabled and gd-
> > >timer
> > hasn't been initialized,
> > 
> > 	uint64_t notrace get_ticks(void)
> > 	{
> > 		u64 count;
> > 		int ret;
> > 
> > 		if (!gd->timer) {
> > 			int ret;
> > 
> > 			if (IS_ENABLED(CONFIG_TIMER_EARLY))
> > 				return timer_early_get_count();
> > 	...
> > 
> > 
> > > Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me>
> 
> Totally correct as this i how i came into fixing the RISCV TIMER, as 
> if (IS_ENABLED(CONFIG_TIMER_EARLY)) doesn't protect us from linking
> error if timer_early_get_count() is missing (unless i am missing
> something).

With optimization, this branch should be turned into dead code and
the reference is thus eliminated. But anyway, please improve the
description to mention it's only a possible linking time dependency. I'm
simply confused by "rely on" since this should be dead code without
CONFIG_TIMER_EARLY :)

> It could be simply avoided by turning on any kind of ACLINT/CLINT
> MTIMER (everybody has one of some sort) - but why i need it if i can
> rely on RISCV TIMER in SPL stage ?
> 
> It seems no RISC-V board is currently using BOOTP/TFTP boot in SPL.
> 
> > 
> > Otherwise this patch looks good to me.
> > 
> > Best regards,
> > Yao Zi

Best regards,
Yao Zi

Re: [PATCH v4 2/2] riscv: timer: Enable early timer for M‑mode

[Nikita Shubin]

On Fri, 2026-09-11 at 09:03 +0000, Yao Zi wrote:
> On Fri, Sep 11, 2026 at 11:36:35AM +0300, Nikita Shubin wrote:
> > On Fri, 2026-09-11 at 08:27 +0000, Yao Zi wrote:
> > > On Fri, Sep 11, 2026 at 10:14:06AM +0300, Nikita Shubin wrote:
> > > > The generic RISC-V timer driver currently defines
> > > > timer_early_get_count() only when
> > > > CONFIG_IS_ENABLED(RISCV_SMODE),
> > > > even though reading the TIME CSR is not inherently limited
> > > > to S‑mode; it works in M‑mode as well when the CSR is
> > > > implemented
> > > > in hardware (e.g., with the Zicntr extension).
> > > > 
> > > > Moreover, timer_early_get_rate() is missing entirely for
> > > > M‑mode,
> > > > causing early timer functions to be unavailable on such
> > > > systems.
> > > > 
> > > > Fix this by:
> > > > - Moving timer_early_get_count() out of the RISCV_SMODE guard
> > > >   so it is always available when CONFIG_TIMER_EARLY is set.
> > > > - Adding M‑mode support to timer_early_get_rate(), returning
> > > >   RISCV_MMODE_TIMER_FREQ when running in M‑mode
> > > >   and RISCV_SMODE_TIMER_FREQ in S‑mode.
> > > > 
> > > > This is also necessary because several functions
> > > > (e.g., net_random_ethaddr() via get_ticks()) rely on
> > > > timer_early_get_count() even if CONFIG_TIMER_EARLY is not
> > > > enabled.
> > > 
> > > Is this description correct? net_random_ethaddr() does invoke
> > > get_ticks(), but the latter only delegates the work to
> > > timer_early_get_count() when CONFIG_TIMER_EARLY is enabled and
> > > gd-
> > > > timer
> > > hasn't been initialized,
> > > 
> > > 	uint64_t notrace get_ticks(void)
> > > 	{
> > > 		u64 count;
> > > 		int ret;
> > > 
> > > 		if (!gd->timer) {
> > > 			int ret;
> > > 
> > > 			if (IS_ENABLED(CONFIG_TIMER_EARLY))
> > > 				return timer_early_get_count();
> > > 	...
> > > 
> > > 
> > > > Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me>
> > 
> > Totally correct as this i how i came into fixing the RISCV TIMER,
> > as 
> > if (IS_ENABLED(CONFIG_TIMER_EARLY)) doesn't protect us from linking
> > error if timer_early_get_count() is missing (unless i am missing
> > something).
> 
> With optimization, this branch should be turned into dead code and
> the reference is thus eliminated. But anyway, please improve the
> description to mention it's only a possible linking time dependency.
> I'm
> simply confused by "rely on" since this should be dead code without
> CONFIG_TIMER_EARLY :)

Yep it's true - should be rephrased into:

"This is also necessary because several functions
(e.g., net_random_ethaddr() via get_ticks()) rely on
timer_early_get_count() and we should provide one if CONFIG_TIMER_EARLY
is enabled."

> 
> > It could be simply avoided by turning on any kind of ACLINT/CLINT
> > MTIMER (everybody has one of some sort) - but why i need it if i
> > can
> > rely on RISCV TIMER in SPL stage ?
> > 
> > It seems no RISC-V board is currently using BOOTP/TFTP boot in SPL.
> > 
> > > 
> > > Otherwise this patch looks good to me.
> > > 
> > > Best regards,
> > > Yao Zi
> 
> Best regards,
> Yao Zi