From: Nicolin Chen <nicolinc@nvidia.com>
To: Daniel Mentz <danielmentz@google.com>
Cc: <iommu@lists.linux.dev>, Will Deacon <will@kernel.org>,
Mostafa Saleh <smostafa@google.com>
Subject: Re: [PATCH] iommu/arm-smmu-v3: Align memory attributes for SMMU-originated accesses
Date: Wed, 30 Sep 2026 16:03:53 -0700 [thread overview]
Message-ID: <ar2VWVTSo2NtJdHr@nvidia.com> (raw)
In-Reply-To: <20260929032229.3532247-1-danielmentz@google.com>
On Tue, Sep 29, 2026 at 03:22:29AM +0000, Daniel Mentz wrote:
> @@ -4858,12 +4867,20 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu)
> return ret;
>
> /* CR1 (table and queue memory attributes) */
> - reg = FIELD_PREP(CR1_TABLE_SH, ARM_SMMU_SH_ISH) |
> - FIELD_PREP(CR1_TABLE_OC, CR1_CACHE_WB) |
> - FIELD_PREP(CR1_TABLE_IC, CR1_CACHE_WB) |
> - FIELD_PREP(CR1_QUEUE_SH, ARM_SMMU_SH_ISH) |
> - FIELD_PREP(CR1_QUEUE_OC, CR1_CACHE_WB) |
> - FIELD_PREP(CR1_QUEUE_IC, CR1_CACHE_WB);
> + if (smmu->features & ARM_SMMU_FEAT_COHERENCY) {
> + cache = CR1_CACHE_WB;
> + sh = ARM_SMMU_SH_ISH;
> + } else {
> + cache = CR1_CACHE_NC;
> + sh = ARM_SMMU_SH_OSH;
> + }
> +
> + reg = FIELD_PREP(CR1_TABLE_SH, sh) |
> + FIELD_PREP(CR1_TABLE_OC, cache) |
> + FIELD_PREP(CR1_TABLE_IC, cache) |
> + FIELD_PREP(CR1_QUEUE_SH, sh) |
> + FIELD_PREP(CR1_QUEUE_OC, cache) |
> + FIELD_PREP(CR1_QUEUE_IC, cache);
> writel_relaxed(reg, smmu->base + ARM_SMMU_CR1);
Nit: this is a big function. Perhaps, cr1_sh and cr1_cache?
Otherwise,
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
next prev parent reply other threads:[~2026-09-30 23:04 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-29 3:22 [PATCH] iommu/arm-smmu-v3: Align memory attributes for SMMU-originated accesses Daniel Mentz
2026-09-30 23:03 ` Nicolin Chen [this message]
2026-10-04 16:00 ` Will Deacon
2026-10-01 9:22 ` Mostafa Saleh
2026-10-02 22:45 ` Daniel Mentz
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