From: Max Chou <max.chou@sifive.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, palmer@dabbelt.com,
daniel.barboza@oss.qualcomm.com, Alistair.Francis@wdc.com,
philmd@oss.qualcomm.com
Subject: Re: [PATCH v3 00/11] tcg/riscv64: Fix AUIPC pair range validation
Date: Wed, 30 Sep 2026 11:42:03 +0800 [thread overview]
Message-ID: <aryAr-8oUs5ZJ-2-@sifive.com> (raw)
In-Reply-To: <983581aa-ffbd-40f9-8a9a-b6fbc066a1cf@linaro.org>
On 2026-09-27 10:30, Richard Henderson wrote:
> Ping.
>
> On 9/13/26 17:08, Richard Henderson wrote:
> > Hi Max,
> >
> > In v2, the change from int32_t to uint32_t is pretty much
> > the opposite of what should have been done, since all of
> > these are logically signed values. I've adjusted all of
> > the encoders to take signed inputs and assert in range.
> >
> > In the process, I noticed tha the branch range tests were
> > off by one. Now all performed in exactly one place.
> >
> > Finally, tcg_out_ldst needed updates for AUIPC as well.
> >
> > I've tested this lightly so far; full testing on a rather
> > slow riscv machine is still on-going.
> >
> >
> > r~
> >
Hi Richard,
I’ve discovered a verification scenario that could trigger an unexpected
segfault due to the AUIPC issue.
The scenario involves running a debug cross-build (riscv64) of
qemu-system-riscv64 with a plugin that instruments callback (e.g.,
libhotblocks.so) in a host riscv machine. (I used qemu-system-riscv64
with the same images here :p)
Before applying this patchset, the internal qemu-system-riscv64
encountered an unexpected segfault during bootup.
(P.S.: I built the riscv64 system mode image using buildroot
qemu_riscv64_virt_defconfig.)
Thanks,
rnax
prev parent reply other threads:[~2026-09-30 3:42 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-14 0:08 [PATCH v3 00/11] tcg/riscv64: Fix AUIPC pair range validation Richard Henderson
2026-09-14 0:08 ` [PATCH v3 01/11] tcg/riscv64: Return tcg_insn_unit from insn encoders Richard Henderson
2026-09-28 3:28 ` Alistair Francis
2026-09-29 15:42 ` Max Chou
2026-09-14 0:08 ` [PATCH v3 02/11] tcg/riscv64: Rename sb-type to b-type format Richard Henderson
2026-09-28 3:30 ` Alistair Francis
2026-09-29 15:43 ` Max Chou
2026-09-14 0:08 ` [PATCH v3 03/11] tcg/riscv64: Rename uj-type to j-type format Richard Henderson
2026-09-28 3:30 ` Alistair Francis
2026-09-29 15:44 ` Max Chou
2026-09-14 0:08 ` [PATCH v3 04/11] tcg/riscv64: Use signed type for encoding immediates Richard Henderson
2026-09-28 3:38 ` Alistair Francis
2026-09-29 15:44 ` Max Chou
2026-09-14 0:08 ` [PATCH v3 05/11] tcg/riscv64: Adjust sign of lui immediate in tcg_out_movi Richard Henderson
2026-09-28 3:33 ` Alistair Francis
2026-09-29 15:52 ` Max Chou
2026-09-14 0:08 ` [PATCH v3 06/11] tcg/riscv64: Assert immediate in range for [isu]-type insns Richard Henderson
2026-09-28 3:33 ` Alistair Francis
2026-09-29 15:57 ` Max Chou
2026-09-14 0:08 ` [PATCH v3 07/11] tcg/riscv64: Return success from encode_jimm Richard Henderson
2026-09-29 16:00 ` Max Chou
2026-09-14 0:08 ` [PATCH v3 08/11] tcg/riscv64: Return success from encode_bimm Richard Henderson
2026-09-29 16:01 ` Max Chou
2026-09-14 0:08 ` [PATCH v3 09/11] tcg/riscv64: Fix off-by-one in branch range tests Richard Henderson
2026-09-29 16:26 ` Max Chou
2026-09-14 0:08 ` [PATCH v3 10/11] tcg/riscv64: Validate AUIPC relocation range Richard Henderson
2026-09-29 16:32 ` Max Chou
2026-09-14 0:08 ` [PATCH v3 11/11] tcg/riscv64: Fall back when AUIPC pairs are out of range Richard Henderson
2026-09-29 16:32 ` Max Chou
2026-09-15 9:47 ` [PATCH v3 00/11] tcg/riscv64: Fix AUIPC pair range validation Max Chou
2026-09-27 17:30 ` Richard Henderson
2026-09-30 3:42 ` Max Chou [this message]
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