Re: [PATCH v9 00/26] usb: dwc3: part 2, make the resynced code work

[Anders Roxell <anders.roxell@linaro.org>]

On 2026-09-29 18:35, Siddharth Vadapalli wrote:
> On 9/29/26 3:37 PM, Anders Roxell wrote:
> > On 2026-09-25 16:09, Siddharth Vadapalli wrote:
> > 
> > [...]
> > 
> > > I didn't see "unknown endpoint event 0" at that point, so this series seems
> > > to introduce a regression.
> > 
> > Hi Siddharth,
> > 
> > Thanks for looking. But that line can not show up on mainline.
> > dwc3_ep0_interrupt() has no default case there, so an event 0 on ep0
> > is dropped and nothing is printed. The dev_err() came with the resync
> > from Linux. So your logs do not tell us if the event is new.
> > 
> > To know if it is a regression we need the same print on both. Can you
> > run ums on AM62p twice, once on plain master and once with my series,
> > and send me what it prints?
> > 
> > On plain master:
> > 
> >    --- a/drivers/usb/dwc3/ep0.c
> >    +++ b/drivers/usb/dwc3/ep0.c
> >    @@ void dwc3_ep0_interrupt(struct dwc3 *dwc,
> >     	case DWC3_DEPEVT_EPCMDCMPLT:
> >     		break;
> >    +	default:
> >    +		printf("unknown ep0 event %d raw %08x\n",
> >    +		       event->endpoint_event, *(const u32 *)event);
> >    +		break;
> >     	}
> >     }
> 
> Based on commit
> 369d71b895b usb: dwc3-generic: Fix ref clock enable error check
> of the main branch and with the above diff applied, I see the following on
> AM62P:
> => ums 0 mmc 1
> UMS: LUN 0, dev mmc 1, hwpart 0, sector 0x0, count 0x1dacc00
> CTRL+C - Operation aborted
> =>
> 
> So the 'unknown ep0 event' print doesn't appear on mainline.

Thanks for testing. Did the host see the disk in that run? If it did,
then mainline is clean and my series causes it.

> 
> > 
> > With my series:
> > 
> >    --- a/drivers/usb/dwc3/ep0.c
> >    +++ b/drivers/usb/dwc3/ep0.c
> >    @@ void dwc3_ep0_interrupt(struct dwc3 *dwc,
> >     	default:
> >     		dev_err(dwc->dev, "unknown endpoint event %d\n", event->endpoint_event);
> >    +		printf("unknown ep0 event %d raw %08x\n",
> >    +		       event->endpoint_event, *(const u32 *)event);
> >     		break;
> >     	}
> 
> I couldn't apply the part1 / part2 series cleanly, so I wasn't able to test
> this on AM62P.


Part 1 and part 2 are both on this branch, so you do not need to apply
anything:

https://github.com/roxell/u-boot/tree/usb_dwc3_sync_v9

Can you run ums there with the diff for my series and send me the raw
value?

The raw value tells me where to look. If it is 00000000 we read an
empty slot. Then I will start with the event buffer code, it changed
a lot in the resync. If other bits are set it is a real event, and
something in the ep0 code handles it wrong.

Cheers,
Anders