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From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: zl020895 <zl020895@163.com>
Cc: longzhao@ambarella.com, Bartosz Golaszewski <brgl@kernel.org>,
	linux-gpio@vger.kernel.org, Linus Walleij <linusw@kernel.org>,
	Michael Walle <mwalle@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>,
	Conor Dooley <conor+dt@kernel.org>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: Re: [PATCH 6/7] gpio: pl061: switch data path to gpio-regmap
Date: Tue, 13 Oct 2026 12:50:46 +0300	[thread overview]
Message-ID: <as3-9rn0HgpPuiJp@ashevche-desk.local> (raw)
In-Reply-To: <e1c092a.7c2c.1a1347a0650.Coremail.zl020895@163.com>

On Tue, Oct 13, 2026 at 04:56:14PM +0800, zl020895 wrote:
> Hi Andy,
> 
> Sorry for the churn and thanks for the review.
> 
> Looking back at your v9 review of the convert patch, the only point I
> did not follow is the data-register path. You marked those
> regmap_write() sites with _set_bits(). I did switch direction and IRQ
> enable to regmap_test_bits() / regmap_clear_bits() / regmap_set_bits(),
> but I left the data-register writes as regmap_write(), because
> regmap_set_bits() cannot clear a bit to drive the line low. 

Can you elaborate on this a bit? Even if the cached value is 0, you still want
to write 0, do I understand correctly? Wouldn't it just mean that the registers
should be marked as volatile or something like that?

> In the next version I will use regmap_assign_bits() there.

Hmm... If regmap_set_bits() doesn't work for you, regmap_assign_bits() will not
work either.

> I did not find the other notes from this mail — drop fast_io, keep the
> regmap_config in the convert patch, and the guard() blank lines — in
> the v9 comments. I will fix those in the next version as well, along
> with reverse Christmas tree in irq_type and a precursor to drop the
> redundant if (pending) check.

Yeah, some notes are new, I only referred to the old ones.
But I believe I have mentioned that the code is not needed a shuffle
as it seems already in a good place. Otherwise it's unclear from this
change why the almost unmodified code is moved around.

...

> >> -static bool pl061_is_data_reg(unsigned int reg)
> >> -{
> >> -	return is_power_of_2(reg) &&
> >> -	       reg >= BIT(PL061_DATA_OFFSET) &&
> >> -	       reg <= BIT(PL061_DATA_OFFSET + PL061_GPIO_NR - 1);
> >> -}
> >> -
> >> -static bool pl061_volatile_reg(struct device *dev, unsigned int reg)
> >> -{
> >> -	switch (reg) {
> >> -	case GPIOMIS:
> >> -	case GPIOIC:
> >> -		return true;
> >> -	default:
> >> -		return pl061_is_data_reg(reg);
> >> -	}
> >> -}
> >> -
> >> -static const struct regmap_config pl061_regmap_config = {
> >> -	.reg_bits = 16,
> >> -	.val_bits = 8,
> >> -	.reg_stride = 4,
> >> -	.max_register = GPIOIC,
> >> -	.volatile_reg = pl061_volatile_reg,
> >> -	.fast_io = true,
> >> -	.use_raw_spinlock = true,
> >> -};
> >
> >No, I have already told you do not move these. If you need to rename, just make
> >sure it's named accordingly in the previous patch that introduced this.

...

> >I have a feeling that you ignored my last review. I stop it here, you need to
> >carefully read *all* the comments and act accordingly.

-- 
With Best Regards,
Andy Shevchenko



  reply	other threads:[~2026-10-13  9:50 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-09 10:57 [PATCH 0/7] gpio: add Ambarella CV75 PL061 support Long Zhao
2026-10-09 10:57 ` Long Zhao via B4 Relay
2026-10-09 10:57 ` [PATCH 1/7] dt-bindings: gpio: pl061: add Ambarella CV75 variant Long Zhao
2026-10-09 10:57   ` Long Zhao via B4 Relay
2026-10-09 11:32   ` Krzysztof Kozlowski
2026-10-09 10:57 ` [PATCH 2/7] gpiolib: regmap: add GPIO_REGMAP_QUIRK_SET_AFTER_DIR Long Zhao
2026-10-09 10:57   ` Long Zhao via B4 Relay
2026-10-09 11:17   ` Michael Walle
2026-10-09 11:27   ` sashiko-bot
2026-10-09 10:57 ` [PATCH 3/7] gpio: pl061: convert register access to regmap Long Zhao
2026-10-09 10:57   ` Long Zhao via B4 Relay
2026-10-13  7:10   ` Andy Shevchenko
2026-10-09 10:57 ` [PATCH 4/7] gpio: pl061: use IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH Long Zhao
2026-10-09 10:57   ` Long Zhao via B4 Relay
2026-10-09 10:57 ` [PATCH 5/7] gpio: pl061: use cleanup helpers for locks Long Zhao
2026-10-09 10:57   ` Long Zhao via B4 Relay
2026-10-13  7:12   ` Andy Shevchenko
2026-10-09 10:57 ` [PATCH 6/7] gpio: pl061: switch data path to gpio-regmap Long Zhao
2026-10-09 10:57   ` Long Zhao via B4 Relay
2026-10-09 11:50   ` sashiko-bot
2026-10-13  7:15   ` Andy Shevchenko
2026-10-13  8:56     ` zl020895
2026-10-13  9:50       ` Andy Shevchenko [this message]
2026-10-13 10:41         ` Re:Re: " zl020895
2026-10-09 10:58 ` [PATCH 7/7] gpio: pl061: add Ambarella register-layout variant Long Zhao
2026-10-09 10:58   ` Long Zhao via B4 Relay
2026-10-09 12:03   ` sashiko-bot
2026-10-13  7:17   ` Andy Shevchenko
2026-10-13  8:59     ` zl020895
2026-10-13  9:46       ` Andy Shevchenko
2026-10-09 11:32 ` [PATCH 0/7] gpio: add Ambarella CV75 PL061 support Krzysztof Kozlowski
2026-10-13 12:58 ` Bartosz Golaszewski
2026-10-13 14:10   ` zl020895
2026-10-13 15:09     ` Bartosz Golaszewski
2026-10-13 15:36       ` zl020895

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