From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: longzhao@ambarella.com
Cc: Bartosz Golaszewski <brgl@kernel.org>,
linux-gpio@vger.kernel.org, Linus Walleij <linusw@kernel.org>,
Michael Walle <mwalle@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>,
Conor Dooley <conor+dt@kernel.org>,
devicetree@vger.kernel.org, Long Zhao <zl020895@163.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 7/7] gpio: pl061: add Ambarella register-layout variant
Date: Tue, 13 Oct 2026 10:17:01 +0300 [thread overview]
Message-ID: <as3a7UTe9YEyBAY3@ashevche-desk.local> (raw)
In-Reply-To: <20261009-cv75-gpio-v1-7-5836bd438423@ambarella.com>
On Fri, Oct 09, 2026 at 06:58:00PM +0800, Long Zhao via B4 Relay wrote:
> Add a 32-bit, 32-line layout with DAT/DIR/IS/IBE/IEV/IE/MIS/IC plus
> MASK and ENABLE. Probe unmasks the bank and enables the controller.
> IRQ type changes also clear the pending bit. This derivative does not
> need write-after-direction or system suspend save/restore.
>
> Cache DAT (REGCACHE_FLAT_S, not volatile) so gpio_set() updates one
> bit from the output shadow instead of read-modify-writing the pin
> level across the bank.
>
> Match the part with designer AMBA_VENDOR_AMBARELLA (JEP106 identity
> 0x68, bit 7 set) and part number 0x061.
Ick?! I thought I gave a tag for this. What's going on?
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2026-10-13 7:17 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-09 10:57 [PATCH 0/7] gpio: add Ambarella CV75 PL061 support Long Zhao
2026-10-09 10:57 ` Long Zhao via B4 Relay
2026-10-09 10:57 ` [PATCH 1/7] dt-bindings: gpio: pl061: add Ambarella CV75 variant Long Zhao
2026-10-09 10:57 ` Long Zhao via B4 Relay
2026-10-09 11:32 ` Krzysztof Kozlowski
2026-10-09 10:57 ` [PATCH 2/7] gpiolib: regmap: add GPIO_REGMAP_QUIRK_SET_AFTER_DIR Long Zhao
2026-10-09 10:57 ` Long Zhao via B4 Relay
2026-10-09 11:17 ` Michael Walle
2026-10-09 11:27 ` sashiko-bot
2026-10-09 10:57 ` [PATCH 3/7] gpio: pl061: convert register access to regmap Long Zhao
2026-10-09 10:57 ` Long Zhao via B4 Relay
2026-10-13 7:10 ` Andy Shevchenko
2026-10-09 10:57 ` [PATCH 4/7] gpio: pl061: use IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH Long Zhao
2026-10-09 10:57 ` Long Zhao via B4 Relay
2026-10-09 10:57 ` [PATCH 5/7] gpio: pl061: use cleanup helpers for locks Long Zhao
2026-10-09 10:57 ` Long Zhao via B4 Relay
2026-10-13 7:12 ` Andy Shevchenko
2026-10-09 10:57 ` [PATCH 6/7] gpio: pl061: switch data path to gpio-regmap Long Zhao
2026-10-09 10:57 ` Long Zhao via B4 Relay
2026-10-09 11:50 ` sashiko-bot
2026-10-13 7:15 ` Andy Shevchenko
2026-10-13 8:56 ` zl020895
2026-10-13 9:50 ` Andy Shevchenko
2026-10-13 10:41 ` zl020895
2026-10-09 10:58 ` [PATCH 7/7] gpio: pl061: add Ambarella register-layout variant Long Zhao
2026-10-09 10:58 ` Long Zhao via B4 Relay
2026-10-09 12:03 ` sashiko-bot
2026-10-13 7:17 ` Andy Shevchenko [this message]
2026-10-13 8:59 ` zl020895
2026-10-13 9:46 ` Andy Shevchenko
2026-10-09 11:32 ` [PATCH 0/7] gpio: add Ambarella CV75 PL061 support Krzysztof Kozlowski
2026-10-13 12:58 ` Bartosz Golaszewski
2026-10-13 14:10 ` zl020895
2026-10-13 15:09 ` Bartosz Golaszewski
2026-10-13 15:36 ` zl020895
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