[PATCH 1/3] dt-bindings: gpu: nvidia,gk20a: Allow a fuse clock after the reference clock

[PATCH 1/3] dt-bindings: gpu: nvidia,gk20a: Allow a fuse clock after the reference clock

[Sasha Levin]

GM20B needs both its reference clock and the fuse clock while it is
powered, so allow "fuse" as a fourth clock after "ref".

Assisted-by: LLM
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml
index 4d856a8b674c..ecbc20e6adec 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml
+++ b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml
@@ -44,6 +44,7 @@ properties:
       - description: GPU clock
       - description: Power clock
       - description: Reference or fuse clock
+      - description: Fuse clock
 
   clock-names:
     minItems: 2
@@ -51,6 +52,7 @@ properties:
       - const: gpu
       - const: pwr
       - enum: [ ref, fuse ]
+      - const: fuse
 
   resets:
     maxItems: 1
-- 
2.43.0

[PATCH 1/3] dt-bindings: gpu: nvidia,gk20a: Allow a fuse clock after the reference clock

[Sasha Levin]

GM20B needs both its reference clock and the fuse clock while it is
powered, so allow "fuse" as a fourth clock after "ref".

Assisted-by: LLM
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml
index 4d856a8b674c..ecbc20e6adec 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml
+++ b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml
@@ -44,6 +44,7 @@ properties:
       - description: GPU clock
       - description: Power clock
       - description: Reference or fuse clock
+      - description: Fuse clock
 
   clock-names:
     minItems: 2
@@ -51,6 +52,7 @@ properties:
       - const: gpu
       - const: pwr
       - enum: [ ref, fuse ]
+      - const: fuse
 
   resets:
     maxItems: 1
-- 
2.43.0

[PATCH 1/3] dt-bindings: gpu: nvidia, gk20a: Allow a fuse clock after the reference clock

[Sasha Levin]

GM20B needs both its reference clock and the fuse clock while it is
powered, so allow "fuse" as a fourth clock after "ref".

Assisted-by: LLM
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml
index 4d856a8b674c..ecbc20e6adec 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml
+++ b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml
@@ -44,6 +44,7 @@ properties:
       - description: GPU clock
       - description: Power clock
       - description: Reference or fuse clock
+      - description: Fuse clock
 
   clock-names:
     minItems: 2
@@ -51,6 +52,7 @@ properties:
       - const: gpu
       - const: pwr
       - enum: [ ref, fuse ]
+      - const: fuse
 
   resets:
     maxItems: 1
-- 
2.43.0

[PATCH 2/3] arm64: tegra: Add the fuse clock to the Tegra210 GPU

[Sasha Levin]

The GM20B GPU on Tegra210 needs the fuse clock running while it is
powered. Describe it so that the GPU driver can keep it enabled.

Assisted-by: LLM
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 5f5e5370d709..2e84b2bda314 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -446,8 +446,9 @@ gpu@57000000 {
 		interrupt-names = "stall", "nonstall";
 		clocks = <&tegra_car TEGRA210_CLK_GPU>,
 			 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
-			 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
-		clock-names = "gpu", "pwr", "ref";
+			 <&tegra_car TEGRA210_CLK_PLL_G_REF>,
+			 <&tegra_car TEGRA210_CLK_FUSE>;
+		clock-names = "gpu", "pwr", "ref", "fuse";
 		resets = <&tegra_car 184>;
 		reset-names = "gpu";
 
-- 
2.43.0

[PATCH 2/3] arm64: tegra: Add the fuse clock to the Tegra210 GPU

[Sasha Levin]

The GM20B GPU on Tegra210 needs the fuse clock running while it is
powered. Describe it so that the GPU driver can keep it enabled.

Assisted-by: LLM
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 5f5e5370d709..2e84b2bda314 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -446,8 +446,9 @@ gpu@57000000 {
 		interrupt-names = "stall", "nonstall";
 		clocks = <&tegra_car TEGRA210_CLK_GPU>,
 			 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
-			 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
-		clock-names = "gpu", "pwr", "ref";
+			 <&tegra_car TEGRA210_CLK_PLL_G_REF>,
+			 <&tegra_car TEGRA210_CLK_FUSE>;
+		clock-names = "gpu", "pwr", "ref", "fuse";
 		resets = <&tegra_car 184>;
 		reset-names = "gpu";
 
-- 
2.43.0

[PATCH 3/3] drm/nouveau/tegra: Keep the fuse clock enabled while the GPU is powered

[Sasha Levin]

Since the GPU on the Jetson TX1 was enabled in commit d1b725476104
("arm64: tegra: p2180: Explicitly enable GPU"), nouveau often fails to
bring up the GM20B. Either BOOT_0 reads back garbage ("unknown chipset
(5ffefa47)"), or PRI reads of the GPC PLL time out ("MMIO read of
00000000 FAULT at 137000 [ TIMEOUT ]"), or the first register reads in
nvkm_device_ctor() stall until an asynchronous SError. How often depends
on the board; one board fails on every boot.

nouveau powers the GPU up with the fuse clock gated: since commit
24a15252ff04 ("soc/tegra: fuse: Add runtime PM support"), the Tegra fuse
driver only enables that clock around its own fuse reads. NVIDIA's
downstream nvgpu driver enables the fuse clock along with the other GPU
clocks whenever the GPU is powered. Do the same: take an optional "fuse"
clock and keep it enabled from before the GPU rail is turned on until
after it is turned off.

Tested on eight Jetson TX1 devkits, on mainline and on v6.18. Without
this patch, the GPU failed to come up in 27 of 109 boots; with it, in 11
of 291, none of them with a garbage BOOT_0. On the board that failed on
every boot, 38 of 40 boots now succeed. The remaining failures are
mostly a register read that stalls until an SError; wherever the console
shows when, nouveau had already finished probing. Such stalls also occur
without this patch and are a separate problem. The Jetson Nano, which
shares the Tegra210 GPU node, still works (24 of 24 boots).

Fixes: d1b725476104 ("arm64: tegra: p2180: Explicitly enable GPU")
Assisted-by: LLM
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h  |  1 +
 drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 13 +++++++++++++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h b/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h
index 6aaa30ef167f..0189043382d0 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h
@@ -15,6 +15,7 @@ struct nvkm_device_tegra {
 	struct clk *clk;
 	struct clk *clk_ref;
 	struct clk *clk_pwr;
+	struct clk *clk_fuse;
 
 	struct regulator *vdd;
 
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
index 3c8d0878891a..31f8eaa9d650 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
@@ -32,6 +32,10 @@ nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev)
 {
 	int ret;
 
+	ret = clk_prepare_enable(tdev->clk_fuse);
+	if (ret)
+		return ret;
+
 	if (tdev->vdd) {
 		ret = regulator_enable(tdev->vdd);
 		if (ret)
@@ -76,6 +80,7 @@ nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev)
 	if (tdev->vdd)
 		regulator_disable(tdev->vdd);
 err_power:
+	clk_disable_unprepare(tdev->clk_fuse);
 	return ret;
 }
 
@@ -95,6 +100,8 @@ nvkm_device_tegra_power_down(struct nvkm_device_tegra *tdev)
 			return ret;
 	}
 
+	clk_disable_unprepare(tdev->clk_fuse);
+
 	return 0;
 }
 
@@ -308,6 +315,12 @@ nvkm_device_tegra_new(const struct nvkm_device_tegra_func *func,
 		goto free;
 	}
 
+	tdev->clk_fuse = devm_clk_get_optional(&pdev->dev, "fuse");
+	if (IS_ERR(tdev->clk_fuse)) {
+		ret = PTR_ERR(tdev->clk_fuse);
+		goto free;
+	}
+
 	tdev->pmc = devm_tegra_pmc_get(&pdev->dev);
 	if (IS_ERR(tdev->pmc)) {
 		ret = PTR_ERR(tdev->pmc);
-- 
2.43.0

[PATCH 3/3] drm/nouveau/tegra: Keep the fuse clock enabled while the GPU is powered

[Sasha Levin]

Since the GPU on the Jetson TX1 was enabled in commit d1b725476104
("arm64: tegra: p2180: Explicitly enable GPU"), nouveau often fails to
bring up the GM20B. Either BOOT_0 reads back garbage ("unknown chipset
(5ffefa47)"), or PRI reads of the GPC PLL time out ("MMIO read of
00000000 FAULT at 137000 [ TIMEOUT ]"), or the first register reads in
nvkm_device_ctor() stall until an asynchronous SError. How often depends
on the board; one board fails on every boot.

nouveau powers the GPU up with the fuse clock gated: since commit
24a15252ff04 ("soc/tegra: fuse: Add runtime PM support"), the Tegra fuse
driver only enables that clock around its own fuse reads. NVIDIA's
downstream nvgpu driver enables the fuse clock along with the other GPU
clocks whenever the GPU is powered. Do the same: take an optional "fuse"
clock and keep it enabled from before the GPU rail is turned on until
after it is turned off.

Tested on eight Jetson TX1 devkits, on mainline and on v6.18. Without
this patch, the GPU failed to come up in 27 of 109 boots; with it, in 11
of 291, none of them with a garbage BOOT_0. On the board that failed on
every boot, 38 of 40 boots now succeed. The remaining failures are
mostly a register read that stalls until an SError; wherever the console
shows when, nouveau had already finished probing. Such stalls also occur
without this patch and are a separate problem. The Jetson Nano, which
shares the Tegra210 GPU node, still works (24 of 24 boots).

Fixes: d1b725476104 ("arm64: tegra: p2180: Explicitly enable GPU")
Assisted-by: LLM
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h  |  1 +
 drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 13 +++++++++++++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h b/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h
index 6aaa30ef167f..0189043382d0 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h
@@ -15,6 +15,7 @@ struct nvkm_device_tegra {
 	struct clk *clk;
 	struct clk *clk_ref;
 	struct clk *clk_pwr;
+	struct clk *clk_fuse;
 
 	struct regulator *vdd;
 
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
index 3c8d0878891a..31f8eaa9d650 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
@@ -32,6 +32,10 @@ nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev)
 {
 	int ret;
 
+	ret = clk_prepare_enable(tdev->clk_fuse);
+	if (ret)
+		return ret;
+
 	if (tdev->vdd) {
 		ret = regulator_enable(tdev->vdd);
 		if (ret)
@@ -76,6 +80,7 @@ nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev)
 	if (tdev->vdd)
 		regulator_disable(tdev->vdd);
 err_power:
+	clk_disable_unprepare(tdev->clk_fuse);
 	return ret;
 }
 
@@ -95,6 +100,8 @@ nvkm_device_tegra_power_down(struct nvkm_device_tegra *tdev)
 			return ret;
 	}
 
+	clk_disable_unprepare(tdev->clk_fuse);
+
 	return 0;
 }
 
@@ -308,6 +315,12 @@ nvkm_device_tegra_new(const struct nvkm_device_tegra_func *func,
 		goto free;
 	}
 
+	tdev->clk_fuse = devm_clk_get_optional(&pdev->dev, "fuse");
+	if (IS_ERR(tdev->clk_fuse)) {
+		ret = PTR_ERR(tdev->clk_fuse);
+		goto free;
+	}
+
 	tdev->pmc = devm_tegra_pmc_get(&pdev->dev);
 	if (IS_ERR(tdev->pmc)) {
 		ret = PTR_ERR(tdev->pmc);
-- 
2.43.0

Re: [PATCH 3/3] drm/nouveau/tegra: Keep the fuse clock enabled while the GPU is powered

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] nouveau: tegra: clk_fuse leak on power_down failure
--

commit 4446c1485fff0b05a5e79c1e4d70e14c4beda300
Author: Sasha Levin <sashal@kernel.org>

    drm/nouveau/tegra: Keep the fuse clock enabled while the GPU is powered

This commit modifies nouveau's Tegra power management sequence to keep the
fuse clock enabled while the GPU is powered. This resolves an issue where
the GM20B GPU would fail to initialize on some boots.

> diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
> index 3c8d0878891ad..31f8eaa9d6509 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
> +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c

[ ... ]

> @@ -95,6 +100,8 @@ nvkm_device_tegra_power_down(struct nvkm_device_tegra *tdev)
>  			return ret;
>  	}
>  
> +	clk_disable_unprepare(tdev->clk_fuse);
> +
>  	return 0;
>  }

[Severity: Medium]
Does this code leak the clk_fuse enable and prepare counts if
regulator_disable() fails?

If regulator_disable() fails and returns an error, the function immediately
returns early. Because the new clk_disable_unprepare() call is positioned
at the very end of this function, it is skipped entirely on this error path.

Since callers like nvkm_device_tegra_dtor() ignore the return value of
nvkm_device_tegra_power_down() and proceed to free the device structure,
would this result in a permanent resource leak where the clk_fuse's prepare
and enable counts are never decremented?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261013145210.103565-1-sashal@kernel.org?part=3

Re: [PATCH 1/3] dt-bindings: gpu: nvidia,gk20a: Allow a fuse clock after the reference clock

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1875 bytes --]

On Tue, Oct 13, 2026 at 10:52:08AM -0400, Sasha Levin wrote:
> GM20B needs both its reference clock and the fuse clock while it is
> powered, so allow "fuse" as a fourth clock after "ref".
> 
> Assisted-by: LLM
> Signed-off-by: Sasha Levin <sashal@kernel.org>
> ---
>  Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml
> index 4d856a8b674c..ecbc20e6adec 100644
> --- a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml
> +++ b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml
> @@ -44,6 +44,7 @@ properties:
>        - description: GPU clock
>        - description: Power clock
>        - description: Reference or fuse clock
> +      - description: Fuse clock
>  
>    clock-names:
>      minItems: 2
> @@ -51,6 +52,7 @@ properties:
>        - const: gpu
>        - const: pwr
>        - enum: [ ref, fuse ]
> +      - const: fuse

Technically this now allows:

    clock-names = "gpu", "pwr", "fuse", "fuse";

I think we may need a very explicit version to cover this now, something
like:

    clock-names:
      oneOf:
        # for GK20A, GP10B, and GV11B
        - minItems: 2
          items:
            - const: gpu
            - const: pwr
            - const: fuse

        # for GM20B
        - minItems: 3
          items:
            - const: gpu
            - const: pwr
            - const: ref
            - const: fuse

We may also want to leave out the minItems property because it turns out
the FUSE clock is indeed required, so we'll need to add it to all device
trees anyway to fix this hang.

The exact list of items could also go into the per-SoC/GPU conditional
sections to be very exact.

Thierry

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Re: [PATCH 1/3] dt-bindings: gpu: nvidia,gk20a: Allow a fuse clock after the reference clock

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1875 bytes --]

On Tue, Oct 13, 2026 at 10:52:08AM -0400, Sasha Levin wrote:
> GM20B needs both its reference clock and the fuse clock while it is
> powered, so allow "fuse" as a fourth clock after "ref".
> 
> Assisted-by: LLM
> Signed-off-by: Sasha Levin <sashal@kernel.org>
> ---
>  Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml
> index 4d856a8b674c..ecbc20e6adec 100644
> --- a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml
> +++ b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml
> @@ -44,6 +44,7 @@ properties:
>        - description: GPU clock
>        - description: Power clock
>        - description: Reference or fuse clock
> +      - description: Fuse clock
>  
>    clock-names:
>      minItems: 2
> @@ -51,6 +52,7 @@ properties:
>        - const: gpu
>        - const: pwr
>        - enum: [ ref, fuse ]
> +      - const: fuse

Technically this now allows:

    clock-names = "gpu", "pwr", "fuse", "fuse";

I think we may need a very explicit version to cover this now, something
like:

    clock-names:
      oneOf:
        # for GK20A, GP10B, and GV11B
        - minItems: 2
          items:
            - const: gpu
            - const: pwr
            - const: fuse

        # for GM20B
        - minItems: 3
          items:
            - const: gpu
            - const: pwr
            - const: ref
            - const: fuse

We may also want to leave out the minItems property because it turns out
the FUSE clock is indeed required, so we'll need to add it to all device
trees anyway to fix this hang.

The exact list of items could also go into the per-SoC/GPU conditional
sections to be very exact.

Thierry

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Re: [PATCH 2/3] arm64: tegra: Add the fuse clock to the Tegra210 GPU

[Thierry Reding]

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On Tue, Oct 13, 2026 at 10:52:09AM -0400, Sasha Levin wrote:
> The GM20B GPU on Tegra210 needs the fuse clock running while it is
> powered. Describe it so that the GPU driver can keep it enabled.
> 
> Assisted-by: LLM
> Signed-off-by: Sasha Levin <sashal@kernel.org>
> ---
>  arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)

We already have that FUSE clock in Tegra194, but since this is now
needed on older models as well, I think we need to add this as far back
as Tegra124, since it likely has the exact same requirements.

Thierry

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Re: [PATCH 2/3] arm64: tegra: Add the fuse clock to the Tegra210 GPU

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 605 bytes --]

On Tue, Oct 13, 2026 at 10:52:09AM -0400, Sasha Levin wrote:
> The GM20B GPU on Tegra210 needs the fuse clock running while it is
> powered. Describe it so that the GPU driver can keep it enabled.
> 
> Assisted-by: LLM
> Signed-off-by: Sasha Levin <sashal@kernel.org>
> ---
>  arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)

We already have that FUSE clock in Tegra194, but since this is now
needed on older models as well, I think we need to add this as far back
as Tegra124, since it likely has the exact same requirements.

Thierry

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Re: [PATCH 3/3] drm/nouveau/tegra: Keep the fuse clock enabled while the GPU is powered

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 2456 bytes --]

On Tue, Oct 13, 2026 at 10:52:10AM -0400, Sasha Levin wrote:
> Since the GPU on the Jetson TX1 was enabled in commit d1b725476104
> ("arm64: tegra: p2180: Explicitly enable GPU"), nouveau often fails to
> bring up the GM20B. Either BOOT_0 reads back garbage ("unknown chipset
> (5ffefa47)"), or PRI reads of the GPC PLL time out ("MMIO read of
> 00000000 FAULT at 137000 [ TIMEOUT ]"), or the first register reads in
> nvkm_device_ctor() stall until an asynchronous SError. How often depends
> on the board; one board fails on every boot.
> 
> nouveau powers the GPU up with the fuse clock gated: since commit
> 24a15252ff04 ("soc/tegra: fuse: Add runtime PM support"), the Tegra fuse
> driver only enables that clock around its own fuse reads. NVIDIA's
> downstream nvgpu driver enables the fuse clock along with the other GPU
> clocks whenever the GPU is powered. Do the same: take an optional "fuse"
> clock and keep it enabled from before the GPU rail is turned on until
> after it is turned off.
> 
> Tested on eight Jetson TX1 devkits, on mainline and on v6.18. Without
> this patch, the GPU failed to come up in 27 of 109 boots; with it, in 11
> of 291, none of them with a garbage BOOT_0. On the board that failed on
> every boot, 38 of 40 boots now succeed. The remaining failures are
> mostly a register read that stalls until an SError; wherever the console
> shows when, nouveau had already finished probing. Such stalls also occur
> without this patch and are a separate problem. The Jetson Nano, which
> shares the Tegra210 GPU node, still works (24 of 24 boots).
> 
> Fixes: d1b725476104 ("arm64: tegra: p2180: Explicitly enable GPU")
> Assisted-by: LLM
> Signed-off-by: Sasha Levin <sashal@kernel.org>
> ---
>  drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h  |  1 +
>  drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 13 +++++++++++++
>  2 files changed, 14 insertions(+)

Given the failure rates, I'm almost tempted to say we need to break DT
ABI and consider the FUSE clock to be required, in which case the driver
should use the regular devm_clk_get() instead of the optional variant.

As you said, we probably got away with this for a long time because we
either didn't enabled the GPU by default or because the FUSE clock was
always turned on. Or we might've tested GPU as built-in, in which case
the FUSE clock might have still been on (not disabled after early boot
yet).

Thierry

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Re: [PATCH 3/3] drm/nouveau/tegra: Keep the fuse clock enabled while the GPU is powered

[Thierry Reding]

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On Tue, Oct 13, 2026 at 10:52:10AM -0400, Sasha Levin wrote:
> Since the GPU on the Jetson TX1 was enabled in commit d1b725476104
> ("arm64: tegra: p2180: Explicitly enable GPU"), nouveau often fails to
> bring up the GM20B. Either BOOT_0 reads back garbage ("unknown chipset
> (5ffefa47)"), or PRI reads of the GPC PLL time out ("MMIO read of
> 00000000 FAULT at 137000 [ TIMEOUT ]"), or the first register reads in
> nvkm_device_ctor() stall until an asynchronous SError. How often depends
> on the board; one board fails on every boot.
> 
> nouveau powers the GPU up with the fuse clock gated: since commit
> 24a15252ff04 ("soc/tegra: fuse: Add runtime PM support"), the Tegra fuse
> driver only enables that clock around its own fuse reads. NVIDIA's
> downstream nvgpu driver enables the fuse clock along with the other GPU
> clocks whenever the GPU is powered. Do the same: take an optional "fuse"
> clock and keep it enabled from before the GPU rail is turned on until
> after it is turned off.
> 
> Tested on eight Jetson TX1 devkits, on mainline and on v6.18. Without
> this patch, the GPU failed to come up in 27 of 109 boots; with it, in 11
> of 291, none of them with a garbage BOOT_0. On the board that failed on
> every boot, 38 of 40 boots now succeed. The remaining failures are
> mostly a register read that stalls until an SError; wherever the console
> shows when, nouveau had already finished probing. Such stalls also occur
> without this patch and are a separate problem. The Jetson Nano, which
> shares the Tegra210 GPU node, still works (24 of 24 boots).
> 
> Fixes: d1b725476104 ("arm64: tegra: p2180: Explicitly enable GPU")
> Assisted-by: LLM
> Signed-off-by: Sasha Levin <sashal@kernel.org>
> ---
>  drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h  |  1 +
>  drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 13 +++++++++++++
>  2 files changed, 14 insertions(+)

Given the failure rates, I'm almost tempted to say we need to break DT
ABI and consider the FUSE clock to be required, in which case the driver
should use the regular devm_clk_get() instead of the optional variant.

As you said, we probably got away with this for a long time because we
either didn't enabled the GPU by default or because the FUSE clock was
always turned on. Or we might've tested GPU as built-in, in which case
the FUSE clock might have still been on (not disabled after early boot
yet).

Thierry

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Re: [PATCH 1/3] dt-bindings: gpu: nvidia,gk20a: Allow a fuse clock after the reference clock

[Thierry Reding]

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On Tue, Oct 13, 2026 at 10:52:08AM -0400, Sasha Levin wrote:
> GM20B needs both its reference clock and the fuse clock while it is
> powered, so allow "fuse" as a fourth clock after "ref".
> 
> Assisted-by: LLM
> Signed-off-by: Sasha Levin <sashal@kernel.org>
> ---
>  Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml | 2 ++
>  1 file changed, 2 insertions(+)

Aaron, Diogo,

I'm fairly sure I remember at least one of you mentioning that GM20B
wasn't always working reliably. Would you mind giving this series a spin
on your devices to see if it fixes any issues you were seeing, too?

Thierry

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Re: [PATCH 1/3] dt-bindings: gpu: nvidia,gk20a: Allow a fuse clock after the reference clock

[Thierry Reding]

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On Tue, Oct 13, 2026 at 10:52:08AM -0400, Sasha Levin wrote:
> GM20B needs both its reference clock and the fuse clock while it is
> powered, so allow "fuse" as a fourth clock after "ref".
> 
> Assisted-by: LLM
> Signed-off-by: Sasha Levin <sashal@kernel.org>
> ---
>  Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml | 2 ++
>  1 file changed, 2 insertions(+)

Aaron, Diogo,

I'm fairly sure I remember at least one of you mentioning that GM20B
wasn't always working reliably. Would you mind giving this series a spin
on your devices to see if it fixes any issues you were seeing, too?

Thierry

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