* FAILED: patch "[PATCH] arm64: errata: Add Cortex-A725 erratum 3821522 workaround" failed to apply to 6.1-stable tree @ 2026-10-05 10:24 gregkh 2026-10-06 8:31 ` [PATCH 6.1.y] arm64: errata: Add Cortex-A725 erratum 3821522 workaround Sasha Levin 2026-10-06 12:32 ` [PATCH 6.1.y v2 1/2] arm64: errata: Factor out broken AMU const counter cap Beata Michalska 0 siblings, 2 replies; 7+ messages in thread From: gregkh @ 2026-10-05 10:24 UTC (permalink / raw) To: beata.michalska, vladimir.murzin, will; +Cc: stable The patch below does not apply to the 6.1-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <stable@vger.kernel.org>. To reproduce the conflict and resubmit, you may use the following commands: git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.1.y git checkout FETCH_HEAD git cherry-pick -x 45f7304679875eb000d67e194090ee7abd05c89c # <resolve conflicts, build, test, etc.> git commit -s git send-email --to '<stable@vger.kernel.org>' --in-reply-to '2026100502-outtakes-dragonfly-ead9@gregkh' --subject-prefix 'PATCH 6.1.y' 'HEAD^..' Possible dependencies: thanks, greg k-h ------------------ original commit in Linus's tree ------------------ From 45f7304679875eb000d67e194090ee7abd05c89c Mon Sep 17 00:00:00 2001 From: Beata Michalska <beata.michalska@arm.com> Date: Thu, 1 Oct 2026 11:00:32 +0200 Subject: [PATCH] arm64: errata: Add Cortex-A725 erratum 3821522 workaround Cortex-A725 erratum 3821522 affects the CNT_CYCLES event, which can incur a significant increment error when a CPU enters and subsequently exits WFE or WFI, and may no longer track the system counter frequency. The AMEVCNTR01_EL0 counter is used as the AMU constant counter for frequency invariance and CPPC FFH feedback counters. Wire the affected Cortex-A725 range into the shared broken AMU constant-counter capability so the affected counter is treated as unavailable by returning zero in the AMU counter paths. This prevents the broken counter from being used as a reference source. The erratum can also affect PMUv3 users of the CNT_CYCLES event, but this workaround intentionally does not change PMU event handling. Hiding or rejecting the PMU event from the erratum code would change the perf-visible PMU event interface, including raw event selection, and would need a separate PMU-specific approach rather than being folded into the AMU reference-counter workaround. Cc: stable@vger.kernel.org Signed-off-by: Beata Michalska <beata.michalska@arm.com> Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Will Deacon <will@kernel.org> diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst index ac3248b9f2f3..99a1eb4b833d 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -174,6 +174,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A725 | #3821522 | ARM64_ERRATUM_3821522 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X1 | #1502854 | N/A | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 | diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 3b6c052d46a1..cab741a695f5 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1081,6 +1081,28 @@ config ARM64_ERRATUM_2645198 If unsure, say Y. +config ARM64_ERRATUM_3821522 + bool "Cortex-A725: 3821522: workaround for possible CNT_CYCLES increment error due to WFE/WFI" + depends on ARM64_AMU_EXTN + select ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT + default y + help + This option adds the workaround for ARM Cortex-A725 erratum 3821522. + + On affected A725 cores, the CNT_CYCLES event may incur a significant + increment error when entering and subsequently exiting WFx. + As a result, the CNT_CYCLES may diverge from the system counter + frequency at which it is expected to increment. + This renders the AMU counter AMEVCNTR01, that implements CNT_CYCLES, + being unreliable and unsuitable for use. + + Since there is no hardware workaround, reads of the affected CNT_CYCLES + counter return 0 in the relevant paths. This causes users of the counter + to treat it as unavailable and is functionally equivalent to firmware + disabling the affected counter. + + If unsure, say Y. + config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD bool diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index dbd70728a9bd..e0c09402540c 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -389,6 +389,10 @@ static const struct midr_range workaround_amu_constcnt_list[] = { #ifdef CONFIG_ARM64_ERRATUM_2457168 /* Cortex-A510 r0p0-r1p1 */ MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), +#endif +#ifdef CONFIG_ARM64_ERRATUM_3821522 + /* Cortex-A725 r0p0 - r0p2 */ + MIDR_RANGE(MIDR_CORTEX_A725, 0, 0, 0, 2), #endif {} }; diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 214d153cba6e..806373aac3db 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -395,10 +395,11 @@ static void cpu_read_corecnt(void *val) static void cpu_read_constcnt(void *val) { /* - * Return 0 if the current CPU is affected by erratum 2457168. A value - * of 0 is also returned if the current CPU does not support AMUs or if - * the counter is disabled. A return value of 0 at counter read is - * properly handled as an error case by the users of the counter. + * Return 0 if the current CPU is affected by a HW erratum. + * A value of 0 is also returned if the current CPU does not + * support AMUs or if the counter is disabled. A return + * value of 0 at counter read is properly handled as an error + * case by the users of the counter. */ *(u64 *)val = this_cpu_has_cap(ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT) ? 0UL : read_constcnt(); ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 6.1.y] arm64: errata: Add Cortex-A725 erratum 3821522 workaround 2026-10-05 10:24 FAILED: patch "[PATCH] arm64: errata: Add Cortex-A725 erratum 3821522 workaround" failed to apply to 6.1-stable tree gregkh @ 2026-10-06 8:31 ` Sasha Levin 2026-10-06 8:53 ` Beata Michalska 2026-10-06 12:32 ` [PATCH 6.1.y v2 1/2] arm64: errata: Factor out broken AMU const counter cap Beata Michalska 1 sibling, 1 reply; 7+ messages in thread From: Sasha Levin @ 2026-10-06 8:31 UTC (permalink / raw) To: stable; +Cc: Beata Michalska, Vladimir Murzin, Will Deacon, Sasha Levin From: Beata Michalska <beata.michalska@arm.com> [ Upstream commit 45f7304679875eb000d67e194090ee7abd05c89c ] Cortex-A725 erratum 3821522 affects the CNT_CYCLES event, which can incur a significant increment error when a CPU enters and subsequently exits WFE or WFI, and may no longer track the system counter frequency. The AMEVCNTR01_EL0 counter is used as the AMU constant counter for frequency invariance and CPPC FFH feedback counters. Wire the affected Cortex-A725 range into the shared broken AMU constant-counter capability so the affected counter is treated as unavailable by returning zero in the AMU counter paths. This prevents the broken counter from being used as a reference source. The erratum can also affect PMUv3 users of the CNT_CYCLES event, but this workaround intentionally does not change PMU event handling. Hiding or rejecting the PMU event from the erratum code would change the perf-visible PMU event interface, including raw event selection, and would need a separate PMU-specific approach rather than being folded into the AMU reference-counter workaround. Cc: stable@vger.kernel.org Signed-off-by: Beata Michalska <beata.michalska@arm.com> Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Will Deacon <will@kernel.org> [ sashal: Reused ARM64_WORKAROUND_2457168 in place of the unavailable generic AMU capability. ] Signed-off-by: Sasha Levin <sashal@kernel.org> --- Documentation/arm64/silicon-errata.rst | 2 ++ arch/arm64/Kconfig | 21 +++++++++++++++++++++ arch/arm64/kernel/cpu_errata.c | 24 +++++++++++++++++++----- arch/arm64/kernel/topology.c | 9 +++++---- 4 files changed, 47 insertions(+), 9 deletions(-) diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst index fe7b90ac52d7b..74ae9e4f637a7 100644 --- a/Documentation/arm64/silicon-errata.rst +++ b/Documentation/arm64/silicon-errata.rst @@ -155,6 +155,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A725 | #3821522 | ARM64_ERRATUM_3821522 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X1 | #4193791 | ARM64_ERRATUM_4118414 | diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 9cb8867eb1205..314a9ac22be54 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -983,6 +983,27 @@ config ARM64_ERRATUM_2457168 If unsure, say Y. +config ARM64_ERRATUM_3821522 + bool "Cortex-A725: 3821522: workaround for possible CNT_CYCLES increment error due to WFE/WFI" + depends on ARM64_AMU_EXTN + default y + help + This option adds the workaround for ARM Cortex-A725 erratum 3821522. + + On affected A725 cores, the CNT_CYCLES event may incur a significant + increment error when entering and subsequently exiting WFx. + As a result, the CNT_CYCLES may diverge from the system counter + frequency at which it is expected to increment. + This renders the AMU counter AMEVCNTR01, that implements CNT_CYCLES, + being unreliable and unsuitable for use. + + Since there is no hardware workaround, reads of the affected CNT_CYCLES + counter return 0 in the relevant paths. This causes users of the counter + to treat it as unavailable and is functionally equivalent to firmware + disabling the affected counter. + + If unsure, say Y. + config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD bool diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index cff85a371c353..fbc80f64f3eeb 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -275,6 +275,21 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { }; #endif +#if defined(CONFIG_ARM64_ERRATUM_2457168) || \ + defined(CONFIG_ARM64_ERRATUM_3821522) +static const struct midr_range workaround_amu_constcnt_list[] = { +#ifdef CONFIG_ARM64_ERRATUM_2457168 + /* Cortex-A510 r0p0-r1p1 */ + MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), +#endif +#ifdef CONFIG_ARM64_ERRATUM_3821522 + /* Cortex-A725 r0p0 - r0p2 */ + MIDR_RANGE(MIDR_CORTEX_A725, 0, 0, 0, 2), +#endif + {} +}; +#endif + #ifdef CONFIG_CAVIUM_ERRATUM_23154 static const struct midr_range cavium_erratum_23154_cpus[] = { MIDR_ALL_VERSIONS(MIDR_THUNDERX), @@ -737,14 +752,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) }, #endif -#ifdef CONFIG_ARM64_ERRATUM_2457168 +#if defined(CONFIG_ARM64_ERRATUM_2457168) || \ + defined(CONFIG_ARM64_ERRATUM_3821522) { - .desc = "ARM erratum 2457168", + .desc = "Broken AMU AMEVCNTR01 (const counter)", .capability = ARM64_WORKAROUND_2457168, .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, - - /* Cortex-A510 r0p0-r1p1 */ - CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1) + CAP_MIDR_RANGE_LIST(workaround_amu_constcnt_list) }, #endif #ifdef CONFIG_ARM64_ERRATUM_2038923 diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 817d788cd8666..575d0f9a76870 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -268,10 +268,11 @@ static void cpu_read_corecnt(void *val) static void cpu_read_constcnt(void *val) { /* - * Return 0 if the current CPU is affected by erratum 2457168. A value - * of 0 is also returned if the current CPU does not support AMUs or if - * the counter is disabled. A return value of 0 at counter read is - * properly handled as an error case by the users of the counter. + * Return 0 if the current CPU is affected by a HW erratum. + * A value of 0 is also returned if the current CPU does not + * support AMUs or if the counter is disabled. A return + * value of 0 at counter read is properly handled as an error + * case by the users of the counter. */ *(u64 *)val = this_cpu_has_cap(ARM64_WORKAROUND_2457168) ? 0UL : read_constcnt(); -- 2.53.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 6.1.y] arm64: errata: Add Cortex-A725 erratum 3821522 workaround 2026-10-06 8:31 ` [PATCH 6.1.y] arm64: errata: Add Cortex-A725 erratum 3821522 workaround Sasha Levin @ 2026-10-06 8:53 ` Beata Michalska 2026-10-06 13:31 ` Beata Michalska 0 siblings, 1 reply; 7+ messages in thread From: Beata Michalska @ 2026-10-06 8:53 UTC (permalink / raw) To: Sasha Levin; +Cc: stable, Vladimir Murzin, Will Deacon This one is also missing/mixing things. Do let me know if you want me to make the backport. --- BR Beata On Tue, Oct 06, 2026 at 04:31:46AM -0400, Sasha Levin wrote: > From: Beata Michalska <beata.michalska@arm.com> > > [ Upstream commit 45f7304679875eb000d67e194090ee7abd05c89c ] > > Cortex-A725 erratum 3821522 affects the CNT_CYCLES event, which can > incur a significant increment error when a CPU enters and subsequently > exits WFE or WFI, and may no longer track the system counter > frequency. > > The AMEVCNTR01_EL0 counter is used as the AMU constant counter for > frequency invariance and CPPC FFH feedback counters. Wire the affected > Cortex-A725 range into the shared broken AMU constant-counter capability > so the affected counter is treated as unavailable by returning zero in > the AMU counter paths. This prevents the broken counter from being used > as a reference source. > > The erratum can also affect PMUv3 users of the CNT_CYCLES event, > but this workaround intentionally does not change PMU event handling. > Hiding or rejecting the PMU event from the erratum code would change > the perf-visible PMU event interface, including raw event selection, > and would need a separate PMU-specific approach rather than being > folded into the AMU reference-counter workaround. > > Cc: stable@vger.kernel.org > Signed-off-by: Beata Michalska <beata.michalska@arm.com> > Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com> > Signed-off-by: Will Deacon <will@kernel.org> > [ sashal: Reused ARM64_WORKAROUND_2457168 in place of the unavailable generic AMU capability. ] > Signed-off-by: Sasha Levin <sashal@kernel.org> > --- > Documentation/arm64/silicon-errata.rst | 2 ++ > arch/arm64/Kconfig | 21 +++++++++++++++++++++ > arch/arm64/kernel/cpu_errata.c | 24 +++++++++++++++++++----- > arch/arm64/kernel/topology.c | 9 +++++---- > 4 files changed, 47 insertions(+), 9 deletions(-) > > diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst > index fe7b90ac52d7b..74ae9e4f637a7 100644 > --- a/Documentation/arm64/silicon-errata.rst > +++ b/Documentation/arm64/silicon-errata.rst > @@ -155,6 +155,8 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-A725 | #3821522 | ARM64_ERRATUM_3821522 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-X1 | #4193791 | ARM64_ERRATUM_4118414 | > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 9cb8867eb1205..314a9ac22be54 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -983,6 +983,27 @@ config ARM64_ERRATUM_2457168 > > If unsure, say Y. > > +config ARM64_ERRATUM_3821522 > + bool "Cortex-A725: 3821522: workaround for possible CNT_CYCLES increment error due to WFE/WFI" > + depends on ARM64_AMU_EXTN > + default y > + help > + This option adds the workaround for ARM Cortex-A725 erratum 3821522. > + > + On affected A725 cores, the CNT_CYCLES event may incur a significant > + increment error when entering and subsequently exiting WFx. > + As a result, the CNT_CYCLES may diverge from the system counter > + frequency at which it is expected to increment. > + This renders the AMU counter AMEVCNTR01, that implements CNT_CYCLES, > + being unreliable and unsuitable for use. > + > + Since there is no hardware workaround, reads of the affected CNT_CYCLES > + counter return 0 in the relevant paths. This causes users of the counter > + to treat it as unavailable and is functionally equivalent to firmware > + disabling the affected counter. > + > + If unsure, say Y. > + > config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD > bool > > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index cff85a371c353..fbc80f64f3eeb 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -275,6 +275,21 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { > }; > #endif > > +#if defined(CONFIG_ARM64_ERRATUM_2457168) || \ > + defined(CONFIG_ARM64_ERRATUM_3821522) > +static const struct midr_range workaround_amu_constcnt_list[] = { > +#ifdef CONFIG_ARM64_ERRATUM_2457168 > + /* Cortex-A510 r0p0-r1p1 */ > + MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), > +#endif > +#ifdef CONFIG_ARM64_ERRATUM_3821522 > + /* Cortex-A725 r0p0 - r0p2 */ > + MIDR_RANGE(MIDR_CORTEX_A725, 0, 0, 0, 2), > +#endif > + {} > +}; > +#endif > + > #ifdef CONFIG_CAVIUM_ERRATUM_23154 > static const struct midr_range cavium_erratum_23154_cpus[] = { > MIDR_ALL_VERSIONS(MIDR_THUNDERX), > @@ -737,14 +752,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { > ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) > }, > #endif > -#ifdef CONFIG_ARM64_ERRATUM_2457168 > +#if defined(CONFIG_ARM64_ERRATUM_2457168) || \ > + defined(CONFIG_ARM64_ERRATUM_3821522) > { > - .desc = "ARM erratum 2457168", > + .desc = "Broken AMU AMEVCNTR01 (const counter)", > .capability = ARM64_WORKAROUND_2457168, > .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, > - > - /* Cortex-A510 r0p0-r1p1 */ > - CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1) > + CAP_MIDR_RANGE_LIST(workaround_amu_constcnt_list) > }, > #endif > #ifdef CONFIG_ARM64_ERRATUM_2038923 > diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c > index 817d788cd8666..575d0f9a76870 100644 > --- a/arch/arm64/kernel/topology.c > +++ b/arch/arm64/kernel/topology.c > @@ -268,10 +268,11 @@ static void cpu_read_corecnt(void *val) > static void cpu_read_constcnt(void *val) > { > /* > - * Return 0 if the current CPU is affected by erratum 2457168. A value > - * of 0 is also returned if the current CPU does not support AMUs or if > - * the counter is disabled. A return value of 0 at counter read is > - * properly handled as an error case by the users of the counter. > + * Return 0 if the current CPU is affected by a HW erratum. > + * A value of 0 is also returned if the current CPU does not > + * support AMUs or if the counter is disabled. A return > + * value of 0 at counter read is properly handled as an error > + * case by the users of the counter. > */ > *(u64 *)val = this_cpu_has_cap(ARM64_WORKAROUND_2457168) ? > 0UL : read_constcnt(); > -- > 2.53.0 > ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 6.1.y] arm64: errata: Add Cortex-A725 erratum 3821522 workaround 2026-10-06 8:53 ` Beata Michalska @ 2026-10-06 13:31 ` Beata Michalska 0 siblings, 0 replies; 7+ messages in thread From: Beata Michalska @ 2026-10-06 13:31 UTC (permalink / raw) To: Sasha Levin; +Cc: stable, Vladimir Murzin, Will Deacon On Tue, Oct 06, 2026 at 10:53:32AM +0200, Beata Michalska wrote: > This one is also missing/mixing things. > Do let me know if you want me to make the backport. > Posted as a reply to: https://lore.kernel.org/stable/2026100502-outtakes-dragonfly-ead9@gregkh/T/#t --- BR Beata > --- > BR > Beata > On Tue, Oct 06, 2026 at 04:31:46AM -0400, Sasha Levin wrote: > > From: Beata Michalska <beata.michalska@arm.com> > > > > [ Upstream commit 45f7304679875eb000d67e194090ee7abd05c89c ] > > > > Cortex-A725 erratum 3821522 affects the CNT_CYCLES event, which can > > incur a significant increment error when a CPU enters and subsequently > > exits WFE or WFI, and may no longer track the system counter > > frequency. > > > > The AMEVCNTR01_EL0 counter is used as the AMU constant counter for > > frequency invariance and CPPC FFH feedback counters. Wire the affected > > Cortex-A725 range into the shared broken AMU constant-counter capability > > so the affected counter is treated as unavailable by returning zero in > > the AMU counter paths. This prevents the broken counter from being used > > as a reference source. > > > > The erratum can also affect PMUv3 users of the CNT_CYCLES event, > > but this workaround intentionally does not change PMU event handling. > > Hiding or rejecting the PMU event from the erratum code would change > > the perf-visible PMU event interface, including raw event selection, > > and would need a separate PMU-specific approach rather than being > > folded into the AMU reference-counter workaround. > > > > Cc: stable@vger.kernel.org > > Signed-off-by: Beata Michalska <beata.michalska@arm.com> > > Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com> > > Signed-off-by: Will Deacon <will@kernel.org> > > [ sashal: Reused ARM64_WORKAROUND_2457168 in place of the unavailable generic AMU capability. ] > > Signed-off-by: Sasha Levin <sashal@kernel.org> > > --- > > Documentation/arm64/silicon-errata.rst | 2 ++ > > arch/arm64/Kconfig | 21 +++++++++++++++++++++ > > arch/arm64/kernel/cpu_errata.c | 24 +++++++++++++++++++----- > > arch/arm64/kernel/topology.c | 9 +++++---- > > 4 files changed, 47 insertions(+), 9 deletions(-) > > > > diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst > > index fe7b90ac52d7b..74ae9e4f637a7 100644 > > --- a/Documentation/arm64/silicon-errata.rst > > +++ b/Documentation/arm64/silicon-errata.rst > > @@ -155,6 +155,8 @@ stable kernels. > > +----------------+-----------------+-----------------+-----------------------------+ > > | ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 | > > +----------------+-----------------+-----------------+-----------------------------+ > > +| ARM | Cortex-A725 | #3821522 | ARM64_ERRATUM_3821522 | > > ++----------------+-----------------+-----------------+-----------------------------+ > > | ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 | > > +----------------+-----------------+-----------------+-----------------------------+ > > | ARM | Cortex-X1 | #4193791 | ARM64_ERRATUM_4118414 | > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > > index 9cb8867eb1205..314a9ac22be54 100644 > > --- a/arch/arm64/Kconfig > > +++ b/arch/arm64/Kconfig > > @@ -983,6 +983,27 @@ config ARM64_ERRATUM_2457168 > > > > If unsure, say Y. > > > > +config ARM64_ERRATUM_3821522 > > + bool "Cortex-A725: 3821522: workaround for possible CNT_CYCLES increment error due to WFE/WFI" > > + depends on ARM64_AMU_EXTN > > + default y > > + help > > + This option adds the workaround for ARM Cortex-A725 erratum 3821522. > > + > > + On affected A725 cores, the CNT_CYCLES event may incur a significant > > + increment error when entering and subsequently exiting WFx. > > + As a result, the CNT_CYCLES may diverge from the system counter > > + frequency at which it is expected to increment. > > + This renders the AMU counter AMEVCNTR01, that implements CNT_CYCLES, > > + being unreliable and unsuitable for use. > > + > > + Since there is no hardware workaround, reads of the affected CNT_CYCLES > > + counter return 0 in the relevant paths. This causes users of the counter > > + to treat it as unavailable and is functionally equivalent to firmware > > + disabling the affected counter. > > + > > + If unsure, say Y. > > + > > config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD > > bool > > > > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > > index cff85a371c353..fbc80f64f3eeb 100644 > > --- a/arch/arm64/kernel/cpu_errata.c > > +++ b/arch/arm64/kernel/cpu_errata.c > > @@ -275,6 +275,21 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { > > }; > > #endif > > > > +#if defined(CONFIG_ARM64_ERRATUM_2457168) || \ > > + defined(CONFIG_ARM64_ERRATUM_3821522) > > +static const struct midr_range workaround_amu_constcnt_list[] = { > > +#ifdef CONFIG_ARM64_ERRATUM_2457168 > > + /* Cortex-A510 r0p0-r1p1 */ > > + MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), > > +#endif > > +#ifdef CONFIG_ARM64_ERRATUM_3821522 > > + /* Cortex-A725 r0p0 - r0p2 */ > > + MIDR_RANGE(MIDR_CORTEX_A725, 0, 0, 0, 2), > > +#endif > > + {} > > +}; > > +#endif > > + > > #ifdef CONFIG_CAVIUM_ERRATUM_23154 > > static const struct midr_range cavium_erratum_23154_cpus[] = { > > MIDR_ALL_VERSIONS(MIDR_THUNDERX), > > @@ -737,14 +752,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { > > ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) > > }, > > #endif > > -#ifdef CONFIG_ARM64_ERRATUM_2457168 > > +#if defined(CONFIG_ARM64_ERRATUM_2457168) || \ > > + defined(CONFIG_ARM64_ERRATUM_3821522) > > { > > - .desc = "ARM erratum 2457168", > > + .desc = "Broken AMU AMEVCNTR01 (const counter)", > > .capability = ARM64_WORKAROUND_2457168, > > .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, > > - > > - /* Cortex-A510 r0p0-r1p1 */ > > - CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1) > > + CAP_MIDR_RANGE_LIST(workaround_amu_constcnt_list) > > }, > > #endif > > #ifdef CONFIG_ARM64_ERRATUM_2038923 > > diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c > > index 817d788cd8666..575d0f9a76870 100644 > > --- a/arch/arm64/kernel/topology.c > > +++ b/arch/arm64/kernel/topology.c > > @@ -268,10 +268,11 @@ static void cpu_read_corecnt(void *val) > > static void cpu_read_constcnt(void *val) > > { > > /* > > - * Return 0 if the current CPU is affected by erratum 2457168. A value > > - * of 0 is also returned if the current CPU does not support AMUs or if > > - * the counter is disabled. A return value of 0 at counter read is > > - * properly handled as an error case by the users of the counter. > > + * Return 0 if the current CPU is affected by a HW erratum. > > + * A value of 0 is also returned if the current CPU does not > > + * support AMUs or if the counter is disabled. A return > > + * value of 0 at counter read is properly handled as an error > > + * case by the users of the counter. > > */ > > *(u64 *)val = this_cpu_has_cap(ARM64_WORKAROUND_2457168) ? > > 0UL : read_constcnt(); > > -- > > 2.53.0 > > ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 6.1.y v2 1/2] arm64: errata: Factor out broken AMU const counter cap 2026-10-05 10:24 FAILED: patch "[PATCH] arm64: errata: Add Cortex-A725 erratum 3821522 workaround" failed to apply to 6.1-stable tree gregkh 2026-10-06 8:31 ` [PATCH 6.1.y] arm64: errata: Add Cortex-A725 erratum 3821522 workaround Sasha Levin @ 2026-10-06 12:32 ` Beata Michalska 2026-10-06 12:32 ` [PATCH 6.1.y v2 2/2] arm64: errata: Add Cortex-A725 erratum 3821522 workaround Beata Michalska 2026-10-07 21:03 ` [PATCH 6.1.y v2 1/2] arm64: errata: Factor out broken AMU const counter cap Sasha Levin 1 sibling, 2 replies; 7+ messages in thread From: Beata Michalska @ 2026-10-06 12:32 UTC (permalink / raw) To: stable Move the workaround from the erratum 2457168-specific cpucap to a generic broken AMU constant-counter one. This keeps the existing Cortex-A510 handling unchanged while allowing other errata with similar AMU constant counter issue to share the capability bit and call sites. Signed-off-by: Beata Michalska <beata.michalska@arm.com> Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit 573371caf7aea8582212da81dcead2c3f48fac4b) Skipped comment updated on amu_read_core_const_ctrs, as that functionality is not available here. Otherwise unmodified. Signed-off-by: Beata Michalska <beata.michalska@arm.com> --- arch/arm64/Kconfig | 8 ++++++++ arch/arm64/kernel/cpu_errata.c | 20 ++++++++++++++------ arch/arm64/kernel/cpufeature.c | 2 +- arch/arm64/kernel/topology.c | 2 +- arch/arm64/tools/cpucaps | 2 +- 5 files changed, 25 insertions(+), 9 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 9cb8867eb120..370bde2b2b07 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -966,9 +966,17 @@ config ARM64_ERRATUM_1902691 If unsure, say Y. +config ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT + bool + # Targeting errata affecting AMEVCNTR01, the AMU constant counter. + # On affected CPUs the counter may not increment at the expected rate, + # making it unreliable. As a result, AMU users should treat it as + # unavailable rather than relying on misleading counter values. + config ARM64_ERRATUM_2457168 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" depends on ARM64_AMU_EXTN + select ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT default y help This option adds the workaround for ARM Cortex-A510 erratum 2457168. diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index cff85a371c35..518e3b6877b5 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -275,6 +275,16 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { }; #endif +#ifdef CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT +static const struct midr_range workaround_amu_constcnt_list[] = { +#ifdef CONFIG_ARM64_ERRATUM_2457168 + /* Cortex-A510 r0p0-r1p1 */ + MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), +#endif + {} +}; +#endif /* CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT */ + #ifdef CONFIG_CAVIUM_ERRATUM_23154 static const struct midr_range cavium_erratum_23154_cpus[] = { MIDR_ALL_VERSIONS(MIDR_THUNDERX), @@ -737,14 +747,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) }, #endif -#ifdef CONFIG_ARM64_ERRATUM_2457168 +#ifdef CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT { - .desc = "ARM erratum 2457168", - .capability = ARM64_WORKAROUND_2457168, + .desc = "Broken AMU AMEVCNTR01 (const counter)", + .capability = ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT, .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, - - /* Cortex-A510 r0p0-r1p1 */ - CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1) + CAP_MIDR_RANGE_LIST(workaround_amu_constcnt_list) }, #endif #ifdef CONFIG_ARM64_ERRATUM_2038923 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 547c47358133..467737615bf3 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1907,7 +1907,7 @@ static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) cpumask_set_cpu(smp_processor_id(), &amu_cpus); /* 0 reference values signal broken/disabled counters */ - if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) + if (!this_cpu_has_cap(ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT)) update_freq_counters_refs(); } } diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 817d788cd866..d61d1afdee15 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -273,7 +273,7 @@ static void cpu_read_constcnt(void *val) * the counter is disabled. A return value of 0 at counter read is * properly handled as an error case by the users of the counter. */ - *(u64 *)val = this_cpu_has_cap(ARM64_WORKAROUND_2457168) ? + *(u64 *)val = this_cpu_has_cap(ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT) ? 0UL : read_constcnt(); } diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index f5c9a4f5f722..f609e8d93937 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -69,7 +69,6 @@ WORKAROUND_1902691 WORKAROUND_2038923 WORKAROUND_2064142 WORKAROUND_2077057 -WORKAROUND_2457168 WORKAROUND_2658417 WORKAROUND_AMPERE_AC03_CPU_38 WORKAROUND_TRBE_OVERWRITE_FILL_MODE @@ -88,3 +87,4 @@ WORKAROUND_REPEAT_TLBI WORKAROUND_SPECULATIVE_AT WORKAROUND_SPECULATIVE_SSBS WORKAROUND_SPECULATIVE_UNPRIV_LOAD +WORKAROUND_BROKEN_AMU_CONSTCNT -- 2.43.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 6.1.y v2 2/2] arm64: errata: Add Cortex-A725 erratum 3821522 workaround 2026-10-06 12:32 ` [PATCH 6.1.y v2 1/2] arm64: errata: Factor out broken AMU const counter cap Beata Michalska @ 2026-10-06 12:32 ` Beata Michalska 2026-10-07 21:03 ` [PATCH 6.1.y v2 1/2] arm64: errata: Factor out broken AMU const counter cap Sasha Levin 1 sibling, 0 replies; 7+ messages in thread From: Beata Michalska @ 2026-10-06 12:32 UTC (permalink / raw) To: stable Cortex-A725 erratum 3821522 affects the CNT_CYCLES event, which can incur a significant increment error when a CPU enters and subsequently exits WFE or WFI, and may no longer track the system counter frequency. The AMEVCNTR01_EL0 counter is used as the AMU constant counter for frequency invariance and CPPC FFH feedback counters. Wire the affected Cortex-A725 range into the shared broken AMU constant-counter capability so the affected counter is treated as unavailable by returning zero in the AMU counter paths. This prevents the broken counter from being used as a reference source. The erratum can also affect PMUv3 users of the CNT_CYCLES event, but this workaround intentionally does not change PMU event handling. Hiding or rejecting the PMU event from the erratum code would change the perf-visible PMU event interface, including raw event selection, and would need a separate PMU-specific approach rather than being folded into the AMU reference-counter workaround. Cc: stable@vger.kernel.org Signed-off-by: Beata Michalska <beata.michalska@arm.com> Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit 45f7304679875eb000d67e194090ee7abd05c89c) Signed-off-by: Beata Michalska <beata.michalska@arm.com> --- Documentation/arm64/silicon-errata.rst | 2 ++ arch/arm64/Kconfig | 22 ++++++++++++++++++++++ arch/arm64/kernel/cpu_errata.c | 4 ++++ arch/arm64/kernel/topology.c | 9 +++++---- 4 files changed, 33 insertions(+), 4 deletions(-) diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst index fe7b90ac52d7..74ae9e4f637a 100644 --- a/Documentation/arm64/silicon-errata.rst +++ b/Documentation/arm64/silicon-errata.rst @@ -155,6 +155,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A725 | #3821522 | ARM64_ERRATUM_3821522 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X1 | #4193791 | ARM64_ERRATUM_4118414 | diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 370bde2b2b07..1b8ee28f2383 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -991,6 +991,28 @@ config ARM64_ERRATUM_2457168 If unsure, say Y. +config ARM64_ERRATUM_3821522 + bool "Cortex-A725: 3821522: workaround for possible CNT_CYCLES increment error due to WFE/WFI" + depends on ARM64_AMU_EXTN + select ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT + default y + help + This option adds the workaround for ARM Cortex-A725 erratum 3821522. + + On affected A725 cores, the CNT_CYCLES event may incur a significant + increment error when entering and subsequently exiting WFx. + As a result, the CNT_CYCLES may diverge from the system counter + frequency at which it is expected to increment. + This renders the AMU counter AMEVCNTR01, that implements CNT_CYCLES, + being unreliable and unsuitable for use. + + Since there is no hardware workaround, reads of the affected CNT_CYCLES + counter return 0 in the relevant paths. This causes users of the counter + to treat it as unavailable and is functionally equivalent to firmware + disabling the affected counter. + + If unsure, say Y. + config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD bool diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 518e3b6877b5..660b3ff16ebc 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -280,6 +280,10 @@ static const struct midr_range workaround_amu_constcnt_list[] = { #ifdef CONFIG_ARM64_ERRATUM_2457168 /* Cortex-A510 r0p0-r1p1 */ MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), +#endif +#ifdef CONFIG_ARM64_ERRATUM_3821522 + /* Cortex-A725 r0p0 - r0p2 */ + MIDR_RANGE(MIDR_CORTEX_A725, 0, 0, 0, 2), #endif {} }; diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index d61d1afdee15..61df0918585b 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -268,10 +268,11 @@ static void cpu_read_corecnt(void *val) static void cpu_read_constcnt(void *val) { /* - * Return 0 if the current CPU is affected by erratum 2457168. A value - * of 0 is also returned if the current CPU does not support AMUs or if - * the counter is disabled. A return value of 0 at counter read is - * properly handled as an error case by the users of the counter. + * Return 0 if the current CPU is affected by a HW erratum. + * A value of 0 is also returned if the current CPU does not + * support AMUs or if the counter is disabled. A return + * value of 0 at counter read is properly handled as an error + * case by the users of the counter. */ *(u64 *)val = this_cpu_has_cap(ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT) ? 0UL : read_constcnt(); -- 2.43.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 6.1.y v2 1/2] arm64: errata: Factor out broken AMU const counter cap 2026-10-06 12:32 ` [PATCH 6.1.y v2 1/2] arm64: errata: Factor out broken AMU const counter cap Beata Michalska 2026-10-06 12:32 ` [PATCH 6.1.y v2 2/2] arm64: errata: Add Cortex-A725 erratum 3821522 workaround Beata Michalska @ 2026-10-07 21:03 ` Sasha Levin 1 sibling, 0 replies; 7+ messages in thread From: Sasha Levin @ 2026-10-07 21:03 UTC (permalink / raw) To: stable; +Cc: Sasha Levin, Beata Michalska > Move the workaround from the erratum 2457168-specific cpucap to a generic > broken AMU constant-counter one. Queued the series for 6.1, thanks. -- Thanks, Sasha ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2026-10-07 21:04 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-10-05 10:24 FAILED: patch "[PATCH] arm64: errata: Add Cortex-A725 erratum 3821522 workaround" failed to apply to 6.1-stable tree gregkh 2026-10-06 8:31 ` [PATCH 6.1.y] arm64: errata: Add Cortex-A725 erratum 3821522 workaround Sasha Levin 2026-10-06 8:53 ` Beata Michalska 2026-10-06 13:31 ` Beata Michalska 2026-10-06 12:32 ` [PATCH 6.1.y v2 1/2] arm64: errata: Factor out broken AMU const counter cap Beata Michalska 2026-10-06 12:32 ` [PATCH 6.1.y v2 2/2] arm64: errata: Add Cortex-A725 erratum 3821522 workaround Beata Michalska 2026-10-07 21:03 ` [PATCH 6.1.y v2 1/2] arm64: errata: Factor out broken AMU const counter cap Sasha Levin
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