Re: [PATCH v8 13/15] drm/xe/hwmon: Get PCIe temperature sensor offset from xe info

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Tue, Oct 06, 2026 at 09:05:32AM +0530, Karthik Poosa wrote:
> Store the PCIe temperature sensor byte offset in xe device info and derive
> the thermal mailbox group and byte from it. Read the configured offset
> inside get_pcie_temp().
> 
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_device_types.h |  2 ++
>  drivers/gpu/drm/xe/xe_hwmon.c        | 14 ++++++++------
>  drivers/gpu/drm/xe/xe_pci.c          |  4 ++++
>  drivers/gpu/drm/xe/xe_pci_types.h    |  1 +
>  drivers/gpu/drm/xe/xe_pcode_api.h    |  2 --
>  5 files changed, 15 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 161ba2b27f47..4b2da72ed136 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -164,6 +164,8 @@ struct xe_device {
>  		u8 vm_max_level;
>  		/** @info.va_bits: Maximum bits of a virtual address */
>  		u8 va_bits;
> +		/** @info.pcie_temp_sensor_offset: PCIe sensor byte offset in READ_THERMAL_DATA */
> +		u8 pcie_temp_sensor_offset;
>  
>  		/*
>  		 * Keep all flags below alphabetically sorted
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 7fe3ba422cc8..54b2fd29ccbe 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -1018,17 +1018,18 @@ static int get_pcie_temp(struct xe_hwmon *hwmon, long *val)
>  {
>  	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
>  	u32 data = 0;
> +	u32 group;
> +	u32 byte;
>  	int ret;
>  
> +	group = hwmon->xe->info.pcie_temp_sensor_offset / sizeof(data);
> +	byte = hwmon->xe->info.pcie_temp_sensor_offset % sizeof(data);
>  	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA,
> -						  PCIE_SENSOR_GROUP_ID), &data, NULL);
> +						  group), &data, NULL);
>  	if (ret)
>  		return ret;
>  
> -	/* Sensor offset is different for G21 */
> -	if (hwmon->xe->info.subplatform != XE_SUBPLATFORM_BATTLEMAGE_G21)
> -		data = REG_FIELD_GET(PCIE_SENSOR_MASK, data);
> -
> +	data >>= byte * BITS_PER_BYTE;
>  	data = REG_FIELD_GET(TEMP_MASK, data);
>  	if (!mbx_temp_valid(hwmon, data)) {
>  		drm_dbg(&hwmon->xe->drm, "PCIe temperature not available\n");
> @@ -1168,7 +1169,8 @@ static bool xe_hwmon_temp_probe(struct xe_hwmon *hwmon, int channel)
>  	case CHANNEL_MCTRL:
>  		return hwmon->temp.count && !get_mc_temp(hwmon, NULL);
>  	case CHANNEL_PCIE:
> -		return hwmon->temp.count && !get_pcie_temp(hwmon, NULL);
> +		return hwmon->temp.count &&
> +		       !get_pcie_temp(hwmon, NULL);
>  	default:
>  		return false;
>  	}
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index e754668100cf..1cbd49933b2c 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -421,6 +421,7 @@ static const struct xe_device_desc bmg_desc = {
>  	.has_flat_ccs = 1,
>  	.has_mbx_power_limits = true,
>  	.has_mbx_thermal_info = true,
> +	.pcie_temp_sensor_offset = 10,
>  	.has_gsc_nvm = 1,
>  	.has_heci_cscfi = 1,
>  	.has_i2c = true,
> @@ -793,6 +794,9 @@ static int xe_info_init_early(struct xe_device *xe,
>  	xe->info.va_bits = desc->va_bits;
>  	xe->info.vm_max_level = desc->vm_max_level;
>  	xe->info.vram_flags = desc->vram_flags;
> +	xe->info.pcie_temp_sensor_offset = desc->pcie_temp_sensor_offset;
> +	if (xe->info.subplatform == XE_SUBPLATFORM_BATTLEMAGE_G21)
> +		xe->info.pcie_temp_sensor_offset = 8;
>  
>  	xe->info.is_dgfx = desc->is_dgfx;
>  	xe->info.has_cached_pt = desc->has_cached_pt;
> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
> index ce0b0f6c5b18..a613bd4ed94c 100644
> --- a/drivers/gpu/drm/xe/xe_pci_types.h
> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> @@ -34,6 +34,7 @@ struct xe_device_desc {
>  	u8 va_bits;
>  	u8 vm_max_level;
>  	u8 vram_flags;
> +	u8 pcie_temp_sensor_offset;
>  
>  	u8 require_force_probe:1;
>  	u8 is_dgfx:1;
> diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
> index 94575c476e3d..00c4fc7d0124 100644
> --- a/drivers/gpu/drm/xe/xe_pcode_api.h
> +++ b/drivers/gpu/drm/xe/xe_pcode_api.h
> @@ -58,8 +58,6 @@
>  #define     READ_THERMAL_LIMITS			0x0
>  #define     READ_THERMAL_CONFIG			0x1
>  #define     READ_THERMAL_DATA			0x2
> -#define       PCIE_SENSOR_GROUP_ID		0x2
> -#define       PCIE_SENSOR_MASK			REG_GENMASK(31, 16)
>  
>  #define   PCODE_LATE_BINDING			0x5C
>  #define     GET_CAPABILITY_STATUS		0x0
> -- 
> 2.25.1
>