Re: [PATCH v3 2/2] drm/xe/nvm: define survivabilty partition

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Alexander Usyskin <alexander.usyskin@intel.com>
Cc: "Miquel Raynal" <miquel.raynal@bootlin.com>,
	"Richard Weinberger" <richard@nod.at>,
	"Vignesh Raghavendra" <vigneshr@ti.com>,
	"Matthew Brost" <matthew.brost@intel.com>,
	"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
	"David Airlie" <airlied@gmail.com>,
	"Simona Vetter" <simona@ffwll.ch>,
	linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
	intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
	"Menachem Adin" <menachem.adin@intel.com>
Subject: Re: [PATCH v3 2/2] drm/xe/nvm: define survivabilty partition
Date: Thu, 8 Oct 2026 12:43:27 -0400	[thread overview]
Message-ID: <asfIL5FsBKiL0sUx@intel.com> (raw)
In-Reply-To: <20260930-cri_surviv-v3-2-357aeed5fc60@intel.com>

On Wed, Sep 30, 2026 at 05:14:47PM +0300, Alexander Usyskin wrote:

typo in the subject, but I will fix while merging it.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> Define 8M survivability partition for CRI when
> storage is open for write override.
> 
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_nvm.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_nvm.c b/drivers/gpu/drm/xe/xe_nvm.c
> index 51a1a431ad85..783c3103a8a4 100644
> --- a/drivers/gpu/drm/xe/xe_nvm.c
> +++ b/drivers/gpu/drm/xe/xe_nvm.c
> @@ -56,10 +56,11 @@ static bool xe_nvm_non_posted_erase(struct xe_device *xe)
>  	}
>  }
>  
> -static bool xe_nvm_writable_override(struct xe_device *xe)
> +static bool xe_nvm_writable_override(struct xe_device *xe, size_t *survivability_size)
>  {
>  	struct xe_mmio *mmio = xe_root_tile_mmio(xe);
>  	bool writable_override;
> +	size_t s_size = 0;
>  	struct xe_reg reg;
>  	u32 test_bit, test_val;
>  
> @@ -68,6 +69,7 @@ static bool xe_nvm_writable_override(struct xe_device *xe)
>  		reg = PCODE_SCRATCH(0);
>  		test_bit = FDO_MODE;
>  		test_val = FDO_MODE;
> +		s_size = SZ_8M;
>  		break;
>  	case XE_BATTLEMAGE:
>  		reg = HECI_FWSTS2(DG2_GSC_HECI2_BASE);
> @@ -91,12 +93,17 @@ static bool xe_nvm_writable_override(struct xe_device *xe)
>  		break;
>  	default:
>  		drm_err(&xe->drm, "Unknown platform\n");
> +		*survivability_size = 0;
>  		return true;
>  	}
>  
>  	writable_override = (xe_mmio_read32(mmio, reg) & test_bit) == test_val;
> -	if (writable_override)
> +	if (writable_override) {
>  		drm_info(&xe->drm, "NVM access overridden by jumper\n");
> +		*survivability_size = s_size;
> +	} else {
> +		*survivability_size = 0;
> +	}
>  	return writable_override;
>  }
>  
> @@ -143,7 +150,7 @@ int xe_nvm_init(struct xe_device *xe)
>  	if (!nvm)
>  		return -ENOMEM;
>  
> -	nvm->writable_override = xe_nvm_writable_override(xe);
> +	nvm->writable_override = xe_nvm_writable_override(xe, &nvm->survivability_size);
>  	nvm->non_posted_erase = xe_nvm_non_posted_erase(xe);
>  	nvm->bar.parent = &pdev->resource[0];
>  	nvm->bar.start = GEN12_GUNIT_NVM_BASE + pdev->resource[0].start;
> 
> -- 
> 2.53.0
> 