From: Nicolin Chen <nicolinc@nvidia.com>
To: Zhenzhong Duan <zhenzhong.duan@intel.com>
Cc: <qemu-devel@nongnu.org>, <alex@shazbot.org>, <clg@redhat.com>,
<eric.auger@redhat.com>, <mst@redhat.com>, <jasowangio@gmail.com>,
<jgg@nvidia.com>, <skolothumtho@nvidia.com>,
<joao.m.martins@oracle.com>, <clement.mathieu--drif@bull.com>,
<kevin.tian@intel.com>, <yi.l.liu@intel.com>,
Xudong Hao <xudong.hao@intel.com>, <qemu-arm@nongnu.org>
Subject: Re: [PATCH v8 3/6] backends/iommufd: Extend iommufd_backend_alloc_hwpt() with fault_id
Date: Fri, 9 Oct 2026 13:26:38 -0700 [thread overview]
Message-ID: <aslN/uXOIuJKP42Q@nvidia.com> (raw)
In-Reply-To: <20261009090737.3930000-4-zhenzhong.duan@intel.com>
On Fri, Oct 09, 2026 at 05:07:33PM +0800, Zhenzhong Duan wrote:
> We should set flags IOMMU_HWPT_FAULT_ID_VALID when pass in a fault
> object id in the caller.
>
> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
> Reviewed-by: Clement Mathieu--Drif <clement.mathieu--drif@bull.com>
> Reviewed-by: Yi Liu <yi.l.liu@intel.com>
> Tested-by: Xudong Hao <xudong.hao@intel.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
next prev parent reply other threads:[~2026-10-09 20:28 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-09 9:07 [PATCH v8 0/6] intel_iommu: Enable PRQ support for passthrough device Zhenzhong Duan
2026-10-09 9:07 ` [PATCH v8 1/6] intel_iommu_accel: Guard VTDAccelPASIDCacheEntry definition Zhenzhong Duan
2026-10-09 9:07 ` [PATCH v8 2/6] backends/iommufd: Introduce iommufd_backend_alloc_faultq Zhenzhong Duan
2026-10-09 20:24 ` Nicolin Chen
2026-10-09 9:07 ` [PATCH v8 3/6] backends/iommufd: Extend iommufd_backend_alloc_hwpt() with fault_id Zhenzhong Duan
2026-10-09 20:26 ` Nicolin Chen [this message]
2026-10-09 9:07 ` [PATCH v8 4/6] intel_iommu_accel: Add PRQ injection for passthrough device Zhenzhong Duan
2026-10-09 9:07 ` [PATCH v8 5/6] intel_iommu_accel: Accept PRQ response " Zhenzhong Duan
2026-10-09 9:07 ` [PATCH v8 6/6] intel_iommu_accel: teardown FAULTQ resources in bottom half Zhenzhong Duan
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