* [PATCH v8 0/6] intel_iommu: Enable PRQ support for passthrough device
@ 2026-10-09 9:07 Zhenzhong Duan
2026-10-09 9:07 ` [PATCH v8 1/6] intel_iommu_accel: Guard VTDAccelPASIDCacheEntry definition Zhenzhong Duan
` (5 more replies)
0 siblings, 6 replies; 9+ messages in thread
From: Zhenzhong Duan @ 2026-10-09 9:07 UTC (permalink / raw)
To: qemu-devel
Cc: alex, clg, eric.auger, mst, jasowangio, jgg, nicolinc,
skolothumtho, joao.m.martins, clement.mathieu--drif, kevin.tian,
yi.l.liu, Zhenzhong Duan
Hi,
When svm=on,pasid-bits=N,fsts=on is configured for virtual vtd, we enable
guest's support for vSVM. In this case, the host VTD may generate
recoverable first stage page fault event, QEMU read the event and inject
it to guest.
After guest handles the event, it sends a page group response, QEMU gets
the response and pass it to host VTD.
This series adds QEMU support for receiving such host events through the
FAULTQ interface and propagating them to the guest, then catching guest's
responses and propagating them to host.
GIT branch: https://github.com/yiliu1765/qemu/tree/zhenzhong/iommufd_prq.v8
Tests:
Tested with DSA wq attached to an user APP which triggers IO page fault on
process page table durging DMA.
Build test with window cross-build.
Thanks
Zhenzhong
Changelog:
v8:
- s/sizeof(IOMMUFaultQueue)/sizeof(*fq) (Clement)
v7:
- add trailing "s" to vtd_propagate_recoverable_fault() name (Clement)
- s/fault/faults/ for array fault[FAULTQ_BUF_SIZE] (Clement)
- s/'ssize_t bytes'/'ssize_t ret' for trace_vtd_[read|write]_fs_faultq() input (Clement)
- switch to designated initialization for variable resp (Clement)
v6:
- further polish doc comments for vtd_pri_request_page (Liuyi)
- set FAULTQ_BUF_SIZE to 2048 to avoid prq lost (Liuyi)
- move PRE validation hunk in the caller side (Liuyi)
- add break in vtd_prq_list search loop in vtd_prq_response_notify (Clement)
- s/vtd_prq_report_fault/vtd_propagate_recoverable_fault (Liuyi, Clement)
- s/vtd_prq_read_fault/vtd_read_fs_faultq (Liuyi)
- s/vtd_prq_write_response/vtd_write_fs_faultq
- s/vtd_prq_response_notify/vtd_prq_handle_pasid_response
v5:
- add comment "Accept the PCI PASID as input" to docstring of function vtd_pri_request_page (Clement)
- change vtd_prq_report_fault() parameter type "int cnt" -> "unsigned cnt" (Clement)
- check return value of vtd_pri_request_page() and send response (Clement)
- free all vtd_prq_list entries when detaching (Clement)
v4:
- add the comment to the docstring of the function vtd_prq_report_fault itself (Clement)
- add "out_" prefix for fault_id & fault_fd output parameter (Clement)
v3:
- convert to PCI pasid before passing to vtd_pri_request_page (Clement)
- expose vtd_pri_request_page and drop accel_ops pointer (Clement)
- add a cleanup patch "intel_iommu_accel: Guard VTDAccelPASIDCacheEntry definition" (Philippe)
v2:
- define fault_fd int type (Liuyi)
- update comments on FAULTQ_BUF_SIZE (Liuyi)
- drop param vtd_hiod in vtd_destroy_old_fs_faultq() (Liuyi)
- s/vtd_propagate_page_group_response_accel/vtd_accel_propagate_page_group_response (Liuyi)
- call vtd_prq_response_notify() directly instead of through pri_notifier (Liuyi)
- replace "fault_id != 0" check with "fault_fd < 0" check (Liuyi)
Zhenzhong Duan (6):
intel_iommu_accel: Guard VTDAccelPASIDCacheEntry definition
backends/iommufd: Introduce iommufd_backend_alloc_faultq
backends/iommufd: Extend iommufd_backend_alloc_hwpt() with fault_id
intel_iommu_accel: Add PRQ injection for passthrough device
intel_iommu_accel: Accept PRQ response for passthrough device
intel_iommu_accel: teardown FAULTQ resources in bottom half
hw/i386/intel_iommu_accel.h | 16 +-
hw/i386/intel_iommu_internal.h | 3 +
include/hw/i386/intel_iommu.h | 6 +
include/system/iommufd.h | 7 +-
backends/iommufd.c | 28 +++-
hw/arm/smmuv3-accel.c | 6 +-
hw/i386/intel_iommu.c | 18 ++-
hw/i386/intel_iommu_accel.c | 282 ++++++++++++++++++++++++++++++++-
hw/vfio/iommufd.c | 2 +-
backends/trace-events | 3 +-
hw/i386/trace-events | 2 +
11 files changed, 351 insertions(+), 22 deletions(-)
--
2.52.0
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v8 1/6] intel_iommu_accel: Guard VTDAccelPASIDCacheEntry definition
2026-10-09 9:07 [PATCH v8 0/6] intel_iommu: Enable PRQ support for passthrough device Zhenzhong Duan
@ 2026-10-09 9:07 ` Zhenzhong Duan
2026-10-09 9:07 ` [PATCH v8 2/6] backends/iommufd: Introduce iommufd_backend_alloc_faultq Zhenzhong Duan
` (4 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Zhenzhong Duan @ 2026-10-09 9:07 UTC (permalink / raw)
To: qemu-devel
Cc: alex, clg, eric.auger, mst, jasowangio, jgg, nicolinc,
skolothumtho, joao.m.martins, clement.mathieu--drif, kevin.tian,
yi.l.liu, Zhenzhong Duan, Philippe Mathieu-Daudé
Move the VTDAccelPASIDCacheEntry typedef structure inside the
CONFIG_VTD_ACCEL ifdef block.
When CONFIG_VTD_ACCEL is disabled, this structure is entirely unused
throughout the code. Moving the layout under the existing preprocessor
guard prevents exposing dead type definitions and ensures the header
remains clean when building without VTD acceleration support.
Suggested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clement Mathieu--Drif <clement.mathieu--drif@bull.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
---
hw/i386/intel_iommu_accel.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h
index 4a9003c92d..46c1a29409 100644
--- a/hw/i386/intel_iommu_accel.h
+++ b/hw/i386/intel_iommu_accel.h
@@ -12,6 +12,7 @@
#define HW_I386_INTEL_IOMMU_ACCEL_H
#include CONFIG_DEVICES
+#ifdef CONFIG_VTD_ACCEL
typedef struct VTDAccelPASIDCacheEntry {
VTDHostIOMMUDevice *vtd_hiod;
VTDPASIDEntry pasid_entry;
@@ -20,7 +21,6 @@ typedef struct VTDAccelPASIDCacheEntry {
QLIST_ENTRY(VTDAccelPASIDCacheEntry) next;
} VTDAccelPASIDCacheEntry;
-#ifdef CONFIG_VTD_ACCEL
bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod,
Error **errp);
VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpace *as);
--
2.52.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v8 2/6] backends/iommufd: Introduce iommufd_backend_alloc_faultq
2026-10-09 9:07 [PATCH v8 0/6] intel_iommu: Enable PRQ support for passthrough device Zhenzhong Duan
2026-10-09 9:07 ` [PATCH v8 1/6] intel_iommu_accel: Guard VTDAccelPASIDCacheEntry definition Zhenzhong Duan
@ 2026-10-09 9:07 ` Zhenzhong Duan
2026-10-09 20:24 ` Nicolin Chen
2026-10-09 9:07 ` [PATCH v8 3/6] backends/iommufd: Extend iommufd_backend_alloc_hwpt() with fault_id Zhenzhong Duan
` (3 subsequent siblings)
5 siblings, 1 reply; 9+ messages in thread
From: Zhenzhong Duan @ 2026-10-09 9:07 UTC (permalink / raw)
To: qemu-devel
Cc: alex, clg, eric.auger, mst, jasowangio, jgg, nicolinc,
skolothumtho, joao.m.martins, clement.mathieu--drif, kevin.tian,
yi.l.liu, Zhenzhong Duan, Xudong Hao
Add a new helper for IOMMU_FAULT_QUEUE_ALLOC ioctl to allocate a fault
handling object which will be used in hwpt allocation.
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clement Mathieu--Drif <clement.mathieu--drif@bull.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Tested-by: Xudong Hao <xudong.hao@intel.com>
---
include/system/iommufd.h | 3 +++
backends/iommufd.c | 21 +++++++++++++++++++++
backends/trace-events | 1 +
3 files changed, 25 insertions(+)
diff --git a/include/system/iommufd.h b/include/system/iommufd.h
index 17bf1a3727..36b34b4899 100644
--- a/include/system/iommufd.h
+++ b/include/system/iommufd.h
@@ -106,6 +106,9 @@ bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be, uint32_t viommu_id,
uint32_t *out_veventq_id,
uint32_t *out_veventq_fd, Error **errp);
+bool iommufd_backend_alloc_faultq(IOMMUFDBackend *be, uint32_t *out_fault_id,
+ uint32_t *out_fault_fd, Error **errp);
+
bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be, uint32_t viommu_id,
uint32_t queue_type, uint32_t index,
uint64_t addr, uint64_t length,
diff --git a/backends/iommufd.c b/backends/iommufd.c
index 15f2a51350..2775eef741 100644
--- a/backends/iommufd.c
+++ b/backends/iommufd.c
@@ -554,6 +554,27 @@ bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be, uint32_t viommu_id,
return true;
}
+bool iommufd_backend_alloc_faultq(IOMMUFDBackend *be, uint32_t *out_fault_id,
+ uint32_t *out_fault_fd, Error **errp)
+{
+ int ret, fd = be->fd;
+ struct iommu_fault_alloc cmd = {
+ .size = sizeof(cmd),
+ };
+
+ ret = ioctl(fd, IOMMU_FAULT_QUEUE_ALLOC, &cmd);
+ trace_iommufd_backend_alloc_faultq(fd, cmd.out_fault_id, cmd.out_fault_fd,
+ ret);
+ if (ret) {
+ error_setg_errno(errp, errno, "Failed to allocate fault queue");
+ return false;
+ }
+
+ *out_fault_id = cmd.out_fault_id;
+ *out_fault_fd = cmd.out_fault_fd;
+ return true;
+}
+
bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be, uint32_t viommu_id,
uint32_t queue_type, uint32_t index,
uint64_t addr, uint64_t length,
diff --git a/backends/trace-events b/backends/trace-events
index 9b7b9b7d68..b1c1d89dd8 100644
--- a/backends/trace-events
+++ b/backends/trace-events
@@ -17,6 +17,7 @@ iommufd_backend_unmap_dma_non_exist(int iommufd, uint32_t ioas, uint64_t iova, u
iommufd_backend_unmap_dma(int iommufd, uint32_t ioas, uint64_t iova, uint64_t size, int ret) " iommufd=%d ioas=%d iova=0x%"PRIx64" size=0x%"PRIx64" (%d)"
iommufd_backend_alloc_ioas(int iommufd, uint32_t ioas) " iommufd=%d ioas=%d"
iommufd_backend_alloc_hwpt(int iommufd, uint32_t dev_id, uint32_t pt_id, uint32_t flags, uint32_t hwpt_type, uint32_t len, uint64_t data_ptr, uint32_t out_hwpt_id, int ret) " iommufd=%d dev_id=%u pt_id=%u flags=0x%x hwpt_type=%u len=%u data_ptr=0x%"PRIx64" out_hwpt=%u (%d)"
+iommufd_backend_alloc_faultq(int iommufd, uint32_t fault_id, uint32_t fault_fd, int ret) " iommufd=%d fault_id=%u fault_fd=%u (%d)"
iommufd_backend_free_id(int iommufd, uint32_t id, int ret) " iommufd=%d id=%d (%d)"
iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, bool start, int ret) " iommufd=%d hwpt=%u enable=%d (%d)"
iommufd_backend_get_dirty_bitmap(int iommufd, uint32_t hwpt_id, uint64_t iova, uint64_t size, uint64_t flags, uint64_t page_size, int ret) " iommufd=%d hwpt=%u iova=0x%"PRIx64" size=0x%"PRIx64" flags=0x%"PRIx64" page_size=0x%"PRIx64" (%d)"
--
2.52.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v8 3/6] backends/iommufd: Extend iommufd_backend_alloc_hwpt() with fault_id
2026-10-09 9:07 [PATCH v8 0/6] intel_iommu: Enable PRQ support for passthrough device Zhenzhong Duan
2026-10-09 9:07 ` [PATCH v8 1/6] intel_iommu_accel: Guard VTDAccelPASIDCacheEntry definition Zhenzhong Duan
2026-10-09 9:07 ` [PATCH v8 2/6] backends/iommufd: Introduce iommufd_backend_alloc_faultq Zhenzhong Duan
@ 2026-10-09 9:07 ` Zhenzhong Duan
2026-10-09 20:26 ` Nicolin Chen
2026-10-09 9:07 ` [PATCH v8 4/6] intel_iommu_accel: Add PRQ injection for passthrough device Zhenzhong Duan
` (2 subsequent siblings)
5 siblings, 1 reply; 9+ messages in thread
From: Zhenzhong Duan @ 2026-10-09 9:07 UTC (permalink / raw)
To: qemu-devel
Cc: alex, clg, eric.auger, mst, jasowangio, jgg, nicolinc,
skolothumtho, joao.m.martins, clement.mathieu--drif, kevin.tian,
yi.l.liu, Zhenzhong Duan, Xudong Hao, qemu-arm
We should set flags IOMMU_HWPT_FAULT_ID_VALID when pass in a fault
object id in the caller.
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clement Mathieu--Drif <clement.mathieu--drif@bull.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Tested-by: Xudong Hao <xudong.hao@intel.com>
---
include/system/iommufd.h | 4 ++--
backends/iommufd.c | 7 ++++---
hw/arm/smmuv3-accel.c | 6 +++---
hw/i386/intel_iommu_accel.c | 2 +-
hw/vfio/iommufd.c | 2 +-
backends/trace-events | 2 +-
6 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/include/system/iommufd.h b/include/system/iommufd.h
index 36b34b4899..79b8dabfb6 100644
--- a/include/system/iommufd.h
+++ b/include/system/iommufd.h
@@ -90,8 +90,8 @@ bool iommufd_backend_get_device_info(IOMMUFDBackend *be, uint32_t devid,
bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint32_t dev_id,
uint32_t pt_id, uint32_t flags,
uint32_t data_type, uint32_t data_len,
- void *data_ptr, uint32_t *out_hwpt,
- Error **errp);
+ void *data_ptr, uint32_t fault_id,
+ uint32_t *out_hwpt, Error **errp);
bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id,
uint32_t viommu_type, uint32_t hwpt_id,
void *data_ptr, uint32_t data_len,
diff --git a/backends/iommufd.c b/backends/iommufd.c
index 2775eef741..f46b3bfa7e 100644
--- a/backends/iommufd.c
+++ b/backends/iommufd.c
@@ -315,8 +315,8 @@ int iommufd_backend_unmap_dma(IOMMUFDBackend *be, uint32_t ioas_id,
bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint32_t dev_id,
uint32_t pt_id, uint32_t flags,
uint32_t data_type, uint32_t data_len,
- void *data_ptr, uint32_t *out_hwpt,
- Error **errp)
+ void *data_ptr, uint32_t fault_id,
+ uint32_t *out_hwpt, Error **errp)
{
int ret, fd = be->fd;
struct iommu_hwpt_alloc alloc_hwpt = {
@@ -327,11 +327,12 @@ bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint32_t dev_id,
.data_type = data_type,
.data_len = data_len,
.data_uptr = (uintptr_t)data_ptr,
+ .fault_id = fault_id,
};
ret = ioctl(fd, IOMMU_HWPT_ALLOC, &alloc_hwpt);
trace_iommufd_backend_alloc_hwpt(fd, dev_id, pt_id, flags, data_type,
- data_len, (uintptr_t)data_ptr,
+ data_len, (uintptr_t)data_ptr, fault_id,
alloc_hwpt.out_hwpt_id, ret);
if (ret) {
error_setg_errno(errp, errno, "Failed to allocate hwpt");
diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
index 91aca1aa14..66e6a5011a 100644
--- a/hw/arm/smmuv3-accel.c
+++ b/hw/arm/smmuv3-accel.c
@@ -268,7 +268,7 @@ smmuv3_accel_dev_alloc_translate(SMMUv3AccelDevice *accel_dev, STE *ste,
accel->viommu->viommu_id, flags,
IOMMU_HWPT_DATA_ARM_SMMUV3,
sizeof(nested_data), &nested_data,
- &hwpt_id, errp)) {
+ 0, &hwpt_id, errp)) {
return NULL;
}
@@ -632,14 +632,14 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *hiodi,
if (!iommufd_backend_alloc_hwpt(hiodi->iommufd, hiodi->devid, viommu_id,
0, IOMMU_HWPT_DATA_ARM_SMMUV3,
sizeof(abort_data), &abort_data,
- &accel->abort_hwpt_id, errp)) {
+ 0, &accel->abort_hwpt_id, errp)) {
goto free_viommu;
}
if (!iommufd_backend_alloc_hwpt(hiodi->iommufd, hiodi->devid, viommu_id,
0, IOMMU_HWPT_DATA_ARM_SMMUV3,
sizeof(bypass_data), &bypass_data,
- &accel->bypass_hwpt_id, errp)) {
+ 0, &accel->bypass_hwpt_id, errp)) {
goto free_abort_hwpt;
}
diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c
index c3677775e9..c8f2835204 100644
--- a/hw/i386/intel_iommu_accel.c
+++ b/hw/i386/intel_iommu_accel.c
@@ -100,7 +100,7 @@ static bool vtd_create_fs_hwpt(VTDHostIOMMUDevice *vtd_hiod,
return iommufd_backend_alloc_hwpt(hiodi->iommufd, hiodi->devid,
hiodi->hwpt_id, flags,
IOMMU_HWPT_DATA_VTD_S1, sizeof(vtd), &vtd,
- fs_hwpt_id, errp);
+ 0, fs_hwpt_id, errp);
}
static void vtd_destroy_old_fs_hwpt(VTDAccelPASIDCacheEntry *vtd_pce)
diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c
index 242644aa00..74a5d77dcc 100644
--- a/hw/vfio/iommufd.c
+++ b/hw/vfio/iommufd.c
@@ -476,7 +476,7 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vbasedev,
if (!iommufd_backend_alloc_hwpt(iommufd, vbasedev->devid,
container->ioas_id, flags,
IOMMU_HWPT_DATA_NONE, 0, NULL,
- &hwpt_id, errp)) {
+ 0, &hwpt_id, errp)) {
return false;
}
diff --git a/backends/trace-events b/backends/trace-events
index b1c1d89dd8..2f242feb78 100644
--- a/backends/trace-events
+++ b/backends/trace-events
@@ -16,7 +16,7 @@ iommufd_backend_map_file_dma(int iommufd, uint32_t ioas, uint64_t iova, uint64_t
iommufd_backend_unmap_dma_non_exist(int iommufd, uint32_t ioas, uint64_t iova, uint64_t size, int ret) " Unmap nonexistent mapping: iommufd=%d ioas=%d iova=0x%"PRIx64" size=0x%"PRIx64" (%d)"
iommufd_backend_unmap_dma(int iommufd, uint32_t ioas, uint64_t iova, uint64_t size, int ret) " iommufd=%d ioas=%d iova=0x%"PRIx64" size=0x%"PRIx64" (%d)"
iommufd_backend_alloc_ioas(int iommufd, uint32_t ioas) " iommufd=%d ioas=%d"
-iommufd_backend_alloc_hwpt(int iommufd, uint32_t dev_id, uint32_t pt_id, uint32_t flags, uint32_t hwpt_type, uint32_t len, uint64_t data_ptr, uint32_t out_hwpt_id, int ret) " iommufd=%d dev_id=%u pt_id=%u flags=0x%x hwpt_type=%u len=%u data_ptr=0x%"PRIx64" out_hwpt=%u (%d)"
+iommufd_backend_alloc_hwpt(int iommufd, uint32_t dev_id, uint32_t pt_id, uint32_t flags, uint32_t hwpt_type, uint32_t len, uint64_t data_ptr, uint32_t fault_id, uint32_t out_hwpt_id, int ret) " iommufd=%d dev_id=%u pt_id=%u flags=0x%x hwpt_type=%u len=%u data_ptr=0x%"PRIx64" fault_id=%u out_hwpt=%u (%d)"
iommufd_backend_alloc_faultq(int iommufd, uint32_t fault_id, uint32_t fault_fd, int ret) " iommufd=%d fault_id=%u fault_fd=%u (%d)"
iommufd_backend_free_id(int iommufd, uint32_t id, int ret) " iommufd=%d id=%d (%d)"
iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, bool start, int ret) " iommufd=%d hwpt=%u enable=%d (%d)"
--
2.52.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v8 4/6] intel_iommu_accel: Add PRQ injection for passthrough device
2026-10-09 9:07 [PATCH v8 0/6] intel_iommu: Enable PRQ support for passthrough device Zhenzhong Duan
` (2 preceding siblings ...)
2026-10-09 9:07 ` [PATCH v8 3/6] backends/iommufd: Extend iommufd_backend_alloc_hwpt() with fault_id Zhenzhong Duan
@ 2026-10-09 9:07 ` Zhenzhong Duan
2026-10-09 9:07 ` [PATCH v8 5/6] intel_iommu_accel: Accept PRQ response " Zhenzhong Duan
2026-10-09 9:07 ` [PATCH v8 6/6] intel_iommu_accel: teardown FAULTQ resources in bottom half Zhenzhong Duan
5 siblings, 0 replies; 9+ messages in thread
From: Zhenzhong Duan @ 2026-10-09 9:07 UTC (permalink / raw)
To: qemu-devel
Cc: alex, clg, eric.auger, mst, jasowangio, jgg, nicolinc,
skolothumtho, joao.m.martins, clement.mathieu--drif, kevin.tian,
yi.l.liu, Zhenzhong Duan, Xudong Hao
When the guest enables the PRQ in vIOMMU, allocate a FAULTQ object so that
host-side recoverable fault events can be received and propagated back to
the guest.
Install an event handler on the FAULTQ fd to read and propagate host
generated recoverable fault events to the guest.
The handler runs in QEMU's main loop, using a non-blocking fd registered
via qemu_set_fd_handler().
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clement Mathieu--Drif <clement.mathieu--drif@bull.com>
Tested-by: Xudong Hao <xudong.hao@intel.com>
---
hw/i386/intel_iommu_accel.h | 2 +
hw/i386/intel_iommu_internal.h | 3 +
hw/i386/intel_iommu.c | 14 ++-
hw/i386/intel_iommu_accel.c | 163 +++++++++++++++++++++++++++++++--
hw/i386/trace-events | 1 +
5 files changed, 172 insertions(+), 11 deletions(-)
diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h
index 46c1a29409..e0319749a5 100644
--- a/hw/i386/intel_iommu_accel.h
+++ b/hw/i386/intel_iommu_accel.h
@@ -18,6 +18,8 @@ typedef struct VTDAccelPASIDCacheEntry {
VTDPASIDEntry pasid_entry;
uint32_t pasid;
uint32_t fs_hwpt_id;
+ uint32_t fault_id;
+ int fault_fd;
QLIST_ENTRY(VTDAccelPASIDCacheEntry) next;
} VTDAccelPASIDCacheEntry;
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index df7a0efa6e..4792035668 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -787,4 +787,7 @@ int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,
VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid);
int vtd_dev_get_pe_from_pasid(IntelIOMMUState *s, PCIBus *bus, uint8_t devfn,
uint32_t pasid, VTDPASIDEntry *pe);
+int vtd_pri_request_page(PCIBus *bus, void *opaque, int devfn, uint32_t pasid,
+ bool priv_req, bool exec_req, hwaddr addr, bool lpig,
+ uint16_t prgi, bool is_read, bool is_write);
#endif
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 350d2b7753..81c53c6f5a 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -5383,11 +5383,15 @@ static int vtd_pri_perform_implicit_invalidation(VTDAddressSpace *vtd_as,
return ret;
}
-/* Page Request Descriptor : 7.4.1.1 */
-static int vtd_pri_request_page(PCIBus *bus, void *opaque, int devfn,
- uint32_t pasid, bool priv_req, bool exec_req,
- hwaddr addr, bool lpig, uint16_t prgi,
- bool is_read, bool is_write)
+/*
+ * Page Request Descriptor : 7.4.1.1
+ *
+ * Because it is facing the emulated device models, so this should be PCI
+ * PASID instead of the pasids used within vIOMMU.
+ */
+int vtd_pri_request_page(PCIBus *bus, void *opaque, int devfn, uint32_t pasid,
+ bool priv_req, bool exec_req, hwaddr addr, bool lpig,
+ uint16_t prgi, bool is_read, bool is_write)
{
IntelIOMMUState *s = opaque;
VTDAddressSpace *vtd_as;
diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c
index c8f2835204..7baefe30cc 100644
--- a/hw/i386/intel_iommu_accel.c
+++ b/hw/i386/intel_iommu_accel.c
@@ -9,6 +9,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/error-report.h"
#include "system/iommufd.h"
#include "intel_iommu_internal.h"
#include "intel_iommu_accel.h"
@@ -83,14 +84,141 @@ VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpace *as)
return NULL;
}
-static bool vtd_create_fs_hwpt(VTDHostIOMMUDevice *vtd_hiod,
- VTDPASIDEntry *pe, uint32_t *fs_hwpt_id,
- Error **errp)
+static void vtd_propagate_recoverable_faults(VTDAccelPASIDCacheEntry *vtd_pce,
+ struct iommu_hwpt_pgfault *fault,
+ unsigned cnt)
+{
+ VTDHostIOMMUDevice *vtd_hiod = vtd_pce->vtd_hiod;
+ uint32_t pasid =
+ vtd_pce->pasid == IOMMU_NO_PASID ? PCI_NO_PASID : vtd_pce->pasid;
+
+ for (; cnt--; fault++) {
+ bool last_page = fault->flags & IOMMU_PGFAULT_FLAGS_LAST_PAGE;
+
+ vtd_pri_request_page(vtd_hiod->bus, vtd_hiod->iommu_state,
+ vtd_hiod->devfn, pasid,
+ fault->perm & IOMMU_PGFAULT_PERM_PRIV,
+ fault->perm & IOMMU_PGFAULT_PERM_EXEC,
+ fault->addr, last_page, fault->grpid,
+ fault->perm & IOMMU_PGFAULT_PERM_READ,
+ fault->perm & IOMMU_PGFAULT_PERM_WRITE);
+ }
+}
+
+/* Batch size per read(); remaining faults trigger another callback */
+#define FAULTQ_BUF_SIZE 2048
+
+static void vtd_read_fs_faultq(void *opaque)
+{
+ VTDAccelPASIDCacheEntry *vtd_pce = opaque;
+ struct iommu_hwpt_pgfault faults[FAULTQ_BUF_SIZE];
+ uint32_t id = vtd_pce->fault_id;
+ int fd = vtd_pce->fault_fd;
+ ssize_t bytes, last_bytes;
+
+ bytes = read(fd, faults, sizeof(faults));
+ trace_vtd_read_fs_faultq(id, fd, bytes);
+ if (bytes < 0) {
+ if (errno != EAGAIN && errno != EINTR) {
+ error_report_once("FAULTQ(id %u): read failed (%m)", id);
+ }
+ return;
+ } else if (!bytes) {
+ error_report_once("FAULTQ(id %u): fault group empty unexpectedly", id);
+ return;
+ }
+
+ last_bytes = bytes % sizeof(faults[0]);
+ if (last_bytes) {
+ error_report_once("FAULTQ(id %u): discard partial fault data: %zd/%zu",
+ id, last_bytes, sizeof(faults[0]));
+ }
+
+ vtd_propagate_recoverable_faults(vtd_pce, faults,
+ bytes / sizeof(faults[0]));
+}
+
+static void vtd_destroy_fs_faultq(VTDHostIOMMUDevice *vtd_hiod,
+ uint32_t fault_id, int fault_fd)
+{
+ HostIOMMUDeviceIOMMUFD *hiodi = HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->hiod);
+
+ if (fault_fd < 0) {
+ return;
+ }
+
+ close(fault_fd);
+ iommufd_backend_free_id(hiodi->iommufd, fault_id);
+}
+
+static bool vtd_create_fs_faultq(VTDHostIOMMUDevice *vtd_hiod,
+ uint32_t *fault_id_p, int *fault_fd_p,
+ Error **errp)
+{
+ HostIOMMUDeviceIOMMUFD *hiodi = HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->hiod);
+ uint32_t fault_id, fault_fd;
+ int flags;
+
+ if (!iommufd_backend_alloc_faultq(hiodi->iommufd, &fault_id, &fault_fd,
+ errp)) {
+ return false;
+ }
+
+ flags = fcntl(fault_fd, F_GETFL);
+ if (flags < 0) {
+ error_setg_errno(errp, errno, "Failed to get flags for FAULTQ fd");
+ goto free_faultq;
+ }
+
+ if (fcntl(fault_fd, F_SETFL, flags | O_NONBLOCK) < 0) {
+ error_setg_errno(errp, errno, "Failed to set O_NONBLOCK on FAULTQ fd");
+ goto free_faultq;
+ }
+
+ *fault_id_p = fault_id;
+ *fault_fd_p = fault_fd;
+ return true;
+
+free_faultq:
+ vtd_destroy_fs_faultq(vtd_hiod, fault_id, fault_fd);
+ return false;
+}
+
+static void vtd_destroy_old_fs_faultq(VTDAccelPASIDCacheEntry *vtd_pce)
+{
+ if (vtd_pce->fault_fd < 0) {
+ return;
+ }
+
+ qemu_set_fd_handler(vtd_pce->fault_fd, NULL, NULL, NULL);
+ vtd_destroy_fs_faultq(vtd_pce->vtd_hiod, vtd_pce->fault_id,
+ vtd_pce->fault_fd);
+ vtd_pce->fault_id = 0;
+ vtd_pce->fault_fd = -1;
+}
+
+static void vtd_setup_fs_faultq(VTDAccelPASIDCacheEntry *vtd_pce,
+ uint32_t fault_id, int fault_fd)
+{
+ if (fault_fd < 0) {
+ return;
+ }
+
+ vtd_pce->fault_id = fault_id;
+ vtd_pce->fault_fd = fault_fd;
+ qemu_set_fd_handler(fault_fd, vtd_read_fs_faultq, NULL, vtd_pce);
+}
+
+static bool vtd_create_fs_hwpt(VTDHostIOMMUDevice *vtd_hiod, VTDPASIDEntry *pe,
+ bool has_fault_id, uint32_t fault_id,
+ uint32_t *fs_hwpt_id, Error **errp)
{
HostIOMMUDeviceIOMMUFD *hiodi = HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->hiod);
struct iommu_hwpt_vtd_s1 vtd = {};
uint32_t flags = vtd_hiod->iommu_state->pasid ? IOMMU_HWPT_ALLOC_PASID : 0;
+ flags |= has_fault_id ? IOMMU_HWPT_FAULT_ID_VALID : 0;
+
vtd.flags = (VTD_SM_PASID_ENTRY_SRE(pe) ? IOMMU_VTD_S1_SRE : 0) |
(VTD_SM_PASID_ENTRY_WPE(pe) ? IOMMU_VTD_S1_WPE : 0) |
(VTD_SM_PASID_ENTRY_EAFE(pe) ? IOMMU_VTD_S1_EAFE : 0);
@@ -100,7 +228,7 @@ static bool vtd_create_fs_hwpt(VTDHostIOMMUDevice *vtd_hiod,
return iommufd_backend_alloc_hwpt(hiodi->iommufd, hiodi->devid,
hiodi->hwpt_id, flags,
IOMMU_HWPT_DATA_VTD_S1, sizeof(vtd), &vtd,
- 0, fs_hwpt_id, errp);
+ fault_id, fs_hwpt_id, errp);
}
static void vtd_destroy_old_fs_hwpt(VTDAccelPASIDCacheEntry *vtd_pce)
@@ -121,7 +249,8 @@ static bool vtd_device_attach_iommufd(VTDAccelPASIDCacheEntry *vtd_pce,
VTDHostIOMMUDevice *vtd_hiod = vtd_pce->vtd_hiod;
HostIOMMUDeviceIOMMUFD *hiodi = HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->hiod);
VTDPASIDEntry *pe = &vtd_pce->pasid_entry;
- uint32_t hwpt_id = hiodi->hwpt_id, pasid = vtd_pce->pasid;
+ uint32_t hwpt_id = hiodi->hwpt_id, pasid = vtd_pce->pasid, fault_id = 0;
+ int fault_fd = -1;
bool ret;
/*
@@ -136,7 +265,24 @@ static bool vtd_device_attach_iommufd(VTDAccelPASIDCacheEntry *vtd_pce,
}
if (vtd_pe_pgtt_is_fst(pe)) {
- if (!vtd_create_fs_hwpt(vtd_hiod, pe, &hwpt_id, errp)) {
+ IntelIOMMUState *s = vtd_hiod->iommu_state;
+ VTDContextEntry ce;
+ uint8_t bus_n = pci_bus_num(vtd_hiod->bus);
+ bool is_pre = false;
+
+ if (s->svm &&
+ !vtd_dev_to_context_entry(s, bus_n, vtd_hiod->devfn, &ce)) {
+ is_pre = !!VTD_CE_GET_PRE(&ce);
+
+ if (is_pre &&
+ !vtd_create_fs_faultq(vtd_hiod, &fault_id, &fault_fd, errp)) {
+ return false;
+ }
+ }
+
+ if (!vtd_create_fs_hwpt(vtd_hiod, pe, is_pre, fault_id, &hwpt_id,
+ errp)) {
+ vtd_destroy_fs_faultq(vtd_hiod, fault_id, fault_fd);
return false;
}
}
@@ -146,11 +292,14 @@ static bool vtd_device_attach_iommufd(VTDAccelPASIDCacheEntry *vtd_pce,
if (ret) {
/* Destroy old fs_hwpt if it's a replacement */
vtd_destroy_old_fs_hwpt(vtd_pce);
+ vtd_destroy_old_fs_faultq(vtd_pce);
if (vtd_pe_pgtt_is_fst(pe)) {
vtd_pce->fs_hwpt_id = hwpt_id;
+ vtd_setup_fs_faultq(vtd_pce, fault_id, fault_fd);
}
} else if (vtd_pe_pgtt_is_fst(pe)) {
iommufd_backend_free_id(hiodi->iommufd, hwpt_id);
+ vtd_destroy_fs_faultq(vtd_hiod, fault_id, fault_fd);
}
return ret;
@@ -183,6 +332,7 @@ static bool vtd_device_detach_iommufd(VTDAccelPASIDCacheEntry *vtd_pce,
if (ret) {
vtd_destroy_old_fs_hwpt(vtd_pce);
+ vtd_destroy_old_fs_faultq(vtd_pce);
}
return ret;
@@ -282,6 +432,7 @@ static void vtd_accel_fill_pc(VTDHostIOMMUDevice *vtd_hiod, uint32_t pasid,
vtd_pce->vtd_hiod = vtd_hiod;
vtd_pce->pasid = pasid;
vtd_pce->pasid_entry = *pe;
+ vtd_pce->fault_fd = -1;
QLIST_INSERT_HEAD(&vtd_hiod->pasid_cache_list, vtd_pce, next);
if (!vtd_device_attach_iommufd(vtd_pce, &local_err)) {
diff --git a/hw/i386/trace-events b/hw/i386/trace-events
index a1a50d0910..ad84d106a4 100644
--- a/hw/i386/trace-events
+++ b/hw/i386/trace-events
@@ -77,6 +77,7 @@ vtd_reset_exit(void) ""
vtd_device_attach_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwpt_id, int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d"
vtd_device_detach_hwpt(uint32_t dev_id, uint32_t pasid, int ret) "dev_id %d pasid %d ret: %d"
vtd_device_reattach_def_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwpt_id, int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d"
+vtd_read_fs_faultq(uint32_t fault_id, uint32_t fault_fd, ssize_t ret) "fault_id %d fault_fd %d ret: %zd"
# amd_iommu.c
amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at addr 0x%"PRIx64" + offset 0x%"PRIx32
--
2.52.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v8 5/6] intel_iommu_accel: Accept PRQ response for passthrough device
2026-10-09 9:07 [PATCH v8 0/6] intel_iommu: Enable PRQ support for passthrough device Zhenzhong Duan
` (3 preceding siblings ...)
2026-10-09 9:07 ` [PATCH v8 4/6] intel_iommu_accel: Add PRQ injection for passthrough device Zhenzhong Duan
@ 2026-10-09 9:07 ` Zhenzhong Duan
2026-10-09 9:07 ` [PATCH v8 6/6] intel_iommu_accel: teardown FAULTQ resources in bottom half Zhenzhong Duan
5 siblings, 0 replies; 9+ messages in thread
From: Zhenzhong Duan @ 2026-10-09 9:07 UTC (permalink / raw)
To: qemu-devel
Cc: alex, clg, eric.auger, mst, jasowangio, jgg, nicolinc,
skolothumtho, joao.m.martins, clement.mathieu--drif, kevin.tian,
yi.l.liu, Zhenzhong Duan, Xudong Hao
Propagate guest's PRQ response to host by writing to fault_fd.
Create a new VTDPRQEntry to cache cookie for each fault group,
this cookie is used to mark the fault group on host side.
If there is either PRQ overflow or full error condition, propagate
a success response to host for LPIG request with the PRQ requests
dropped. For other error conditions, propagate response of invalid
request.
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clement Mathieu--Drif <clement.mathieu--drif@bull.com>
Tested-by: Xudong Hao <xudong.hao@intel.com>
---
hw/i386/intel_iommu_accel.h | 12 +++++
include/hw/i386/intel_iommu.h | 6 +++
hw/i386/intel_iommu.c | 4 ++
hw/i386/intel_iommu_accel.c | 99 ++++++++++++++++++++++++++++++++---
hw/i386/trace-events | 1 +
5 files changed, 115 insertions(+), 7 deletions(-)
diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h
index e0319749a5..0cc22b2cbb 100644
--- a/hw/i386/intel_iommu_accel.h
+++ b/hw/i386/intel_iommu_accel.h
@@ -20,6 +20,7 @@ typedef struct VTDAccelPASIDCacheEntry {
uint32_t fs_hwpt_id;
uint32_t fault_id;
int fault_fd;
+ QLIST_HEAD(, VTDPRQEntry) vtd_prq_list;
QLIST_ENTRY(VTDAccelPASIDCacheEntry) next;
} VTDAccelPASIDCacheEntry;
@@ -31,6 +32,9 @@ void vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s, uint16_t domain_id,
uint64_t npages, bool ih);
void vtd_accel_pasid_cache_sync(IntelIOMMUState *s, VTDPASIDCacheInfo *pc_info);
void vtd_accel_pasid_cache_reset(IntelIOMMUState *s);
+bool vtd_accel_propagate_page_group_response(IntelIOMMUState *s,
+ uint16_t rid, uint32_t pasid,
+ IOMMUPRIResponse *response);
void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops);
#else
static inline bool vtd_check_hiod_accel(IntelIOMMUState *s,
@@ -69,6 +73,14 @@ static inline void vtd_accel_pasid_cache_reset(IntelIOMMUState *s)
{
}
+static inline
+bool vtd_accel_propagate_page_group_response(IntelIOMMUState *s,
+ uint16_t rid, uint32_t pasid,
+ IOMMUPRIResponse *response)
+{
+ return false;
+}
+
static inline void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops)
{
}
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index 1842ba5840..5d44eac0ed 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -100,6 +100,12 @@ typedef struct VTDPASIDCacheEntry {
bool valid;
} VTDPASIDCacheEntry;
+typedef struct VTDPRQEntry {
+ uint32_t grpid;
+ uint32_t cookie;
+ QLIST_ENTRY(VTDPRQEntry) next;
+} VTDPRQEntry;
+
struct VTDAddressSpace {
PCIBus *bus;
uint8_t devfn;
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 81c53c6f5a..4c2347e7d2 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3380,6 +3380,10 @@ static bool vtd_process_page_group_response_desc(IntelIOMMUState *s,
response.response_code = IOMMU_PRI_RESP_FAILURE;
}
+ if (vtd_accel_propagate_page_group_response(s, rid, pasid, &response)) {
+ return true;
+ }
+
if (vtd_dev_as->pri_notifier) {
vtd_dev_as->pri_notifier->notify(vtd_dev_as->pri_notifier, &response);
}
diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c
index 7baefe30cc..cd227315da 100644
--- a/hw/i386/intel_iommu_accel.c
+++ b/hw/i386/intel_iommu_accel.c
@@ -84,6 +84,62 @@ VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpace *as)
return NULL;
}
+static void vtd_write_fs_faultq(VTDAccelPASIDCacheEntry *vtd_pce,
+ uint32_t cookie, uint32_t code)
+{
+ struct iommu_hwpt_page_response resp = {.cookie = cookie, .code = code};
+ uint32_t id = vtd_pce->fault_id;
+ int fd = vtd_pce->fault_fd;
+ ssize_t bytes;
+
+ bytes = write(fd, &resp, sizeof(resp));
+ trace_vtd_write_fs_faultq(id, fd, cookie, code, bytes);
+ if (bytes < 0) {
+ error_report_once("FAULTQ(id %u): write failed "
+ "[cookie 0x%x code 0x%x] (%m)", id, cookie, code);
+ }
+}
+
+static void vtd_prq_handle_pasid_response(VTDAccelPASIDCacheEntry *vtd_pce,
+ IOMMUPRIResponse *response)
+{
+ VTDPRQEntry *prqe, *tmp;
+
+ QLIST_FOREACH_SAFE(prqe, &vtd_pce->vtd_prq_list, next, tmp) {
+ if (prqe->grpid != response->prgi) {
+ continue;
+ }
+
+ vtd_write_fs_faultq(vtd_pce, prqe->cookie, response->response_code);
+
+ QLIST_REMOVE(prqe, next);
+ g_free(prqe);
+ break;
+ }
+}
+
+bool vtd_accel_propagate_page_group_response(IntelIOMMUState *s,
+ uint16_t rid, uint32_t pasid,
+ IOMMUPRIResponse *response)
+{
+ VTDAddressSpace *vtd_as = vtd_get_as_by_sid(s, rid);
+ VTDAccelPASIDCacheEntry *vtd_pce;
+ VTDHostIOMMUDevice *vtd_hiod = vtd_find_hiod_iommufd(vtd_as);
+
+ if (!vtd_hiod) {
+ return false;
+ }
+
+ QLIST_FOREACH(vtd_pce, &vtd_hiod->pasid_cache_list, next) {
+ if (vtd_pce->pasid == pasid) {
+ vtd_prq_handle_pasid_response(vtd_pce, response);
+ return true;
+ }
+ }
+
+ return false;
+}
+
static void vtd_propagate_recoverable_faults(VTDAccelPASIDCacheEntry *vtd_pce,
struct iommu_hwpt_pgfault *fault,
unsigned cnt)
@@ -94,14 +150,42 @@ static void vtd_propagate_recoverable_faults(VTDAccelPASIDCacheEntry *vtd_pce,
for (; cnt--; fault++) {
bool last_page = fault->flags & IOMMU_PGFAULT_FLAGS_LAST_PAGE;
+ int ret;
+
+ ret = vtd_pri_request_page(vtd_hiod->bus, vtd_hiod->iommu_state,
+ vtd_hiod->devfn, pasid,
+ fault->perm & IOMMU_PGFAULT_PERM_PRIV,
+ fault->perm & IOMMU_PGFAULT_PERM_EXEC,
+ fault->addr, last_page, fault->grpid,
+ fault->perm & IOMMU_PGFAULT_PERM_READ,
+ fault->perm & IOMMU_PGFAULT_PERM_WRITE);
+ if (!last_page) {
+ continue;
+ }
+
+ if (!ret) {
+ VTDPRQEntry *prqe = g_malloc0(sizeof(*prqe));
+
+ prqe->grpid = fault->grpid;
+ prqe->cookie = fault->cookie;
+ QLIST_INSERT_HEAD(&vtd_pce->vtd_prq_list, prqe, next);
+ continue;
+ }
- vtd_pri_request_page(vtd_hiod->bus, vtd_hiod->iommu_state,
- vtd_hiod->devfn, pasid,
- fault->perm & IOMMU_PGFAULT_PERM_PRIV,
- fault->perm & IOMMU_PGFAULT_PERM_EXEC,
- fault->addr, last_page, fault->grpid,
- fault->perm & IOMMU_PGFAULT_PERM_READ,
- fault->perm & IOMMU_PGFAULT_PERM_WRITE);
+ /*
+ * vt-d spec 7.4.1:
+ *
+ * Hardware generates page group response with code of success for
+ * PRQ overflow and PRQ full, with code of invalid request for
+ * other error conditions.
+ */
+ if (ret == -ENOSPC) {
+ vtd_write_fs_faultq(vtd_pce, fault->cookie,
+ IOMMUFD_PAGE_RESP_SUCCESS);
+ } else {
+ vtd_write_fs_faultq(vtd_pce, fault->cookie,
+ IOMMUFD_PAGE_RESP_INVALID);
+ }
}
}
@@ -433,6 +517,7 @@ static void vtd_accel_fill_pc(VTDHostIOMMUDevice *vtd_hiod, uint32_t pasid,
vtd_pce->pasid = pasid;
vtd_pce->pasid_entry = *pe;
vtd_pce->fault_fd = -1;
+ QLIST_INIT(&vtd_pce->vtd_prq_list);
QLIST_INSERT_HEAD(&vtd_hiod->pasid_cache_list, vtd_pce, next);
if (!vtd_device_attach_iommufd(vtd_pce, &local_err)) {
diff --git a/hw/i386/trace-events b/hw/i386/trace-events
index ad84d106a4..7bf4cddd38 100644
--- a/hw/i386/trace-events
+++ b/hw/i386/trace-events
@@ -78,6 +78,7 @@ vtd_device_attach_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwpt_id, int re
vtd_device_detach_hwpt(uint32_t dev_id, uint32_t pasid, int ret) "dev_id %d pasid %d ret: %d"
vtd_device_reattach_def_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwpt_id, int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d"
vtd_read_fs_faultq(uint32_t fault_id, uint32_t fault_fd, ssize_t ret) "fault_id %d fault_fd %d ret: %zd"
+vtd_write_fs_faultq(uint32_t fault_id, uint32_t fault_fd, uint32_t cookie, uint32_t code, ssize_t ret) "fault_id %d fault_fd %d cookie %d code %d ret: %zd"
# amd_iommu.c
amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at addr 0x%"PRIx64" + offset 0x%"PRIx32
--
2.52.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v8 6/6] intel_iommu_accel: teardown FAULTQ resources in bottom half
2026-10-09 9:07 [PATCH v8 0/6] intel_iommu: Enable PRQ support for passthrough device Zhenzhong Duan
` (4 preceding siblings ...)
2026-10-09 9:07 ` [PATCH v8 5/6] intel_iommu_accel: Accept PRQ response " Zhenzhong Duan
@ 2026-10-09 9:07 ` Zhenzhong Duan
5 siblings, 0 replies; 9+ messages in thread
From: Zhenzhong Duan @ 2026-10-09 9:07 UTC (permalink / raw)
To: qemu-devel
Cc: alex, clg, eric.auger, mst, jasowangio, jgg, nicolinc,
skolothumtho, joao.m.martins, clement.mathieu--drif, kevin.tian,
yi.l.liu, Zhenzhong Duan, Xudong Hao
When a pasid entry becomes invalid, we need to release all resources
allocated for that entry including FAULTQ object and fault_fd.
We call qemu_set_fd_handler() to detach fault_fd's io_read handler and
wakes up main thread from poll(), but there could still be a small
window we call iommufd_backend_free_id(fault_id) before poll() exit
and release fault_id file reference. In this rare case, FAULTQ object
free return -EBUSY because opened fault_id file keeps reference of
FAULTQ object.
Teardown FAULTQ resources in bottom half to ensure poll() has released
fault_id file reference.
Suggested-by: Shameer Kolothum <skolothumtho@nvidia.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Tested-by: Xudong Hao <xudong.hao@intel.com>
---
hw/i386/intel_iommu_accel.c | 40 ++++++++++++++++++++++++++++++++++---
1 file changed, 37 insertions(+), 3 deletions(-)
diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c
index cd227315da..c07ffa68e0 100644
--- a/hw/i386/intel_iommu_accel.c
+++ b/hw/i386/intel_iommu_accel.c
@@ -268,17 +268,51 @@ free_faultq:
return false;
}
+typedef struct IOMMUFaultQueue {
+ IOMMUFDBackend *iommufd;
+ uint32_t id;
+ int fd;
+ QLIST_HEAD(, VTDPRQEntry) vtd_prq_list;
+} IOMMUFaultQueue;
+
+static void faultq_teardown_bh(void *opaque)
+{
+ IOMMUFaultQueue *fq = opaque;
+ VTDPRQEntry *prqe, *next;
+
+ QLIST_FOREACH_SAFE(prqe, &fq->vtd_prq_list, next, next) {
+ QLIST_REMOVE(prqe, next);
+ g_free(prqe);
+ }
+
+ qemu_set_fd_handler(fq->fd, NULL, NULL, NULL);
+ close(fq->fd);
+ iommufd_backend_free_id(fq->iommufd, fq->id);
+
+ g_free(fq);
+}
+
static void vtd_destroy_old_fs_faultq(VTDAccelPASIDCacheEntry *vtd_pce)
{
+ HostIOMMUDeviceIOMMUFD *idev =
+ HOST_IOMMU_DEVICE_IOMMUFD(vtd_pce->vtd_hiod->hiod);
+ IOMMUFaultQueue *fq;
+
if (vtd_pce->fault_fd < 0) {
return;
}
- qemu_set_fd_handler(vtd_pce->fault_fd, NULL, NULL, NULL);
- vtd_destroy_fs_faultq(vtd_pce->vtd_hiod, vtd_pce->fault_id,
- vtd_pce->fault_fd);
+ fq = g_malloc(sizeof(*fq));
+ fq->iommufd = idev->iommufd;
+ fq->fd = vtd_pce->fault_fd;
+ fq->id = vtd_pce->fault_id;
vtd_pce->fault_id = 0;
vtd_pce->fault_fd = -1;
+ fq->vtd_prq_list.lh_first = vtd_pce->vtd_prq_list.lh_first;
+ QLIST_INIT(&vtd_pce->vtd_prq_list);
+
+ aio_bh_schedule_oneshot(iohandler_get_aio_context(),
+ faultq_teardown_bh, fq);
}
static void vtd_setup_fs_faultq(VTDAccelPASIDCacheEntry *vtd_pce,
--
2.52.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v8 2/6] backends/iommufd: Introduce iommufd_backend_alloc_faultq
2026-10-09 9:07 ` [PATCH v8 2/6] backends/iommufd: Introduce iommufd_backend_alloc_faultq Zhenzhong Duan
@ 2026-10-09 20:24 ` Nicolin Chen
0 siblings, 0 replies; 9+ messages in thread
From: Nicolin Chen @ 2026-10-09 20:24 UTC (permalink / raw)
To: Zhenzhong Duan
Cc: qemu-devel, alex, clg, eric.auger, mst, jasowangio, jgg,
skolothumtho, joao.m.martins, clement.mathieu--drif, kevin.tian,
yi.l.liu, Xudong Hao
On Fri, Oct 09, 2026 at 05:07:32PM +0800, Zhenzhong Duan wrote:
> Add a new helper for IOMMU_FAULT_QUEUE_ALLOC ioctl to allocate a fault
> handling object which will be used in hwpt allocation.
>
> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
> Reviewed-by: Clement Mathieu--Drif <clement.mathieu--drif@bull.com>
> Reviewed-by: Yi Liu <yi.l.liu@intel.com>
> Tested-by: Xudong Hao <xudong.hao@intel.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v8 3/6] backends/iommufd: Extend iommufd_backend_alloc_hwpt() with fault_id
2026-10-09 9:07 ` [PATCH v8 3/6] backends/iommufd: Extend iommufd_backend_alloc_hwpt() with fault_id Zhenzhong Duan
@ 2026-10-09 20:26 ` Nicolin Chen
0 siblings, 0 replies; 9+ messages in thread
From: Nicolin Chen @ 2026-10-09 20:26 UTC (permalink / raw)
To: Zhenzhong Duan
Cc: qemu-devel, alex, clg, eric.auger, mst, jasowangio, jgg,
skolothumtho, joao.m.martins, clement.mathieu--drif, kevin.tian,
yi.l.liu, Xudong Hao, qemu-arm
On Fri, Oct 09, 2026 at 05:07:33PM +0800, Zhenzhong Duan wrote:
> We should set flags IOMMU_HWPT_FAULT_ID_VALID when pass in a fault
> object id in the caller.
>
> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
> Reviewed-by: Clement Mathieu--Drif <clement.mathieu--drif@bull.com>
> Reviewed-by: Yi Liu <yi.l.liu@intel.com>
> Tested-by: Xudong Hao <xudong.hao@intel.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2026-10-09 20:30 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-10-09 9:07 [PATCH v8 0/6] intel_iommu: Enable PRQ support for passthrough device Zhenzhong Duan
2026-10-09 9:07 ` [PATCH v8 1/6] intel_iommu_accel: Guard VTDAccelPASIDCacheEntry definition Zhenzhong Duan
2026-10-09 9:07 ` [PATCH v8 2/6] backends/iommufd: Introduce iommufd_backend_alloc_faultq Zhenzhong Duan
2026-10-09 20:24 ` Nicolin Chen
2026-10-09 9:07 ` [PATCH v8 3/6] backends/iommufd: Extend iommufd_backend_alloc_hwpt() with fault_id Zhenzhong Duan
2026-10-09 20:26 ` Nicolin Chen
2026-10-09 9:07 ` [PATCH v8 4/6] intel_iommu_accel: Add PRQ injection for passthrough device Zhenzhong Duan
2026-10-09 9:07 ` [PATCH v8 5/6] intel_iommu_accel: Accept PRQ response " Zhenzhong Duan
2026-10-09 9:07 ` [PATCH v8 6/6] intel_iommu_accel: teardown FAULTQ resources in bottom half Zhenzhong Duan
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