From: Francesco Dolcini <francesco.dolcini@toradex.com>
To: ye.li@oss.nxp.com
Cc: festevam@gmail.com, u-boot@lists.u-boot-project.org,
emanuele.ghidoli@toradex.com, peng.fan@nxp.com,
uboot-imx@nxp.com, alice.guo@nxp.com, ye.li@nxp.com
Subject: Re: [PATCH 2/2] toradex: {aquila, smarc, verdin}-imx95: Enable caches in SPL
Date: Sun, 11 Oct 2026 11:17:54 +0200 [thread overview]
Message-ID: <astUQpojAQPoglo7@francesco-nb> (raw)
In-Reply-To: <20261010075951.3939861-2-ye.li@oss.nxp.com>
On Sat, Oct 10, 2026 at 03:59:51PM +0800, ye.li@oss.nxp.com wrote:
> From: Ye Li <ye.li@nxp.com>
>
> To enable icache and dcache in SPL, add the definition of secure DDR
> space which could be accessed by SPL and move arch_cpu_init before
> spl_early_init.
>
> Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
next prev parent reply other threads:[~2026-10-11 9:18 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-10 7:59 [PATCH 1/2] imx9: scmi: Move u-boot early MMU table to top 2MB of first 64MB DDR ye.li
2026-10-10 7:59 ` [PATCH 2/2] toradex: {aquila, smarc, verdin}-imx95: Enable caches in SPL ye.li
2026-10-11 9:17 ` Francesco Dolcini [this message]
2026-10-13 8:44 ` Emanuele Ghidoli
2026-10-11 9:16 ` [PATCH 1/2] imx9: scmi: Move u-boot early MMU table to top 2MB of first 64MB DDR Francesco Dolcini
2026-10-13 8:03 ` Emanuele Ghidoli
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