From: Francesco Dolcini <francesco.dolcini@toradex.com>
To: emanuele.ghidoli@toradex.com, ye.li@oss.nxp.com
Cc: festevam@gmail.com, u-boot@lists.u-boot-project.org,
peng.fan@nxp.com, uboot-imx@nxp.com, alice.guo@nxp.com,
ye.li@nxp.com
Subject: Re: [PATCH 1/2] imx9: scmi: Move u-boot early MMU table to top 2MB of first 64MB DDR
Date: Sun, 11 Oct 2026 11:16:42 +0200 [thread overview]
Message-ID: <astT-nyb5riMAC38@francesco-nb> (raw)
In-Reply-To: <20261010075951.3939861-1-ye.li@oss.nxp.com>
Hello Ye,
thanks for the patch, appreciated.
On Sat, Oct 10, 2026 at 03:59:50PM +0800, ye.li@oss.nxp.com wrote:
> From: Ye Li <ye.li@nxp.com>
>
> The default u-boot early MMU table address is at CFG_SYS_SDRAM_BASE.
> The same address is used as alias target on Toradex's iMX95 boards in
> RAM-size probe. When a probe address aliases that location, the test
> temporarily overwrites an entry in the active page tables.
>
> To avoid such overlap, move u-boot early MMU table to top 2MB of first
> 64MB DDR.
>
> Signed-off-by: Ye Li <ye.li@nxp.com>
Emanuele, can you please review this and the following one?
Francesco
next prev parent reply other threads:[~2026-10-11 9:16 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-10 7:59 [PATCH 1/2] imx9: scmi: Move u-boot early MMU table to top 2MB of first 64MB DDR ye.li
2026-10-10 7:59 ` [PATCH 2/2] toradex: {aquila, smarc, verdin}-imx95: Enable caches in SPL ye.li
2026-10-11 9:17 ` Francesco Dolcini
2026-10-13 8:44 ` Emanuele Ghidoli
2026-10-11 9:16 ` Francesco Dolcini [this message]
2026-10-13 8:03 ` [PATCH 1/2] imx9: scmi: Move u-boot early MMU table to top 2MB of first 64MB DDR Emanuele Ghidoli
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