All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH 1/2] imx9: scmi: Move u-boot early MMU table to top 2MB of first 64MB DDR
@ 2026-10-10  7:59 ye.li
  2026-10-10  7:59 ` [PATCH 2/2] toradex: {aquila, smarc, verdin}-imx95: Enable caches in SPL ye.li
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: ye.li @ 2026-10-10  7:59 UTC (permalink / raw)
  To: festevam, u-boot, francesco.dolcini, emanuele.ghidoli
  Cc: peng.fan, uboot-imx, alice.guo, ye.li

From: Ye Li <ye.li@nxp.com>

The default u-boot early MMU table address is at CFG_SYS_SDRAM_BASE.
The same address is used as alias target on Toradex's iMX95 boards in
RAM-size probe. When a probe address aliases that location, the test
temporarily overwrites an entry in the active page tables.

To avoid such overlap, move u-boot early MMU table to top 2MB of first
64MB DDR.

Signed-off-by: Ye Li <ye.li@nxp.com>
---
 arch/arm/mach-imx/imx9/scmi/soc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c
index 22f9c9d045b..fa6b9a0e53d 100644
--- a/arch/arm/mach-imx/imx9/scmi/soc.c
+++ b/arch/arm/mach-imx/imx9/scmi/soc.c
@@ -613,9 +613,12 @@ __weak unsigned long board_spl_mmu_tlb_base(void)
 #endif
 }
 
+/* Uboot early MMU only map first 64MB DDR before DM init.
+ * Set default early MMU table at top 2MB of first 64MB DDR
+ */
 __weak unsigned long board_early_mmu_tlb_base(void)
 {
-	return CFG_SYS_SDRAM_BASE;
+	return CFG_SYS_SDRAM_BASE + SZ_64M - SZ_2M;
 }
 
 /*
-- 
2.50.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [PATCH 2/2] toradex: {aquila, smarc, verdin}-imx95: Enable caches in SPL
  2026-10-10  7:59 [PATCH 1/2] imx9: scmi: Move u-boot early MMU table to top 2MB of first 64MB DDR ye.li
@ 2026-10-10  7:59 ` ye.li
  2026-10-11  9:17   ` Francesco Dolcini
  2026-10-13  8:44   ` Emanuele Ghidoli
  2026-10-11  9:16 ` [PATCH 1/2] imx9: scmi: Move u-boot early MMU table to top 2MB of first 64MB DDR Francesco Dolcini
  2026-10-13  8:03 ` Emanuele Ghidoli
  2 siblings, 2 replies; 6+ messages in thread
From: ye.li @ 2026-10-10  7:59 UTC (permalink / raw)
  To: festevam, u-boot, francesco.dolcini, emanuele.ghidoli
  Cc: peng.fan, uboot-imx, alice.guo, ye.li

From: Ye Li <ye.li@nxp.com>

To enable icache and dcache in SPL, add the definition of secure DDR
space which could be accessed by SPL and move arch_cpu_init before
spl_early_init.

Signed-off-by: Ye Li <ye.li@nxp.com>
---
 board/toradex/aquila-imx95/spl.c      | 4 ++--
 board/toradex/smarc-imx95/spl.c       | 4 ++--
 board/toradex/verdin-imx95/spl.c      | 4 ++--
 include/configs/aquila-imx95.h        | 2 +-
 include/configs/toradex-smarc-imx95.h | 3 +++
 include/configs/verdin-imx95.h        | 3 +++
 6 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/board/toradex/aquila-imx95/spl.c b/board/toradex/aquila-imx95/spl.c
index 93e76be6145..31730fc22c8 100644
--- a/board/toradex/aquila-imx95/spl.c
+++ b/board/toradex/aquila-imx95/spl.c
@@ -58,6 +58,8 @@ void board_init_f(ulong dummy)
 
 	timer_init();
 
+	arch_cpu_init();
+
 	/* Need dm_init() to run before any SCMI calls */
 	spl_early_init();
 
@@ -66,8 +68,6 @@ void board_init_f(ulong dummy)
 	if (ret)
 		hang(); /* MU not probed, nothing can be outputed, hang */
 
-	arch_cpu_init();
-
 	preloader_console_init();
 
 	debug("SOC: 0x%x\n", gd->arch.soc_rev);
diff --git a/board/toradex/smarc-imx95/spl.c b/board/toradex/smarc-imx95/spl.c
index aebb4a2f0b6..a3fd11a50db 100644
--- a/board/toradex/smarc-imx95/spl.c
+++ b/board/toradex/smarc-imx95/spl.c
@@ -99,6 +99,8 @@ void board_init_f(ulong dummy)
 
 	timer_init();
 
+	arch_cpu_init();
+
 	/* Need dm_init() to run before any SCMI calls */
 	spl_early_init();
 
@@ -107,8 +109,6 @@ void board_init_f(ulong dummy)
 	if (ret)
 		hang(); /* MU not probed, nothing can be outputed, hang */
 
-	arch_cpu_init();
-
 	preloader_console_init();
 
 	debug("SOC: 0x%x\n", gd->arch.soc_rev);
diff --git a/board/toradex/verdin-imx95/spl.c b/board/toradex/verdin-imx95/spl.c
index 93e76be6145..31730fc22c8 100644
--- a/board/toradex/verdin-imx95/spl.c
+++ b/board/toradex/verdin-imx95/spl.c
@@ -58,6 +58,8 @@ void board_init_f(ulong dummy)
 
 	timer_init();
 
+	arch_cpu_init();
+
 	/* Need dm_init() to run before any SCMI calls */
 	spl_early_init();
 
@@ -66,8 +68,6 @@ void board_init_f(ulong dummy)
 	if (ret)
 		hang(); /* MU not probed, nothing can be outputed, hang */
 
-	arch_cpu_init();
-
 	preloader_console_init();
 
 	debug("SOC: 0x%x\n", gd->arch.soc_rev);
diff --git a/include/configs/aquila-imx95.h b/include/configs/aquila-imx95.h
index 96c11ff2d5b..9c48d2b2736 100644
--- a/include/configs/aquila-imx95.h
+++ b/include/configs/aquila-imx95.h
@@ -26,6 +26,6 @@
 #define PHYS_SDRAM_2_SIZE	SZ_6G
 
 #define CFG_SYS_SECURE_SDRAM_BASE	0x8A000000 /* Secure DDR region for A55, SPL could use first 2MB */
-#define CFG_SYS_SECURE_SDRAM_SIZE	0x06000000
+#define CFG_SYS_SECURE_SDRAM_SIZE	SZ_64M
 
 #endif
diff --git a/include/configs/toradex-smarc-imx95.h b/include/configs/toradex-smarc-imx95.h
index 97e3322ac28..5e23db7c9e5 100644
--- a/include/configs/toradex-smarc-imx95.h
+++ b/include/configs/toradex-smarc-imx95.h
@@ -22,4 +22,7 @@
 #define PHYS_SDRAM_SIZE		(SZ_2G - PHYS_SDRAM_FW_RSVD)
 #define PHYS_SDRAM_2_SIZE	SZ_6G
 
+#define CFG_SYS_SECURE_SDRAM_BASE      0x8A000000 /* Secure DDR region for A55 */
+#define CFG_SYS_SECURE_SDRAM_SIZE      SZ_64M
+
 #endif
diff --git a/include/configs/verdin-imx95.h b/include/configs/verdin-imx95.h
index b6df4d48695..87085cc8719 100644
--- a/include/configs/verdin-imx95.h
+++ b/include/configs/verdin-imx95.h
@@ -22,4 +22,7 @@
 #define PHYS_SDRAM_SIZE		(SZ_2G - PHYS_SDRAM_FW_RSVD)
 #define PHYS_SDRAM_2_SIZE	SZ_30G
 
+#define CFG_SYS_SECURE_SDRAM_BASE      0x8A000000 /* Secure DDR region for A55 */
+#define CFG_SYS_SECURE_SDRAM_SIZE      SZ_64M
+
 #endif
-- 
2.50.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [PATCH 1/2] imx9: scmi: Move u-boot early MMU table to top 2MB of first 64MB DDR
  2026-10-10  7:59 [PATCH 1/2] imx9: scmi: Move u-boot early MMU table to top 2MB of first 64MB DDR ye.li
  2026-10-10  7:59 ` [PATCH 2/2] toradex: {aquila, smarc, verdin}-imx95: Enable caches in SPL ye.li
@ 2026-10-11  9:16 ` Francesco Dolcini
  2026-10-13  8:03 ` Emanuele Ghidoli
  2 siblings, 0 replies; 6+ messages in thread
From: Francesco Dolcini @ 2026-10-11  9:16 UTC (permalink / raw)
  To: emanuele.ghidoli, ye.li
  Cc: festevam, u-boot, peng.fan, uboot-imx, alice.guo, ye.li

Hello Ye,
thanks for the patch, appreciated.


On Sat, Oct 10, 2026 at 03:59:50PM +0800, ye.li@oss.nxp.com wrote:
> From: Ye Li <ye.li@nxp.com>
> 
> The default u-boot early MMU table address is at CFG_SYS_SDRAM_BASE.
> The same address is used as alias target on Toradex's iMX95 boards in
> RAM-size probe. When a probe address aliases that location, the test
> temporarily overwrites an entry in the active page tables.
> 
> To avoid such overlap, move u-boot early MMU table to top 2MB of first
> 64MB DDR.
> 
> Signed-off-by: Ye Li <ye.li@nxp.com>

Emanuele, can you please review this and the following one?

Francesco


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 2/2] toradex: {aquila, smarc, verdin}-imx95: Enable caches in SPL
  2026-10-10  7:59 ` [PATCH 2/2] toradex: {aquila, smarc, verdin}-imx95: Enable caches in SPL ye.li
@ 2026-10-11  9:17   ` Francesco Dolcini
  2026-10-13  8:44   ` Emanuele Ghidoli
  1 sibling, 0 replies; 6+ messages in thread
From: Francesco Dolcini @ 2026-10-11  9:17 UTC (permalink / raw)
  To: ye.li
  Cc: festevam, u-boot, emanuele.ghidoli, peng.fan, uboot-imx,
	alice.guo, ye.li

On Sat, Oct 10, 2026 at 03:59:51PM +0800, ye.li@oss.nxp.com wrote:
> From: Ye Li <ye.li@nxp.com>
> 
> To enable icache and dcache in SPL, add the definition of secure DDR
> space which could be accessed by SPL and move arch_cpu_init before
> spl_early_init.
> 
> Signed-off-by: Ye Li <ye.li@nxp.com>

Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 1/2] imx9: scmi: Move u-boot early MMU table to top 2MB of first 64MB DDR
  2026-10-10  7:59 [PATCH 1/2] imx9: scmi: Move u-boot early MMU table to top 2MB of first 64MB DDR ye.li
  2026-10-10  7:59 ` [PATCH 2/2] toradex: {aquila, smarc, verdin}-imx95: Enable caches in SPL ye.li
  2026-10-11  9:16 ` [PATCH 1/2] imx9: scmi: Move u-boot early MMU table to top 2MB of first 64MB DDR Francesco Dolcini
@ 2026-10-13  8:03 ` Emanuele Ghidoli
  2 siblings, 0 replies; 6+ messages in thread
From: Emanuele Ghidoli @ 2026-10-13  8:03 UTC (permalink / raw)
  To: ye.li, festevam, u-boot, francesco.dolcini, emanuele.ghidoli
  Cc: peng.fan, uboot-imx, alice.guo, ye.li



On 10/10/26 09:59, ye.li@oss.nxp.com wrote:
> From: Ye Li <ye.li@nxp.com>
> 
> The default u-boot early MMU table address is at CFG_SYS_SDRAM_BASE.
> The same address is used as alias target on Toradex's iMX95 boards in
> RAM-size probe. When a probe address aliases that location, the test
> temporarily overwrites an entry in the active page tables.
> 
> To avoid such overlap, move u-boot early MMU table to top 2MB of first
> 64MB DDR.
> 
> Signed-off-by: Ye Li <ye.li@nxp.com>
> ---
>  arch/arm/mach-imx/imx9/scmi/soc.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c
> index 22f9c9d045b..fa6b9a0e53d 100644
> --- a/arch/arm/mach-imx/imx9/scmi/soc.c
> +++ b/arch/arm/mach-imx/imx9/scmi/soc.c
> @@ -613,9 +613,12 @@ __weak unsigned long board_spl_mmu_tlb_base(void)
>  #endif
>  }
>  
> +/* Uboot early MMU only map first 64MB DDR before DM init.
> + * Set default early MMU table at top 2MB of first 64MB DDR
> + */
>  __weak unsigned long board_early_mmu_tlb_base(void)
>  {
> -	return CFG_SYS_SDRAM_BASE;
> +	return CFG_SYS_SDRAM_BASE + SZ_64M - SZ_2M;
>  }
>  
>  /*
Hello Ye,
thanks for the patch.

Reviewed-by: Emanuele Ghidoli <ghidoliemanuele@gmail.com>
Tested-by:  Emanuele Ghidoli <ghidoliemanuele@gmail.com>

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 2/2] toradex: {aquila, smarc, verdin}-imx95: Enable caches in SPL
  2026-10-10  7:59 ` [PATCH 2/2] toradex: {aquila, smarc, verdin}-imx95: Enable caches in SPL ye.li
  2026-10-11  9:17   ` Francesco Dolcini
@ 2026-10-13  8:44   ` Emanuele Ghidoli
  1 sibling, 0 replies; 6+ messages in thread
From: Emanuele Ghidoli @ 2026-10-13  8:44 UTC (permalink / raw)
  To: ye.li, festevam, u-boot, francesco.dolcini, emanuele.ghidoli
  Cc: peng.fan, uboot-imx, alice.guo, ye.li



On 10/10/26 09:59, ye.li@oss.nxp.com wrote:
> From: Ye Li <ye.li@nxp.com>
> 
> To enable icache and dcache in SPL, add the definition of secure DDR
> space which could be accessed by SPL and move arch_cpu_init before
> spl_early_init.
> 
> Signed-off-by: Ye Li <ye.li@nxp.com>
> ---
>  board/toradex/aquila-imx95/spl.c      | 4 ++--
>  board/toradex/smarc-imx95/spl.c       | 4 ++--
>  board/toradex/verdin-imx95/spl.c      | 4 ++--
>  include/configs/aquila-imx95.h        | 2 +-
>  include/configs/toradex-smarc-imx95.h | 3 +++
>  include/configs/verdin-imx95.h        | 3 +++
>  6 files changed, 13 insertions(+), 7 deletions(-)
> 
> diff --git a/board/toradex/aquila-imx95/spl.c b/board/toradex/aquila-imx95/spl.c
> [...]
Hello Ye,

Nit: spaces instead of tabs after the added #defines in
toradex-smarc-imx95.h and verdin-imx95.h.

Reviewed-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Tested-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2026-10-13  8:44 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-10-10  7:59 [PATCH 1/2] imx9: scmi: Move u-boot early MMU table to top 2MB of first 64MB DDR ye.li
2026-10-10  7:59 ` [PATCH 2/2] toradex: {aquila, smarc, verdin}-imx95: Enable caches in SPL ye.li
2026-10-11  9:17   ` Francesco Dolcini
2026-10-13  8:44   ` Emanuele Ghidoli
2026-10-11  9:16 ` [PATCH 1/2] imx9: scmi: Move u-boot early MMU table to top 2MB of first 64MB DDR Francesco Dolcini
2026-10-13  8:03 ` Emanuele Ghidoli

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.