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From: Manivannan Sadhasivam <mani@kernel.org>
To: Xu Yang <xu.yang_2@oss.nxp.com>
Cc: ivaylo <ivo.ivanov.ivanov1@gmail.com>,
	vkoul@kernel.org,  neil.armstrong@linaro.org,
	dmitry.baryshkov@oss.qualcomm.com, linux-phy@lists.infradead.org,
	 linux-kernel@vger.kernel.org, imx@lists.linux.dev
Subject: Re: [PATCH] phy: phy-snps-eusb2: fix FSEL_48_MHZ_VAL definition
Date: Mon, 12 Oct 2026 15:13:45 +0530	[thread overview]
Message-ID: <asyrexEOKzZkoD23@debian> (raw)
In-Reply-To: <ogfpkqixf3xkyvh4bbpvui5ybfaro6g35g6u5kb56k2jsyrsmt@jm67at6cpksf>

On Wed, Sep 09, 2026 at 10:49:41AM +0800, Xu Yang wrote:
> On Tue, Sep 08, 2026 at 04:17:57PM +0400, ivaylo wrote:
> > On 8.09.26 12:59, Xu Yang wrote:
> > > From: Xu Yang <xu.yang_2@nxp.com>
> > > 
> > > According to Synopsys eUSB2 PHY Databook, FSEL_48_MHZ_VAL should be 0x6
> > > for supported 48 MHz reference clock.
> > 
> > I don't see this as a justified change. Samsung's implementation of eUSB2
> > differs from the generic Synopsys interface, as is visible from the
> > differences
> > between QCOM's implementation and Samsung's.
> > 
> > From what I see for exynos2200, the FSEL value is 0x2 for both 24 MHz and
> > 48 MHz. The differentiating part is that the upper PLL divider is 0x0 for 24
> > MHz
> > and 0x1 for 48 MHz. The current programming was taken from the samsung\
> 
> For Product Code H483-0, it's 0x2 for 24 MHz and 0x6 for 48 MHz. The PLL divider
> is 0x0 for 24 MHz and 0x1 for 48 MHz too. So it does seem like something mismatch
> in your side. Because the FSEL_*_MHZ_VAL is common definition in the driver, this
> means FSEL_48_MHZ_VAL is not common anymore. But if you have confirmed it's simply
> like that, it's fine. Others need to add their specific definition in the future.
> 

If the values differ between vendor implementations, then please deal with it
using compatible check or drvdata.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

WARNING: multiple messages have this Message-ID (diff)
From: Manivannan Sadhasivam <mani@kernel.org>
To: Xu Yang <xu.yang_2@oss.nxp.com>
Cc: ivaylo <ivo.ivanov.ivanov1@gmail.com>,
	vkoul@kernel.org,  neil.armstrong@linaro.org,
	dmitry.baryshkov@oss.qualcomm.com, linux-phy@lists.infradead.org,
	 linux-kernel@vger.kernel.org, imx@lists.linux.dev
Subject: Re: [PATCH] phy: phy-snps-eusb2: fix FSEL_48_MHZ_VAL definition
Date: Mon, 12 Oct 2026 15:13:45 +0530	[thread overview]
Message-ID: <asyrexEOKzZkoD23@debian> (raw)
In-Reply-To: <ogfpkqixf3xkyvh4bbpvui5ybfaro6g35g6u5kb56k2jsyrsmt@jm67at6cpksf>

On Wed, Sep 09, 2026 at 10:49:41AM +0800, Xu Yang wrote:
> On Tue, Sep 08, 2026 at 04:17:57PM +0400, ivaylo wrote:
> > On 8.09.26 12:59, Xu Yang wrote:
> > > From: Xu Yang <xu.yang_2@nxp.com>
> > > 
> > > According to Synopsys eUSB2 PHY Databook, FSEL_48_MHZ_VAL should be 0x6
> > > for supported 48 MHz reference clock.
> > 
> > I don't see this as a justified change. Samsung's implementation of eUSB2
> > differs from the generic Synopsys interface, as is visible from the
> > differences
> > between QCOM's implementation and Samsung's.
> > 
> > From what I see for exynos2200, the FSEL value is 0x2 for both 24 MHz and
> > 48 MHz. The differentiating part is that the upper PLL divider is 0x0 for 24
> > MHz
> > and 0x1 for 48 MHz. The current programming was taken from the samsung\
> 
> For Product Code H483-0, it's 0x2 for 24 MHz and 0x6 for 48 MHz. The PLL divider
> is 0x0 for 24 MHz and 0x1 for 48 MHz too. So it does seem like something mismatch
> in your side. Because the FSEL_*_MHZ_VAL is common definition in the driver, this
> means FSEL_48_MHZ_VAL is not common anymore. But if you have confirmed it's simply
> like that, it's fine. Others need to add their specific definition in the future.
> 

If the values differ between vendor implementations, then please deal with it
using compatible check or drvdata.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

  reply	other threads:[~2026-10-12  9:43 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-08  8:59 [PATCH] phy: phy-snps-eusb2: fix FSEL_48_MHZ_VAL definition Xu Yang
2026-09-08  8:59 ` Xu Yang
2026-09-08  9:04 ` sashiko-bot
2026-09-08  9:04   ` sashiko-bot
2026-09-08 12:17 ` ivaylo
2026-09-08 12:17   ` ivaylo
2026-09-09  2:49   ` Xu Yang
2026-09-09  2:49     ` Xu Yang
2026-10-12  9:43     ` Manivannan Sadhasivam [this message]
2026-10-12  9:43       ` Manivannan Sadhasivam

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