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* [PATCH 00/12] Add the RCPU to Tenstorrent Atlantis
@ 2026-10-15  3:17 Portia Stephens
  2026-10-15  3:17 ` [PATCH 01/12] hw/riscv/atlantis: Set valid_cpu_types for Atlantis machine Portia Stephens
                   ` (11 more replies)
  0 siblings, 12 replies; 16+ messages in thread
From: Portia Stephens @ 2026-10-15  3:17 UTC (permalink / raw)
  To: qemu-devel
  Cc: Nicholas Piggin, Palmer Dabbelt, Chao Liu, Alistair Francis,
	qemu-riscv, Philippe Mathieu-Daudé, Paolo Bonzini,
	Joel Stanley, Liu Zhiwei, Alex Bennée, Pierrick Bouvier,
	Weiwei Li, Anirudh Srinivasan, Richard Henderson, Zhao Liu,
	Daniel Henrique Barboza, Portia Stephens, Michael Ellerman

Atlantis includes a 32-bit RISC-V core (RCPU) used for boot, low-level
control, and ongoing system management [1]. This series is the first step in
adding the RCPU to the tt-atlantis machine. The RCPU shares access to most
peripherals with the Ascalon cores. However, the RCPU has a different memory view.
This requires a different memory map and a private memory container that the
SoC aliases the shared devices into, at the addresses the RCPU expects.

On hardware, the RCPU is responsible for loading images from the boot medium
into DRAM and releasing the Ascalon cores from reset, via the CPL. This
functionality is not implemented in these changes. The images for the Ascalon
cores continue to be loaded directly into DRAM via command line arguments and
the Ascalon cores start executing at reset.

With these changes, running tt-atlantis with rcpu=on will create a separate
CPUCluster with the RCPU, giving gdb two inferiors. If no bootrom is provided,
the RCPU hart will be held powered off. With a bootrom provided,
via tt-atlantis,rcpu=on,bootrom=, the RCPU will execute the image and console
output is on the second command line serial. This series does not provide a
binary to test on the RCPU, it is in active development and not publicly
available. The QEMU tests are updated to test booting of the Ascalon cores with
and without the RCPU modeled. The machine properties related to the cpus, smp
count and cpu-type, apply to the Ascalon cluster. The RCPU is an auxiliary
core and is not configurable.

See docs/system/riscv/tt_atlantis.rst for usage.

[1] https://github.com/tenstorrent/atlantis-soc-docs/blob/main/data_sheet/atl_soc_data_sheet.pdf

Joel Stanley (1):
  machine: Support extra board CPUs outside -smp

Portia Stephens (11):
  hw/riscv/atlantis: Set valid_cpu_types for Atlantis machine
  hw/riscv/atlantis: Update fdt functions to take generic parameters
  hw/riscv/atlantis: Move Ascalon into cluster struct
  hw/riscv/atlantis: Store Ascalon memory in cluster struct
  hw/riscv/atlantis: Create CPU cluster for Atlantis cpus
  target/riscv: Add Tenstorrent Real-time CPU
  hw/riscv/atlantis: Add the RCPU to the Atlantis SoC
  hw/riscv/atlantis: Back RCPU memory region by unimplemented device
  hw/riscv/atlantis: Load the RCPU bootrom
  tests/functional/riscv64: Add rcpu to tt-atlantis tests
  docs/atlantis: Update Atlantis documentation to include the RCPU

 MAINTAINERS                                  |   1 +
 accel/tcg/tcg-all.c                          |   2 +-
 docs/system/gdb.rst                          |   2 +
 docs/system/riscv/tt_atlantis.rst            |  30 +
 hw/riscv/Kconfig                             |   2 +
 hw/riscv/tt_atlantis.c                       | 613 +++++++++++++++----
 include/hw/core/boards.h                     |   4 +
 include/hw/riscv/tt_atlantis.h               |  81 ++-
 target/riscv/cpu-qom.h                       |   1 +
 target/riscv/cpu.c                           |  28 +
 target/riscv/tcg/csr.h                       |   3 +
 target/riscv/tcg/meson.build                 |   1 +
 target/riscv/tcg/tt_csr.c                    |  58 ++
 tests/functional/riscv64/test_tt_atlantis.py |  10 +-
 14 files changed, 709 insertions(+), 127 deletions(-)
 create mode 100644 target/riscv/tcg/tt_csr.c

-- 
2.43.0



^ permalink raw reply	[flat|nested] 16+ messages in thread
end of thread, other threads:[~2026-10-16 11:23 UTC | newest]

Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-10-15  3:17 [PATCH 00/12] Add the RCPU to Tenstorrent Atlantis Portia Stephens
2026-10-15  3:17 ` [PATCH 01/12] hw/riscv/atlantis: Set valid_cpu_types for Atlantis machine Portia Stephens
2026-10-15  3:17 ` [PATCH 02/12] hw/riscv/atlantis: Update fdt functions to take generic parameters Portia Stephens
2026-10-15  3:17 ` [PATCH 03/12] hw/riscv/atlantis: Move Ascalon into cluster struct Portia Stephens
2026-10-15  3:17 ` [PATCH 04/12] hw/riscv/atlantis: Store Ascalon memory in " Portia Stephens
2026-10-15  3:17 ` [PATCH 05/12] hw/riscv/atlantis: Create CPU cluster for Atlantis cpus Portia Stephens
2026-10-15  3:17 ` [PATCH 06/12] target/riscv: Add Tenstorrent Real-time CPU Portia Stephens
2026-10-15  3:17 ` [PATCH 07/12] machine: Support extra board CPUs outside -smp Portia Stephens
2026-10-15 20:31   ` Daniel Henrique Barboza
2026-10-16 10:26     ` Daniel P. Berrangé
2026-10-16 11:23       ` Daniel Henrique Barboza
2026-10-15  3:18 ` [PATCH 08/12] hw/riscv/atlantis: Add the RCPU to the Atlantis SoC Portia Stephens
2026-10-15  3:18 ` [PATCH 09/12] hw/riscv/atlantis: Back RCPU memory region by unimplemented device Portia Stephens
2026-10-15  3:18 ` [PATCH 10/12] hw/riscv/atlantis: Load the RCPU bootrom Portia Stephens
2026-10-15  3:18 ` [PATCH 11/12] tests/functional/riscv64: Add rcpu to tt-atlantis tests Portia Stephens
2026-10-15  3:18 ` [PATCH 12/12] docs/atlantis: Update Atlantis documentation to include the RCPU Portia Stephens

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