[PATCH 0/6] perf jevents: Add NVIDIA Tegra410 uncore PMU events and metrics

[PATCH 0/6] perf jevents: Add NVIDIA Tegra410 uncore PMU events and metrics

[Besar Wicaksono]

Add event aliases and derived metrics for the NVIDIA Tegra410 uncore
PMUs.

The series covers the UCF, PCIe, PCIe target, CPU memory latency, and
chip-to-chip interconnect PMUs. It provides symbolic names for the raw
event encodings and metrics for bandwidth, frequency, and average read
latency.

Patch 1 fixes a jevents ordering problem found with this layout: the
uncore events live in arch/arm64/nvidia/t410/sys/, next to the T410 core
events, and without the fix jevents puts the core tlb.json (which sorts
after "sys") into the sys table, so its events are lost from perf list
and perf stat.

Besar Wicaksono (6):
  perf jevents: Process model files before sys subdirectories
  perf jevents: Add support for NVIDIA Tegra410 UCF PMU aliasing
  perf jevents: Add support for NVIDIA Tegra410 PCIE PMU aliasing
  perf jevents: Add support for NVIDIA Tegra410 PCIE-TGT PMU aliasing
  perf jevents: Add support for NVIDIA Tegra410 CPU Memory Latency PMU
    aliasing
  perf jevents: Add support for NVIDIA Tegra410 C2C PMU aliasing

 .../arm64/nvidia/t410/sys/uncore-cpu_mem.json |  48 ++
 .../arm64/nvidia/t410/sys/uncore-nvclink.json |  75 ++
 .../arm64/nvidia/t410/sys/uncore-nvdlink.json |  48 ++
 .../nvidia/t410/sys/uncore-nvlink_c2c.json    | 129 ++++
 .../arm64/nvidia/t410/sys/uncore-pcie.json    | 247 +++++++
 .../nvidia/t410/sys/uncore-pcie_tgt.json      |  93 +++
 .../arm64/nvidia/t410/sys/uncore-ucf.json     | 693 ++++++++++++++++++
 tools/perf/pmu-events/jevents.py              |   4 +-
 8 files changed, 1336 insertions(+), 1 deletion(-)
 create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-cpu_mem.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-nvclink.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-nvdlink.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-nvlink_c2c.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie_tgt.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-ucf.json

-- 
2.43.0

[PATCH 1/6] perf jevents: Process model files before sys subdirectories

[Besar Wicaksono]

jevents walks each directory in name order, mixing files and
subdirectories. When it reaches a sys/ directory inside a model
directory, process_one_file() flushes the model's pending tables and
switches the pending table name to the sys table. After the walk
returns from sys/, nothing switches it back, so model JSON files whose
names sort after "sys" (for example tlb.json) are added to the sys
table. Sys tables are only matched by Compat against uncore PMU
identifiers, so these core events are lost: perf list doesn't show
them and perf stat rejects them.

Visit the files of a directory before its subdirectories, so that all
of a model's JSON files are added to the model's table before a sys/
subdirectory is processed. The generated pmu-events.c is unchanged for
the existing event directories.

Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
---
 tools/perf/pmu-events/jevents.py | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py
index cc143f7e7cdf..ba974b2784b0 100755
--- a/tools/perf/pmu-events/jevents.py
+++ b/tools/perf/pmu-events/jevents.py
@@ -1463,7 +1463,9 @@ def main() -> None:
           action: Callable[[Sequence[str], os.DirEntry], None]) -> None:
     """Replicate the directory/file walking behavior of C's file tree walk."""
     assert _args is not None
-    for item in sorted(os.scandir(path), key=lambda e: e.name):
+    # Visit a directory's files before its subdirectories, because
+    # entering a subdirectory switches the table that files are added to.
+    for item in sorted(os.scandir(path), key=lambda e: (e.is_dir(), e.name)):
       if _args.model != 'all' and item.is_dir():
         # Check if the model matches one in _args.model.
         if len(parents) == _args.model.split(',')[0].count('/'):
-- 
2.43.0

[PATCH 2/6] perf jevents: Add support for NVIDIA Tegra410 UCF PMU aliasing

[Besar Wicaksono]

Add alias support for NVIDIA Tegra410 UCF PMU events and metrics.

Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
---
 .../arm64/nvidia/t410/sys/uncore-ucf.json     | 693 ++++++++++++++++++
 1 file changed, 693 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-ucf.json

diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-ucf.json b/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-ucf.json
new file mode 100644
index 000000000000..37dae2a65fc8
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-ucf.json
@@ -0,0 +1,693 @@
+[
+    {
+        "EventCode": "0x100000000",
+        "EventName": "UCF_CYCLES",
+        "BriefDescription": "Counts UCF cycles using the dedicated PMU cycle counter.",
+        "PublicDescription": "Counts UCF cycles using the PMU's dedicated cycle counter.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "EventCode": "0x1d",
+        "EventName": "UCF_BUS_CYCLES",
+        "BriefDescription": "Counts UCF cycles using a programmable event counter.",
+        "PublicDescription": "Counts UCF cycles using a programmable event counter. The count is identical to UCF_CYCLES. Source and destination filters are ignored.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "EventCode": "0x111",
+        "EventName": "UCF_SLC_ACCESS_RD",
+        "BriefDescription": "Counts read requests from a requester to the SLC.",
+        "PublicDescription": "Counts read requests from a requester to the SLC. A read is a request for which the completer returns data: dataless MakeReadUnique and snoop requests are not reads, and prefetches issued by the cores' L1/L2 caches count as reads rather than as prefetch requests. Filters: src_loc_cpu, src_loc_noncpu and src_rem select the request initiator: local CPU, local non-CPU device or remote socket. dst_loc_cmem, dst_loc_gmem, dst_loc_other and dst_rem select the memory type of the request address: local CMEM, local GMEM, local CXL memory or remote memory; local or remote is determined by the home socket of the address. An unset group counts all.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "EventCode": "0x112",
+        "EventName": "UCF_SLC_ACCESS_WR",
+        "BriefDescription": "Counts write requests from a requester to the SLC.",
+        "PublicDescription": "Counts write requests from a requester to the SLC. A write is a request in which the requester sends data: dataless WriteEvictOrEvict is not a write, and CHI Write*Zero is a write because it eventually consumes DRAM bandwidth although it sends no data over the interface. Filters: src_loc_cpu, src_loc_noncpu and src_rem select the request initiator: local CPU, local non-CPU device or remote socket. dst_loc_cmem, dst_loc_gmem, dst_loc_other and dst_rem select the memory type of the request address: local CMEM, local GMEM, local CXL memory or remote memory; local or remote is determined by the home socket of the address. An unset group counts all.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "EventCode": "0x183",
+        "EventName": "UCF_SLC_ACCESS_DATALESS",
+        "BriefDescription": "Counts CHI Dataless requests to the SLC.",
+        "PublicDescription": "Counts CHI Dataless requests to the SLC. Dataless MakeReadUnique and WriteEvictOrEvict requests are not counted. Filters: src_loc_cpu, src_loc_noncpu and src_rem select the request initiator: local CPU, local non-CPU device or remote socket. dst_loc_cmem, dst_loc_gmem, dst_loc_other and dst_rem select the memory type of the request address: local CMEM, local GMEM, local CXL memory or remote memory; local or remote is determined by the home socket of the address. An unset group counts all.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "EventCode": "0x184",
+        "EventName": "UCF_SLC_ACCESS_ATOMIC",
+        "BriefDescription": "Counts CHI Atomic requests to the SLC.",
+        "PublicDescription": "Counts CHI Atomic requests to the SLC. Filters: src_loc_cpu, src_loc_noncpu and src_rem select the request initiator: local CPU, local non-CPU device or remote socket. dst_loc_cmem, dst_loc_gmem, dst_loc_other and dst_rem select the memory type of the request address: local CMEM, local GMEM, local CXL memory or remote memory; local or remote is determined by the home socket of the address. An unset group counts all.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "EventCode": "0x113",
+        "EventName": "UCF_SLC_BYTES_RD",
+        "BriefDescription": "Counts bytes transferred by the read requests counted by UCF_SLC_ACCESS_RD.",
+        "PublicDescription": "Counts the bytes transferred by the read requests counted by UCF_SLC_ACCESS_RD, including read data sent by Direct Memory Transfer (DMT) or Direct Cache Transfer (DCT). For transfers of an odd number of bytes, the count is rounded to the nearest power of 2 greater than the bytes transferred. Because reads can be smaller than 64 bytes, the count may not equal UCF_SLC_ACCESS_RD times 64. Source and destination filters work as described for UCF_SLC_ACCESS_RD.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "EventCode": "0x114",
+        "EventName": "UCF_SLC_BYTES_WR",
+        "BriefDescription": "Counts bytes transferred by the write requests counted by UCF_SLC_ACCESS_WR.",
+        "PublicDescription": "Counts the bytes transferred by the write requests counted by UCF_SLC_ACCESS_WR, including write data sent by Direct Write Transfer (DWT). For transfers of an odd number of bytes, the count is rounded to the nearest power of 2. Data returned to the SLC by a requester's cache in response to a snoop is not counted. Because writes can be smaller than 64 bytes, the count may not equal UCF_SLC_ACCESS_WR times 64. Source and destination filters work as described for UCF_SLC_ACCESS_WR.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "EventCode": "0x119",
+        "EventName": "UCF_SLC_HIT_RD",
+        "BriefDescription": "Counts inbound read requests that hit in the SLC's L3 cache or in a peer requester cache.",
+        "PublicDescription": "Counts inbound read requests that hit in the SLC's L3 cache or in a peer requester cache, including one in a remote socket. Some hits are still refilled from memory (see UCF_SLC_REFILL_RD). Filters: src_loc_cpu, src_loc_noncpu and src_rem select the request initiator: local CPU, local non-CPU device or remote socket. dst_loc_cmem, dst_loc_gmem, dst_loc_other and dst_rem select the memory type of the request address: local CMEM, local GMEM, local CXL memory or remote memory; local or remote is determined by the home socket of the address. An unset group counts all.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "EventCode": "0x109",
+        "EventName": "UCF_SLC_REFILL_RD",
+        "BriefDescription": "Counts inbound read requests not supplied by the local socket's L1, L2 or L3 caches.",
+        "PublicDescription": "Counts inbound read requests not supplied by the local socket's L1, L2 or L3 caches. For remote-memory addresses, it also counts each Shared-to-Unique permission upgrade (dataless MakeReadUnique) of a cache line shared by requesters in different sockets. A refill is not the same as a miss: the SLC may fetch data from memory even when a requester cache holds clean data, and such accesses are hits that are still refilled. Filters: src_loc_cpu, src_loc_noncpu and src_rem select the request initiator: local CPU, local non-CPU device or remote socket. dst_loc_cmem, dst_loc_gmem, dst_loc_other and dst_rem select the memory type of the request address: local CMEM, local GMEM, local CXL memory or remote memory; local or remote is determined by the home socket of the address. An unset group counts all.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "EventCode": "0x10a",
+        "EventName": "UCF_SLC_REFILL_WR",
+        "BriefDescription": "Counts inbound write requests not supplied by the local socket's L1, L2 or L3 caches.",
+        "PublicDescription": "Counts inbound write requests not supplied by the local socket's L1, L2 or L3 caches. A write refill occurs only for a partial write that needs the existing data; dataless write requests do not cause a refill and are not counted. Filters: src_loc_cpu, src_loc_noncpu and src_rem select the request initiator: local CPU, local non-CPU device or remote socket. dst_loc_cmem, dst_loc_gmem, dst_loc_other and dst_rem select the memory type of the request address: local CMEM, local GMEM, local CXL memory or remote memory; local or remote is determined by the home socket of the address. An unset group counts all.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "EventCode": "0xf0",
+        "EventName": "UCF_SLC_ALLOCATE",
+        "BriefDescription": "Counts read, write, atomic or prefetch accesses that allocate a line in the SLC's L3 cache.",
+        "PublicDescription": "Counts read, write, atomic or prefetch accesses that allocate a line in the SLC's L3 cache. Filters: src_loc_cpu, src_loc_noncpu and src_rem select the request initiator: local CPU, local non-CPU device or remote socket. dst_loc_cmem, dst_loc_gmem, dst_loc_other and dst_rem select the memory type of the request address: local CMEM, local GMEM, local CXL memory or remote memory; local or remote is determined by the home socket of the address. An unset group counts all.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "EventCode": "0xf3",
+        "EventName": "UCF_SLC_WB",
+        "BriefDescription": "Counts SLC eviction and coherence write-backs, and non-allocating write-backs from upstream clients.",
+        "PublicDescription": "Counts SLC write-backs: eviction write-backs, coherence write-backs, and non-allocating write-backs from upstream clients. Evictions include L3 cache and snoop filter evictions. A coherence write-back occurs when data is dirty in the L3 cache or another requester node cache, but a requesting agent needs clean data. A home SLC in another socket, or the GL2 of a connected local or remote GPU (the point of coherence for GPU memory), can evict a line and snoop this SLC. A data-bearing snoop response from this SLC is not counted by this event, though it uses this SLC's downstream bandwidth. For a home SLC eviction, the home SLC's events count the downstream write traffic it causes. Filters: src_loc_cpu, src_loc_noncpu and src_rem select the initiator of the request that caused the write-back: local CPU, local non-CPU device or remote socket. This need not be the agent that produced or modified the data. dst_loc_cmem, dst_loc_gmem, dst_loc_other and dst_rem select the memory type of the memory written back: local CMEM, local GMEM, local CXL memory or remote memory; local or remote is determined by the home socket of the address. An unset group counts all.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "EventCode": "0x180",
+        "EventName": "UCF_LOCAL_SNOOP",
+        "BriefDescription": "Counts snoop requests sent by this SLC to local fully coherent requester nodes or to an SLC in another socket.",
+        "PublicDescription": "Counts snoop requests sent by this SLC to fully coherent requester nodes in the local socket or to an SLC in another socket, including an SLC that this SLC tracks as a sharing node. Invalidating, forwarding, and non-forwarding snoops are included. Each snoop request is counted separately, even when one transaction snoops several clients for the same cache line. Snoops generated for atomic requests or dataless requests are not counted. Filters: src_loc_cpu, src_loc_noncpu and src_rem select the initiator of the request that caused the snoop: local CPU, local non-CPU device or remote socket. dst_loc_cmem, dst_loc_gmem, dst_loc_other and dst_rem select the memory type of the request address: local CMEM, local GMEM, local CXL memory or remote memory; local or remote is determined by the home socket of the address. An unset group counts all.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "EventCode": "0x181",
+        "EventName": "UCF_EXT_SNP_ACCESS",
+        "BriefDescription": "Counts snoop requests that a home SLC or GL2 in another socket sends to this SLC.",
+        "PublicDescription": "Counts snoop requests that a home SLC or GL2 in another socket sends to this SLC. Snoops are counted whether or not the response carries data. Filters: every counted snoop matches src_rem and dst_rem, since it comes from a remote initiator for an address homed in another socket. An unset source or destination group counts all.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "EventCode": "0x182",
+        "EventName": "UCF_EXT_SNP_EVICT",
+        "BriefDescription": "Counts snoop requests from a home SLC or GL2 in another socket that invalidate an L3 cache or snoop filter entry in this SLC.",
+        "PublicDescription": "Counts snoop requests from a home SLC or GL2 in another socket that invalidate an L3 cache entry or snoop filter entry in this SLC. Snoops are counted whether or not the response carries data, so this event cannot give the number or volume of data-bearing snoop responses (see UCF_SLC_WB). Filters: every counted snoop matches src_rem and dst_rem, since it comes from a remote initiator for an address homed in another socket. An unset source or destination group counts all.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "EventCode": "0x121",
+        "EventName": "UCF_MEM_ACCESS_RD",
+        "BriefDescription": "Counts read requests from the SLC toward local CMEM, local GMEM, local CXL memory or remote memory.",
+        "PublicDescription": "Counts read requests from the SLC toward local CMEM, local GMEM, local CXL memory or remote memory. For remote memory it can overcount: it also increments for each Shared-to-Unique permission upgrade (dataless MakeReadUnique) of a cache line shared by requesters in different sockets. To count reads from remote sources without this overcount, count UCF_SLC_ACCESS_RD on the memory's home socket with src_rem, dst_loc_cmem, dst_loc_gmem and dst_loc_other set. Filters: src_loc_cpu, src_loc_noncpu and src_rem select the request initiator: local CPU, local non-CPU device or remote socket. dst_loc_cmem, dst_loc_gmem, dst_loc_other and dst_rem select the memory type of the request address: local CMEM, local GMEM, local CXL memory or remote memory; local or remote is determined by the home socket of the address. An unset group counts all.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "EventCode": "0x122",
+        "EventName": "UCF_MEM_ACCESS_WR",
+        "BriefDescription": "Counts write requests from the SLC toward local CMEM, local GMEM, local CXL memory or remote memory.",
+        "PublicDescription": "Counts write requests from the SLC toward local CMEM, local GMEM, local CXL memory or remote memory. It includes SLC write-backs, which are attributed as described for UCF_SLC_WB. Data-bearing snoop responses to evictions by a home SLC in another socket or a connected GPU's GL2 are not counted (see UCF_SLC_WB). Filters: src_loc_cpu, src_loc_noncpu and src_rem select the request initiator: local CPU, local non-CPU device or remote socket. dst_loc_cmem, dst_loc_gmem, dst_loc_other and dst_rem select the memory type of the request address: local CMEM, local GMEM, local CXL memory or remote memory; local or remote is determined by the home socket of the address. An unset group counts all.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "EventCode": "0x123",
+        "EventName": "UCF_MEM_BYTES_RD",
+        "BriefDescription": "Counts bytes transferred by the read requests counted by UCF_MEM_ACCESS_RD.",
+        "PublicDescription": "Counts bytes transferred by the read requests counted by UCF_MEM_ACCESS_RD. Source and destination filters work as described for UCF_MEM_ACCESS_RD.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "EventCode": "0x124",
+        "EventName": "UCF_MEM_BYTES_WR",
+        "BriefDescription": "Counts bytes transferred by the write requests counted by UCF_MEM_ACCESS_WR.",
+        "PublicDescription": "Counts bytes transferred by the write requests counted by UCF_MEM_ACCESS_WR, including write-back data attributed as described for UCF_SLC_WB. Data-bearing snoop responses to evictions by a home SLC in another socket or a connected GPU's GL2 are not counted (see UCF_SLC_WB). Source and destination filters work as described for UCF_MEM_ACCESS_WR.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_freq",
+        "MetricGroup": "UCF_Frequency",
+        "MetricConstraint": "NO_GROUP_EVENTS",
+        "MetricExpr": "(UCF_CYCLES / aggr_nr(UCF_CYCLES)) / 1e9 / duration_time",
+        "ScaleUnit": "1GHz",
+        "BriefDescription": "UCF clock frequency.",
+        "PublicDescription": "Average UCF clock frequency over the measurement interval.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_rd_bandwidth_all_src_to_all_dst",
+        "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_All_Src_To_All_Dst",
+        "MetricExpr": "UCF_SLC_BYTES_RD@src_loc_cpu=1,src_loc_noncpu=1,src_rem=1,dst_loc_cmem=1,dst_loc_gmem=1,dst_loc_other=1,dst_rem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC read bandwidth for requests from all sources to all destinations.",
+        "PublicDescription": "Average requester-to-SLC read bandwidth of requests from local CPUs, local non-CPU devices and remote sockets for local CMEM, local GMEM, local CXL memory and remote memory addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_rd_bandwidth_all_src_to_all_dst",
+        "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_All_Src_To_All_Dst",
+        "MetricExpr": "UCF_MEM_BYTES_RD@src_loc_cpu=1,src_loc_noncpu=1,src_rem=1,dst_loc_cmem=1,dst_loc_gmem=1,dst_loc_other=1,dst_rem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory read bandwidth for all memory destinations, for requests from all initiators.",
+        "PublicDescription": "Average SLC-to-memory read bandwidth for local CMEM, local GMEM, local CXL memory and remote memory, for requests initiated by local CPUs, local non-CPU devices and remote sockets.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_wr_bandwidth_all_src_to_all_dst",
+        "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_All_Src_To_All_Dst",
+        "MetricExpr": "UCF_SLC_BYTES_WR@src_loc_cpu=1,src_loc_noncpu=1,src_rem=1,dst_loc_cmem=1,dst_loc_gmem=1,dst_loc_other=1,dst_rem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC write bandwidth for requests from all sources to all destinations.",
+        "PublicDescription": "Average requester-to-SLC write bandwidth of requests from local CPUs, local non-CPU devices and remote sockets for local CMEM, local GMEM, local CXL memory and remote memory addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_wr_bandwidth_all_src_to_all_dst",
+        "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_All_Src_To_All_Dst",
+        "MetricExpr": "UCF_MEM_BYTES_WR@src_loc_cpu=1,src_loc_noncpu=1,src_rem=1,dst_loc_cmem=1,dst_loc_gmem=1,dst_loc_other=1,dst_rem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory write bandwidth for local and remote memory, for traffic from all initiators.",
+        "PublicDescription": "Average SLC-to-memory write bandwidth for local CMEM, local GMEM, local CXL memory and remote memory, for traffic initiated by local CPUs, local non-CPU devices and remote sockets. Includes write-backs, attributed as described for UCF_SLC_WB. Data-bearing snoop responses to evictions by a home SLC in another socket or a connected GPU's GL2 are not counted (see UCF_SLC_WB).",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_rd_bandwidth_local_cpu_to_local_cmem",
+        "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Local_CPU;UCF_BW_Local_CMEM;UCF_BW_Local_CPU_To_Local_CMEM",
+        "MetricExpr": "UCF_SLC_BYTES_RD@src_loc_cpu=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC read bandwidth for local CPU requests to local CMEM addresses.",
+        "PublicDescription": "Average requester-to-SLC read bandwidth of requests from local CPUs for local CMEM addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_rd_bandwidth_local_cpu_to_local_cmem",
+        "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Local_CPU;UCF_BW_Local_CMEM;UCF_BW_Local_CPU_To_Local_CMEM",
+        "MetricExpr": "UCF_MEM_BYTES_RD@src_loc_cpu=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory read bandwidth for local CMEM, for requests initiated by local CPUs.",
+        "PublicDescription": "Average SLC-to-memory read bandwidth for local CMEM, for requests initiated by local CPUs.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_wr_bandwidth_local_cpu_to_local_cmem",
+        "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Local_CPU;UCF_BW_Local_CMEM;UCF_BW_Local_CPU_To_Local_CMEM",
+        "MetricExpr": "UCF_SLC_BYTES_WR@src_loc_cpu=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC write bandwidth for local CPU requests to local CMEM addresses.",
+        "PublicDescription": "Average requester-to-SLC write bandwidth of requests from local CPUs for local CMEM addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_wr_bandwidth_local_cpu_to_local_cmem",
+        "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Local_CPU;UCF_BW_Local_CMEM;UCF_BW_Local_CPU_To_Local_CMEM",
+        "MetricExpr": "UCF_MEM_BYTES_WR@src_loc_cpu=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory write bandwidth for local CMEM, for traffic initiated by local CPUs.",
+        "PublicDescription": "Average SLC-to-memory write bandwidth for local CMEM, for traffic initiated by local CPUs. Includes write-backs, attributed as described for UCF_SLC_WB.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_rd_bandwidth_local_cpu_to_local_gmem",
+        "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Local_CPU;UCF_BW_Local_GMEM;UCF_BW_Local_CPU_To_Local_GMEM",
+        "MetricExpr": "UCF_SLC_BYTES_RD@src_loc_cpu=1,dst_loc_gmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC read bandwidth for local CPU requests to local GMEM addresses.",
+        "PublicDescription": "Average requester-to-SLC read bandwidth of requests from local CPUs for local GMEM addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_rd_bandwidth_local_cpu_to_local_gmem",
+        "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Local_CPU;UCF_BW_Local_GMEM;UCF_BW_Local_CPU_To_Local_GMEM",
+        "MetricExpr": "UCF_MEM_BYTES_RD@src_loc_cpu=1,dst_loc_gmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory read bandwidth for local GMEM, for requests initiated by local CPUs.",
+        "PublicDescription": "Average SLC-to-memory read bandwidth for local GMEM, for requests initiated by local CPUs.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_wr_bandwidth_local_cpu_to_local_gmem",
+        "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Local_CPU;UCF_BW_Local_GMEM;UCF_BW_Local_CPU_To_Local_GMEM",
+        "MetricExpr": "UCF_SLC_BYTES_WR@src_loc_cpu=1,dst_loc_gmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC write bandwidth for local CPU requests to local GMEM addresses.",
+        "PublicDescription": "Average requester-to-SLC write bandwidth of requests from local CPUs for local GMEM addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_wr_bandwidth_local_cpu_to_local_gmem",
+        "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Local_CPU;UCF_BW_Local_GMEM;UCF_BW_Local_CPU_To_Local_GMEM",
+        "MetricExpr": "UCF_MEM_BYTES_WR@src_loc_cpu=1,dst_loc_gmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory write bandwidth for local GMEM, for traffic initiated by local CPUs.",
+        "PublicDescription": "Average SLC-to-memory write bandwidth for local GMEM, for traffic initiated by local CPUs. Includes write-backs, attributed as described for UCF_SLC_WB. Data-bearing snoop responses to evictions by a home SLC in another socket or a connected GPU's GL2 are not counted (see UCF_SLC_WB).",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_rd_bandwidth_local_cpu_to_local_cxlmem",
+        "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Local_CPU;UCF_BW_Local_CXLMEM;UCF_BW_Local_CPU_To_Local_CXLMEM",
+        "MetricExpr": "UCF_SLC_BYTES_RD@src_loc_cpu=1,dst_loc_other=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC read bandwidth for local CPU requests to local CXL memory addresses.",
+        "PublicDescription": "Average requester-to-SLC read bandwidth of requests from local CPUs for local CXL memory addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_rd_bandwidth_local_cpu_to_local_cxlmem",
+        "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Local_CPU;UCF_BW_Local_CXLMEM;UCF_BW_Local_CPU_To_Local_CXLMEM",
+        "MetricExpr": "UCF_MEM_BYTES_RD@src_loc_cpu=1,dst_loc_other=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory read bandwidth for local CXL memory, for requests initiated by local CPUs.",
+        "PublicDescription": "Average SLC-to-memory read bandwidth for local CXL memory, for requests initiated by local CPUs.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_wr_bandwidth_local_cpu_to_local_cxlmem",
+        "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Local_CPU;UCF_BW_Local_CXLMEM;UCF_BW_Local_CPU_To_Local_CXLMEM",
+        "MetricExpr": "UCF_SLC_BYTES_WR@src_loc_cpu=1,dst_loc_other=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC write bandwidth for local CPU requests to local CXL memory addresses.",
+        "PublicDescription": "Average requester-to-SLC write bandwidth of requests from local CPUs for local CXL memory addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_wr_bandwidth_local_cpu_to_local_cxlmem",
+        "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Local_CPU;UCF_BW_Local_CXLMEM;UCF_BW_Local_CPU_To_Local_CXLMEM",
+        "MetricExpr": "UCF_MEM_BYTES_WR@src_loc_cpu=1,dst_loc_other=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory write bandwidth for local CXL memory, for traffic initiated by local CPUs.",
+        "PublicDescription": "Average SLC-to-memory write bandwidth for local CXL memory, for traffic initiated by local CPUs. Includes write-backs, attributed as described for UCF_SLC_WB.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_rd_bandwidth_local_cpu_to_remote_mem",
+        "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Local_CPU;UCF_BW_Remote_Memory;UCF_BW_Local_CPU_To_Remote_Memory",
+        "MetricExpr": "UCF_SLC_BYTES_RD@src_loc_cpu=1,dst_rem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC read bandwidth for local CPU requests to remote memory addresses.",
+        "PublicDescription": "Average requester-to-SLC read bandwidth of requests from local CPUs for remote memory addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_rd_bandwidth_local_cpu_to_remote_mem",
+        "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Local_CPU;UCF_BW_Remote_Memory;UCF_BW_Local_CPU_To_Remote_Memory",
+        "MetricExpr": "UCF_MEM_BYTES_RD@src_loc_cpu=1,dst_rem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory read bandwidth for remote memory, for requests initiated by local CPUs.",
+        "PublicDescription": "Average SLC-to-memory read bandwidth for remote memory, for requests initiated by local CPUs.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_wr_bandwidth_local_cpu_to_remote_mem",
+        "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Local_CPU;UCF_BW_Remote_Memory;UCF_BW_Local_CPU_To_Remote_Memory",
+        "MetricExpr": "UCF_SLC_BYTES_WR@src_loc_cpu=1,dst_rem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC write bandwidth for local CPU requests to remote memory addresses.",
+        "PublicDescription": "Average requester-to-SLC write bandwidth of requests from local CPUs for remote memory addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_wr_bandwidth_local_cpu_to_remote_mem",
+        "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Local_CPU;UCF_BW_Remote_Memory;UCF_BW_Local_CPU_To_Remote_Memory",
+        "MetricExpr": "UCF_MEM_BYTES_WR@src_loc_cpu=1,dst_rem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory write bandwidth for remote memory, for traffic initiated by local CPUs.",
+        "PublicDescription": "Average SLC-to-memory write bandwidth for remote memory, for traffic initiated by local CPUs. Includes write-backs, attributed as described for UCF_SLC_WB. Data-bearing snoop responses to evictions by a home SLC in another socket or a connected GPU's GL2 are not counted (see UCF_SLC_WB).",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_rd_bandwidth_local_noncpu_to_local_cmem",
+        "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Local_NonCPU;UCF_BW_Local_CMEM;UCF_BW_Local_NonCPU_To_Local_CMEM",
+        "MetricExpr": "UCF_SLC_BYTES_RD@src_loc_noncpu=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC read bandwidth for local non-CPU requests to local CMEM addresses.",
+        "PublicDescription": "Average requester-to-SLC read bandwidth of requests from local non-CPU devices such as the GPU and PCIe devices for local CMEM addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_rd_bandwidth_local_noncpu_to_local_cmem",
+        "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Local_NonCPU;UCF_BW_Local_CMEM;UCF_BW_Local_NonCPU_To_Local_CMEM",
+        "MetricExpr": "UCF_MEM_BYTES_RD@src_loc_noncpu=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory read bandwidth for local CMEM, for requests initiated by local non-CPU devices.",
+        "PublicDescription": "Average SLC-to-memory read bandwidth for local CMEM, for requests initiated by local non-CPU devices such as the GPU and PCIe devices.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_wr_bandwidth_local_noncpu_to_local_cmem",
+        "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Local_NonCPU;UCF_BW_Local_CMEM;UCF_BW_Local_NonCPU_To_Local_CMEM",
+        "MetricExpr": "UCF_SLC_BYTES_WR@src_loc_noncpu=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC write bandwidth for local non-CPU requests to local CMEM addresses.",
+        "PublicDescription": "Average requester-to-SLC write bandwidth of requests from local non-CPU devices such as the GPU and PCIe devices for local CMEM addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_wr_bandwidth_local_noncpu_to_local_cmem",
+        "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Local_NonCPU;UCF_BW_Local_CMEM;UCF_BW_Local_NonCPU_To_Local_CMEM",
+        "MetricExpr": "UCF_MEM_BYTES_WR@src_loc_noncpu=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory write bandwidth for local CMEM, for traffic initiated by local non-CPU devices.",
+        "PublicDescription": "Average SLC-to-memory write bandwidth for local CMEM, for traffic initiated by local non-CPU devices such as the GPU and PCIe devices. Includes write-backs, attributed as described for UCF_SLC_WB.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_rd_bandwidth_local_noncpu_to_local_gmem",
+        "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Local_NonCPU;UCF_BW_Local_GMEM;UCF_BW_Local_NonCPU_To_Local_GMEM",
+        "MetricExpr": "UCF_SLC_BYTES_RD@src_loc_noncpu=1,dst_loc_gmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC read bandwidth for local non-CPU requests to local GMEM addresses.",
+        "PublicDescription": "Average requester-to-SLC read bandwidth of requests from local non-CPU devices such as the GPU and PCIe devices for local GMEM addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_rd_bandwidth_local_noncpu_to_local_gmem",
+        "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Local_NonCPU;UCF_BW_Local_GMEM;UCF_BW_Local_NonCPU_To_Local_GMEM",
+        "MetricExpr": "UCF_MEM_BYTES_RD@src_loc_noncpu=1,dst_loc_gmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory read bandwidth for local GMEM, for requests initiated by local non-CPU devices.",
+        "PublicDescription": "Average SLC-to-memory read bandwidth for local GMEM, for requests initiated by local non-CPU devices such as the GPU and PCIe devices.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_wr_bandwidth_local_noncpu_to_local_gmem",
+        "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Local_NonCPU;UCF_BW_Local_GMEM;UCF_BW_Local_NonCPU_To_Local_GMEM",
+        "MetricExpr": "UCF_SLC_BYTES_WR@src_loc_noncpu=1,dst_loc_gmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC write bandwidth for local non-CPU requests to local GMEM addresses.",
+        "PublicDescription": "Average requester-to-SLC write bandwidth of requests from local non-CPU devices such as the GPU and PCIe devices for local GMEM addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_wr_bandwidth_local_noncpu_to_local_gmem",
+        "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Local_NonCPU;UCF_BW_Local_GMEM;UCF_BW_Local_NonCPU_To_Local_GMEM",
+        "MetricExpr": "UCF_MEM_BYTES_WR@src_loc_noncpu=1,dst_loc_gmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory write bandwidth for local GMEM, for traffic initiated by local non-CPU devices.",
+        "PublicDescription": "Average SLC-to-memory write bandwidth for local GMEM, for traffic initiated by local non-CPU devices such as the GPU and PCIe devices. Includes write-backs, attributed as described for UCF_SLC_WB. Data-bearing snoop responses to evictions by a home SLC in another socket or a connected GPU's GL2 are not counted (see UCF_SLC_WB).",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_rd_bandwidth_local_noncpu_to_local_cxlmem",
+        "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Local_NonCPU;UCF_BW_Local_CXLMEM;UCF_BW_Local_NonCPU_To_Local_CXLMEM",
+        "MetricExpr": "UCF_SLC_BYTES_RD@src_loc_noncpu=1,dst_loc_other=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC read bandwidth for local non-CPU requests to local CXL memory addresses.",
+        "PublicDescription": "Average requester-to-SLC read bandwidth of requests from local non-CPU devices such as the GPU and PCIe devices for local CXL memory addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_rd_bandwidth_local_noncpu_to_local_cxlmem",
+        "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Local_NonCPU;UCF_BW_Local_CXLMEM;UCF_BW_Local_NonCPU_To_Local_CXLMEM",
+        "MetricExpr": "UCF_MEM_BYTES_RD@src_loc_noncpu=1,dst_loc_other=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory read bandwidth for local CXL memory, for requests initiated by local non-CPU devices.",
+        "PublicDescription": "Average SLC-to-memory read bandwidth for local CXL memory, for requests initiated by local non-CPU devices such as the GPU and PCIe devices.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_wr_bandwidth_local_noncpu_to_local_cxlmem",
+        "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Local_NonCPU;UCF_BW_Local_CXLMEM;UCF_BW_Local_NonCPU_To_Local_CXLMEM",
+        "MetricExpr": "UCF_SLC_BYTES_WR@src_loc_noncpu=1,dst_loc_other=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC write bandwidth for local non-CPU requests to local CXL memory addresses.",
+        "PublicDescription": "Average requester-to-SLC write bandwidth of requests from local non-CPU devices such as the GPU and PCIe devices for local CXL memory addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_wr_bandwidth_local_noncpu_to_local_cxlmem",
+        "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Local_NonCPU;UCF_BW_Local_CXLMEM;UCF_BW_Local_NonCPU_To_Local_CXLMEM",
+        "MetricExpr": "UCF_MEM_BYTES_WR@src_loc_noncpu=1,dst_loc_other=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory write bandwidth for local CXL memory, for traffic initiated by local non-CPU devices.",
+        "PublicDescription": "Average SLC-to-memory write bandwidth for local CXL memory, for traffic initiated by local non-CPU devices such as the GPU and PCIe devices. Includes write-backs, attributed as described for UCF_SLC_WB.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_rd_bandwidth_local_noncpu_to_remote_mem",
+        "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Local_NonCPU;UCF_BW_Remote_Memory;UCF_BW_Local_NonCPU_To_Remote_Memory",
+        "MetricExpr": "UCF_SLC_BYTES_RD@src_loc_noncpu=1,dst_rem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC read bandwidth for local non-CPU requests to remote memory addresses.",
+        "PublicDescription": "Average requester-to-SLC read bandwidth of requests from local non-CPU devices such as the GPU and PCIe devices for remote memory addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_rd_bandwidth_local_noncpu_to_remote_mem",
+        "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Local_NonCPU;UCF_BW_Remote_Memory;UCF_BW_Local_NonCPU_To_Remote_Memory",
+        "MetricExpr": "UCF_MEM_BYTES_RD@src_loc_noncpu=1,dst_rem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory read bandwidth for remote memory, for requests initiated by local non-CPU devices.",
+        "PublicDescription": "Average SLC-to-memory read bandwidth for remote memory, for requests initiated by local non-CPU devices such as the GPU and PCIe devices.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_wr_bandwidth_local_noncpu_to_remote_mem",
+        "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Local_NonCPU;UCF_BW_Remote_Memory;UCF_BW_Local_NonCPU_To_Remote_Memory",
+        "MetricExpr": "UCF_SLC_BYTES_WR@src_loc_noncpu=1,dst_rem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC write bandwidth for local non-CPU requests to remote memory addresses.",
+        "PublicDescription": "Average requester-to-SLC write bandwidth of requests from local non-CPU devices such as the GPU and PCIe devices for remote memory addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_wr_bandwidth_local_noncpu_to_remote_mem",
+        "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Local_NonCPU;UCF_BW_Remote_Memory;UCF_BW_Local_NonCPU_To_Remote_Memory",
+        "MetricExpr": "UCF_MEM_BYTES_WR@src_loc_noncpu=1,dst_rem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory write bandwidth for remote memory, for traffic initiated by local non-CPU devices.",
+        "PublicDescription": "Average SLC-to-memory write bandwidth for remote memory, for traffic initiated by local non-CPU devices such as the GPU and PCIe devices. Includes write-backs, attributed as described for UCF_SLC_WB. Data-bearing snoop responses to evictions by a home SLC in another socket or a connected GPU's GL2 are not counted (see UCF_SLC_WB).",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_rd_bandwidth_remote_to_local_cmem",
+        "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Remote_Source;UCF_BW_Local_CMEM;UCF_BW_Remote_To_Local_CMEM",
+        "MetricExpr": "UCF_SLC_BYTES_RD@src_rem=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC read bandwidth for remote-socket requests to local CMEM addresses.",
+        "PublicDescription": "Average requester-to-SLC read bandwidth of requests from a remote socket for local CMEM addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_rd_bandwidth_remote_to_local_cmem",
+        "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Remote_Source;UCF_BW_Local_CMEM;UCF_BW_Remote_To_Local_CMEM",
+        "MetricExpr": "UCF_MEM_BYTES_RD@src_rem=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory read bandwidth for local CMEM, for requests initiated by a remote socket.",
+        "PublicDescription": "Average SLC-to-memory read bandwidth for local CMEM, for requests initiated by a remote socket.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_wr_bandwidth_remote_to_local_cmem",
+        "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Remote_Source;UCF_BW_Local_CMEM;UCF_BW_Remote_To_Local_CMEM",
+        "MetricExpr": "UCF_SLC_BYTES_WR@src_rem=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC write bandwidth for remote-socket requests to local CMEM addresses.",
+        "PublicDescription": "Average requester-to-SLC write bandwidth of requests from a remote socket for local CMEM addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_wr_bandwidth_remote_to_local_cmem",
+        "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Remote_Source;UCF_BW_Local_CMEM;UCF_BW_Remote_To_Local_CMEM",
+        "MetricExpr": "UCF_MEM_BYTES_WR@src_rem=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory write bandwidth for local CMEM, for traffic initiated by a remote socket.",
+        "PublicDescription": "Average SLC-to-memory write bandwidth for local CMEM, for traffic initiated by a remote socket. Includes write-backs, attributed as described for UCF_SLC_WB.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_rd_bandwidth_remote_to_local_gmem",
+        "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Remote_Source;UCF_BW_Local_GMEM;UCF_BW_Remote_To_Local_GMEM",
+        "MetricExpr": "UCF_SLC_BYTES_RD@src_rem=1,dst_loc_gmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC read bandwidth for remote-socket requests to local GMEM addresses.",
+        "PublicDescription": "Average requester-to-SLC read bandwidth of requests from a remote socket for local GMEM addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_rd_bandwidth_remote_to_local_gmem",
+        "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Remote_Source;UCF_BW_Local_GMEM;UCF_BW_Remote_To_Local_GMEM",
+        "MetricExpr": "UCF_MEM_BYTES_RD@src_rem=1,dst_loc_gmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory read bandwidth for local GMEM, for requests initiated by a remote socket.",
+        "PublicDescription": "Average SLC-to-memory read bandwidth for local GMEM, for requests initiated by a remote socket.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_wr_bandwidth_remote_to_local_gmem",
+        "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Remote_Source;UCF_BW_Local_GMEM;UCF_BW_Remote_To_Local_GMEM",
+        "MetricExpr": "UCF_SLC_BYTES_WR@src_rem=1,dst_loc_gmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC write bandwidth for remote-socket requests to local GMEM addresses.",
+        "PublicDescription": "Average requester-to-SLC write bandwidth of requests from a remote socket for local GMEM addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_wr_bandwidth_remote_to_local_gmem",
+        "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Remote_Source;UCF_BW_Local_GMEM;UCF_BW_Remote_To_Local_GMEM",
+        "MetricExpr": "UCF_MEM_BYTES_WR@src_rem=1,dst_loc_gmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory write bandwidth for local GMEM, for traffic initiated by a remote socket.",
+        "PublicDescription": "Average SLC-to-memory write bandwidth for local GMEM, for traffic initiated by a remote socket. Includes write-backs, attributed as described for UCF_SLC_WB. Data-bearing snoop responses to evictions by a home SLC in another socket or a connected GPU's GL2 are not counted (see UCF_SLC_WB).",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_rd_bandwidth_remote_to_local_cxlmem",
+        "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Remote_Source;UCF_BW_Local_CXLMEM;UCF_BW_Remote_To_Local_CXLMEM",
+        "MetricExpr": "UCF_SLC_BYTES_RD@src_rem=1,dst_loc_other=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC read bandwidth for remote-socket requests to local CXL memory addresses.",
+        "PublicDescription": "Average requester-to-SLC read bandwidth of requests from a remote socket for local CXL memory addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_rd_bandwidth_remote_to_local_cxlmem",
+        "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Remote_Source;UCF_BW_Local_CXLMEM;UCF_BW_Remote_To_Local_CXLMEM",
+        "MetricExpr": "UCF_MEM_BYTES_RD@src_rem=1,dst_loc_other=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory read bandwidth for local CXL memory, for requests initiated by a remote socket.",
+        "PublicDescription": "Average SLC-to-memory read bandwidth for local CXL memory, for requests initiated by a remote socket.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_wr_bandwidth_remote_to_local_cxlmem",
+        "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Remote_Source;UCF_BW_Local_CXLMEM;UCF_BW_Remote_To_Local_CXLMEM",
+        "MetricExpr": "UCF_SLC_BYTES_WR@src_rem=1,dst_loc_other=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC write bandwidth for remote-socket requests to local CXL memory addresses.",
+        "PublicDescription": "Average requester-to-SLC write bandwidth of requests from a remote socket for local CXL memory addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_wr_bandwidth_remote_to_local_cxlmem",
+        "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Remote_Source;UCF_BW_Local_CXLMEM;UCF_BW_Remote_To_Local_CXLMEM",
+        "MetricExpr": "UCF_MEM_BYTES_WR@src_rem=1,dst_loc_other=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory write bandwidth for local CXL memory, for traffic initiated by a remote socket.",
+        "PublicDescription": "Average SLC-to-memory write bandwidth for local CXL memory, for traffic initiated by a remote socket. Includes write-backs, attributed as described for UCF_SLC_WB.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_rd_bandwidth_remote_to_remote_mem",
+        "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Remote_Source;UCF_BW_Remote_Memory;UCF_BW_Remote_To_Remote_Memory",
+        "MetricExpr": "UCF_SLC_BYTES_RD@src_rem=1,dst_rem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC read bandwidth for remote-socket requests to remote memory addresses.",
+        "PublicDescription": "Average requester-to-SLC read bandwidth of requests from a remote socket for remote memory addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_rd_bandwidth_remote_to_remote_mem",
+        "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Remote_Source;UCF_BW_Remote_Memory;UCF_BW_Remote_To_Remote_Memory",
+        "MetricExpr": "UCF_MEM_BYTES_RD@src_rem=1,dst_rem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory read bandwidth for remote memory, for requests initiated by a remote socket.",
+        "PublicDescription": "Average SLC-to-memory read bandwidth for remote memory, for requests initiated by a remote socket.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_slc_wr_bandwidth_remote_to_remote_mem",
+        "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Remote_Source;UCF_BW_Remote_Memory;UCF_BW_Remote_To_Remote_Memory",
+        "MetricExpr": "UCF_SLC_BYTES_WR@src_rem=1,dst_rem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average requester-to-SLC write bandwidth for remote-socket requests to remote memory addresses.",
+        "PublicDescription": "Average requester-to-SLC write bandwidth of requests from a remote socket for remote memory addresses.",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    },
+    {
+        "MetricName": "ucf_avg_mem_wr_bandwidth_remote_to_remote_mem",
+        "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Remote_Source;UCF_BW_Remote_Memory;UCF_BW_Remote_To_Remote_Memory",
+        "MetricExpr": "UCF_MEM_BYTES_WR@src_rem=1,dst_rem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average SLC-to-memory write bandwidth for remote memory, for traffic initiated by a remote socket.",
+        "PublicDescription": "Average SLC-to-memory write bandwidth for remote memory, for traffic initiated by a remote socket. Includes write-backs, attributed as described for UCF_SLC_WB. Data-bearing snoop responses to evictions by a home SLC in another socket or a connected GPU's GL2 are not counted (see UCF_SLC_WB).",
+        "Compat": "2cf2036b",
+        "Unit": "nvidia_ucf_pmu_"
+    }
+]
-- 
2.43.0

[PATCH 3/6] perf jevents: Add support for NVIDIA Tegra410 PCIE PMU aliasing

[Besar Wicaksono]

Add alias support for NVIDIA Tegra410 PCIE PMU events and metrics.

Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
---
 .../arm64/nvidia/t410/sys/uncore-pcie.json    | 247 ++++++++++++++++++
 1 file changed, 247 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie.json

diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie.json b/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie.json
new file mode 100644
index 000000000000..37c3eac305e5
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie.json
@@ -0,0 +1,247 @@
+[
+    {
+        "EventCode": "0x100000000",
+        "EventName": "PCIE_CYCLES",
+        "BriefDescription": "Counts cycles at the PCIe interface to the Tegra SoC data fabric.",
+        "PublicDescription": "Counts cycles at the PCIe interface to the Tegra SoC data fabric.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    },
+    {
+        "EventCode": "0x2",
+        "EventName": "PCIE_RD_REQ",
+        "BriefDescription": "Counts read requests from PCIe devices under this PCIe root complex to memory or another PCIe device.",
+        "PublicDescription": "Counts read requests from PCIe devices under this PCIe root complex to memory or another PCIe device, where the target responds with data. Request size can be from 1 to 256 bytes. Filters: src_rp_mask selects the requesting root ports. Alternatively, src_bdf with src_bdf_en selects one requesting device (BDF); it cannot be combined with src_rp_mask and applies to all counters of this PMU. Destination filters select the memory type of the request address: dst_loc_cmem local CMEM, dst_loc_gmem local GMEM, dst_loc_pcie_p2p local PCIe peer addresses, dst_loc_pcie_cxl local CXL memory, dst_rem remote memory. This is the address's home type, not where the data currently resides; local or remote is determined by the home socket of the address. An unset source filter counts all root ports; an unset destination filter counts all destinations.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    },
+    {
+        "EventCode": "0x3",
+        "EventName": "PCIE_WR_REQ",
+        "BriefDescription": "Counts write requests from PCIe devices under this PCIe root complex to memory or another PCIe device.",
+        "PublicDescription": "Counts write requests from PCIe devices under this PCIe root complex to memory or another PCIe device, where the PCIe device sends data. Request size can be from 1 to 256 bytes. Filters: src_rp_mask selects the requesting root ports. Alternatively, src_bdf with src_bdf_en selects one requesting device (BDF); it cannot be combined with src_rp_mask and applies to all counters of this PMU. Destination filters select the memory type of the request address: dst_loc_cmem local CMEM, dst_loc_gmem local GMEM, dst_loc_pcie_p2p local PCIe peer addresses, dst_loc_pcie_cxl local CXL memory, dst_rem remote memory. This is the address's home type, not where the data currently resides; local or remote is determined by the home socket of the address. An unset source filter counts all root ports; an unset destination filter counts all destinations.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    },
+    {
+        "EventCode": "0x0",
+        "EventName": "PCIE_RD_BYTES",
+        "BriefDescription": "Counts bytes transferred by the read requests counted by PCIE_RD_REQ.",
+        "PublicDescription": "Counts bytes transferred by the read requests counted by PCIE_RD_REQ. Source and destination filters work as described for PCIE_RD_REQ.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    },
+    {
+        "EventCode": "0x1",
+        "EventName": "PCIE_WR_BYTES",
+        "BriefDescription": "Counts bytes transferred by the write requests counted by PCIE_WR_REQ.",
+        "PublicDescription": "Counts bytes transferred by the write requests counted by PCIE_WR_REQ. Source and destination filters work as described for PCIE_WR_REQ.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    },
+    {
+        "EventCode": "0x4",
+        "EventName": "PCIE_RD_CUM_OUTS",
+        "BriefDescription": "Accumulates the outstanding read requests counted by PCIE_RD_REQ each cycle at the PCIe interface.",
+        "PublicDescription": "Accumulates the outstanding read requests counted by PCIE_RD_REQ each cycle at the PCIe interface. Pair the two under the same filters for the average read latency. Source and destination filters work as described for PCIE_RD_REQ.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    },
+    {
+        "MetricName": "pcie_freq",
+        "MetricGroup": "PCIE_Frequency;PCIE_Read_Latency",
+        "MetricConstraint": "NO_GROUP_EVENTS",
+        "MetricExpr": "(PCIE_CYCLES / aggr_nr(PCIE_CYCLES)) / 1e9 / duration_time",
+        "ScaleUnit": "1GHz",
+        "BriefDescription": "Frequency of the cycles at the PCIe interface to the Tegra SoC data fabric.",
+        "PublicDescription": "Average frequency of the cycles at the PCIe interface to the Tegra SoC data fabric over the measurement interval.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    },
+    {
+        "MetricName": "pcie_avg_rd_bandwidth_to_all_dst",
+        "MetricGroup": "PCIE_Bandwidth;PCIE_To_All_Destinations",
+        "MetricExpr": "PCIE_RD_BYTES@dst_loc_cmem=1,dst_loc_gmem=1,dst_loc_pcie_p2p=1,dst_loc_pcie_cxl=1,dst_rem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average read bandwidth from PCIe devices under this PCIe root complex to all destinations.",
+        "PublicDescription": "Average read bandwidth of requests from all PCIe devices under this PCIe root complex to all destinations: local CMEM, local GMEM, local PCIe peer addresses, local CXL memory and remote memory.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    },
+    {
+        "MetricName": "pcie_avg_wr_bandwidth_to_all_dst",
+        "MetricGroup": "PCIE_Bandwidth;PCIE_To_All_Destinations",
+        "MetricExpr": "PCIE_WR_BYTES@dst_loc_cmem=1,dst_loc_gmem=1,dst_loc_pcie_p2p=1,dst_loc_pcie_cxl=1,dst_rem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average write bandwidth from PCIe devices under this PCIe root complex to all destinations.",
+        "PublicDescription": "Average write bandwidth of requests from all PCIe devices under this PCIe root complex to all destinations: local CMEM, local GMEM, local PCIe peer addresses, local CXL memory and remote memory.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    },
+    {
+        "MetricName": "pcie_avg_rd_latency_to_all_dst",
+        "MetricGroup": "PCIE_Read_Latency;PCIE_To_All_Destinations",
+        "MetricConstraint": "NO_GROUP_EVENTS",
+        "MetricExpr": "(PCIE_RD_CUM_OUTS@dst_loc_cmem=1,dst_loc_gmem=1,dst_loc_pcie_p2p=1,dst_loc_pcie_cxl=1,dst_rem=1@ / PCIE_RD_REQ@dst_loc_cmem=1,dst_loc_gmem=1,dst_loc_pcie_p2p=1,dst_loc_pcie_cxl=1,dst_rem=1@) / pcie_freq",
+        "ScaleUnit": "1ns/request",
+        "BriefDescription": "Average read latency from PCIe devices under this PCIe root complex to all destinations.",
+        "PublicDescription": "Average latency of read requests from all PCIe devices under this PCIe root complex to all destinations: local CMEM, local GMEM, local PCIe peer addresses, local CXL memory and remote memory.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    },
+    {
+        "MetricName": "pcie_avg_rd_bandwidth_to_local_cmem",
+        "MetricGroup": "PCIE_Bandwidth;PCIE_Read;PCIE_To_Local_CMEM",
+        "MetricExpr": "PCIE_RD_BYTES@dst_loc_cmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average read bandwidth from PCIe devices under this PCIe root complex to local CMEM.",
+        "PublicDescription": "Average read bandwidth of requests from all PCIe devices under this PCIe root complex to local CMEM.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    },
+    {
+        "MetricName": "pcie_avg_wr_bandwidth_to_local_cmem",
+        "MetricGroup": "PCIE_Bandwidth;PCIE_Write;PCIE_To_Local_CMEM",
+        "MetricExpr": "PCIE_WR_BYTES@dst_loc_cmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average write bandwidth from PCIe devices under this PCIe root complex to local CMEM.",
+        "PublicDescription": "Average write bandwidth of requests from all PCIe devices under this PCIe root complex to local CMEM.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    },
+    {
+        "MetricName": "pcie_avg_rd_latency_to_local_cmem",
+        "MetricGroup": "PCIE_Read_Latency;PCIE_Read;PCIE_To_Local_CMEM",
+        "MetricConstraint": "NO_GROUP_EVENTS",
+        "MetricExpr": "(PCIE_RD_CUM_OUTS@dst_loc_cmem=1@ / PCIE_RD_REQ@dst_loc_cmem=1@) / pcie_freq",
+        "ScaleUnit": "1ns/request",
+        "BriefDescription": "Average read latency from PCIe devices under this PCIe root complex to local CMEM.",
+        "PublicDescription": "Average latency of read requests from all PCIe devices under this PCIe root complex to local CMEM.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    },
+    {
+        "MetricName": "pcie_avg_rd_bandwidth_to_local_gmem",
+        "MetricGroup": "PCIE_Bandwidth;PCIE_Read;PCIE_To_Local_GMEM",
+        "MetricExpr": "PCIE_RD_BYTES@dst_loc_gmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average read bandwidth from PCIe devices under this PCIe root complex to local GMEM.",
+        "PublicDescription": "Average read bandwidth of requests from all PCIe devices under this PCIe root complex to local GMEM.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    },
+    {
+        "MetricName": "pcie_avg_wr_bandwidth_to_local_gmem",
+        "MetricGroup": "PCIE_Bandwidth;PCIE_Write;PCIE_To_Local_GMEM",
+        "MetricExpr": "PCIE_WR_BYTES@dst_loc_gmem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average write bandwidth from PCIe devices under this PCIe root complex to local GMEM.",
+        "PublicDescription": "Average write bandwidth of requests from all PCIe devices under this PCIe root complex to local GMEM.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    },
+    {
+        "MetricName": "pcie_avg_rd_latency_to_local_gmem",
+        "MetricGroup": "PCIE_Read_Latency;PCIE_Read;PCIE_To_Local_GMEM",
+        "MetricConstraint": "NO_GROUP_EVENTS",
+        "MetricExpr": "(PCIE_RD_CUM_OUTS@dst_loc_gmem=1@ / PCIE_RD_REQ@dst_loc_gmem=1@) / pcie_freq",
+        "ScaleUnit": "1ns/request",
+        "BriefDescription": "Average read latency from PCIe devices under this PCIe root complex to local GMEM.",
+        "PublicDescription": "Average latency of read requests from all PCIe devices under this PCIe root complex to local GMEM.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    },
+    {
+        "MetricName": "pcie_avg_rd_bandwidth_to_local_cxlmem",
+        "MetricGroup": "PCIE_Bandwidth;PCIE_Read;PCIE_To_Local_CXLMEM",
+        "MetricExpr": "PCIE_RD_BYTES@dst_loc_pcie_cxl=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average read bandwidth from PCIe devices under this PCIe root complex to local CXL memory.",
+        "PublicDescription": "Average read bandwidth of requests from all PCIe devices under this PCIe root complex to local CXL memory.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    },
+    {
+        "MetricName": "pcie_avg_wr_bandwidth_to_local_cxlmem",
+        "MetricGroup": "PCIE_Bandwidth;PCIE_Write;PCIE_To_Local_CXLMEM",
+        "MetricExpr": "PCIE_WR_BYTES@dst_loc_pcie_cxl=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average write bandwidth from PCIe devices under this PCIe root complex to local CXL memory.",
+        "PublicDescription": "Average write bandwidth of requests from all PCIe devices under this PCIe root complex to local CXL memory.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    },
+    {
+        "MetricName": "pcie_avg_rd_latency_to_local_cxlmem",
+        "MetricGroup": "PCIE_Read_Latency;PCIE_Read;PCIE_To_Local_CXLMEM",
+        "MetricConstraint": "NO_GROUP_EVENTS",
+        "MetricExpr": "(PCIE_RD_CUM_OUTS@dst_loc_pcie_cxl=1@ / PCIE_RD_REQ@dst_loc_pcie_cxl=1@) / pcie_freq",
+        "ScaleUnit": "1ns/request",
+        "BriefDescription": "Average read latency from PCIe devices under this PCIe root complex to local CXL memory.",
+        "PublicDescription": "Average latency of read requests from all PCIe devices under this PCIe root complex to local CXL memory.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    },
+    {
+        "MetricName": "pcie_avg_rd_bandwidth_to_remote_mem",
+        "MetricGroup": "PCIE_Bandwidth;PCIE_Read;PCIE_To_Remote_Memory",
+        "MetricExpr": "PCIE_RD_BYTES@dst_rem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average read bandwidth from PCIe devices under this PCIe root complex to remote memory.",
+        "PublicDescription": "Average read bandwidth of requests from all PCIe devices under this PCIe root complex to remote memory.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    },
+    {
+        "MetricName": "pcie_avg_wr_bandwidth_to_remote_mem",
+        "MetricGroup": "PCIE_Bandwidth;PCIE_Write;PCIE_To_Remote_Memory",
+        "MetricExpr": "PCIE_WR_BYTES@dst_rem=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average write bandwidth from PCIe devices under this PCIe root complex to remote memory.",
+        "PublicDescription": "Average write bandwidth of requests from all PCIe devices under this PCIe root complex to remote memory.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    },
+    {
+        "MetricName": "pcie_avg_rd_latency_to_remote_mem",
+        "MetricGroup": "PCIE_Read_Latency;PCIE_Read;PCIE_To_Remote_Memory",
+        "MetricConstraint": "NO_GROUP_EVENTS",
+        "MetricExpr": "(PCIE_RD_CUM_OUTS@dst_rem=1@ / PCIE_RD_REQ@dst_rem=1@) / pcie_freq",
+        "ScaleUnit": "1ns/request",
+        "BriefDescription": "Average read latency from PCIe devices under this PCIe root complex to remote memory.",
+        "PublicDescription": "Average latency of read requests from all PCIe devices under this PCIe root complex to remote memory.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    },
+    {
+        "MetricName": "pcie_avg_rd_bandwidth_to_local_pcie_peer",
+        "MetricGroup": "PCIE_Bandwidth;PCIE_Read;PCIE_To_Local_PCIE_Peer",
+        "MetricExpr": "PCIE_RD_BYTES@dst_loc_pcie_p2p=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average read bandwidth from PCIe devices under this PCIe root complex to local PCIe peer addresses.",
+        "PublicDescription": "Average read bandwidth of requests from all PCIe devices under this PCIe root complex to local PCIe peer addresses.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    },
+    {
+        "MetricName": "pcie_avg_wr_bandwidth_to_local_pcie_peer",
+        "MetricGroup": "PCIE_Bandwidth;PCIE_Write;PCIE_To_Local_PCIE_Peer",
+        "MetricExpr": "PCIE_WR_BYTES@dst_loc_pcie_p2p=1@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average write bandwidth from PCIe devices under this PCIe root complex to local PCIe peer addresses.",
+        "PublicDescription": "Average write bandwidth of requests from all PCIe devices under this PCIe root complex to local PCIe peer addresses.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    },
+    {
+        "MetricName": "pcie_avg_rd_latency_to_local_pcie_peer",
+        "MetricGroup": "PCIE_Read_Latency;PCIE_Read;PCIE_To_Local_PCIE_Peer",
+        "MetricConstraint": "NO_GROUP_EVENTS",
+        "MetricExpr": "(PCIE_RD_CUM_OUTS@dst_loc_pcie_p2p=1@ / PCIE_RD_REQ@dst_loc_pcie_p2p=1@) / pcie_freq",
+        "ScaleUnit": "1ns/request",
+        "BriefDescription": "Average read latency from PCIe devices under this PCIe root complex to local PCIe peer addresses.",
+        "PublicDescription": "Average latency of read requests from all PCIe devices under this PCIe root complex to local PCIe peer addresses.",
+        "Compat": "1030136b",
+        "Unit": "nvidia_pcie_pmu_,rc_"
+    }
+]
-- 
2.43.0

[PATCH 4/6] perf jevents: Add support for NVIDIA Tegra410 PCIE-TGT PMU aliasing

[Besar Wicaksono]

Add alias support for NVIDIA Tegra410 PCIE-TGT PMU events and metrics.

Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
---
 .../nvidia/t410/sys/uncore-pcie_tgt.json      | 93 +++++++++++++++++++
 1 file changed, 93 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie_tgt.json

diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie_tgt.json b/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie_tgt.json
new file mode 100644
index 000000000000..74786fc3d578
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie_tgt.json
@@ -0,0 +1,93 @@
+[
+    {
+        "EventCode": "0x4",
+        "EventName": "PCIE_TGT_CYCLES",
+        "BriefDescription": "Counts cycles at the PCIe interface to the Tegra SoC data fabric.",
+        "PublicDescription": "Counts cycles at the PCIe interface to the Tegra SoC data fabric.",
+        "Compat": "1070036b",
+        "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+    },
+    {
+        "EventCode": "0x2",
+        "EventName": "PCIE_TGT_RD_REQ",
+        "BriefDescription": "Counts read requests from any source to PCIe BAR or CXL HDM ranges under this PCIe root complex.",
+        "PublicDescription": "Counts read requests from any source to PCIe BAR or CXL HDM ranges under this PCIe root complex, where the target responds with data. Request size can be from 1 to 256 bytes. Filters: dst_rp_mask selects PCIe BAR traffic to root ports (bit n = root port n). dst_addr_en with dst_addr_base and dst_addr_mask selects PCIe BAR or CXL HDM addresses that equal the base in the mask's set bits. If both dst_rp_mask and the address filter are set, a request matching either is counted. With no filter, PCIe BAR traffic to all root ports is counted.",
+        "Compat": "1070036b",
+        "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+    },
+    {
+        "EventCode": "0x3",
+        "EventName": "PCIE_TGT_WR_REQ",
+        "BriefDescription": "Counts write requests from any source to PCIe BAR or CXL HDM ranges under this PCIe root complex.",
+        "PublicDescription": "Counts write requests from any source to PCIe BAR or CXL HDM ranges under this PCIe root complex, where the source sends data. Request size can be from 1 to 256 bytes. Filters: dst_rp_mask selects PCIe BAR traffic to root ports (bit n = root port n). dst_addr_en with dst_addr_base and dst_addr_mask selects PCIe BAR or CXL HDM addresses that equal the base in the mask's set bits. If both dst_rp_mask and the address filter are set, a request matching either is counted. With no filter, PCIe BAR traffic to all root ports is counted.",
+        "Compat": "1070036b",
+        "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+    },
+    {
+        "EventCode": "0x0",
+        "EventName": "PCIE_TGT_RD_BYTES",
+        "BriefDescription": "Counts bytes transferred by the read requests counted by PCIE_TGT_RD_REQ.",
+        "PublicDescription": "Counts bytes transferred by the read requests counted by PCIE_TGT_RD_REQ. Destination filters work as described for PCIE_TGT_RD_REQ.",
+        "Compat": "1070036b",
+        "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+    },
+    {
+        "EventCode": "0x1",
+        "EventName": "PCIE_TGT_WR_BYTES",
+        "BriefDescription": "Counts bytes transferred by the write requests counted by PCIE_TGT_WR_REQ.",
+        "PublicDescription": "Counts bytes transferred by the write requests counted by PCIE_TGT_WR_REQ. Destination filters work as described for PCIE_TGT_WR_REQ.",
+        "Compat": "1070036b",
+        "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+    },
+    {
+        "MetricName": "pcie_tgt_freq",
+        "MetricGroup": "PCIE_TGT_Frequency",
+        "MetricConstraint": "NO_GROUP_EVENTS",
+        "MetricExpr": "(PCIE_TGT_CYCLES / aggr_nr(PCIE_TGT_CYCLES)) / 1e9 / duration_time",
+        "ScaleUnit": "1GHz",
+        "BriefDescription": "Frequency of the cycles at the PCIe interface to the Tegra SoC data fabric.",
+        "PublicDescription": "Average frequency of the cycles at the PCIe interface to the Tegra SoC data fabric over the measurement interval.",
+        "Compat": "1070036b",
+        "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+    },
+    {
+        "MetricName": "pcie_tgt_avg_rd_bandwidth_to_all_dst",
+        "MetricGroup": "PCIE_TGT_Bandwidth;PCIE_TGT_BW_PCIE_BAR_CXL_HDM",
+        "MetricExpr": "PCIE_TGT_RD_BYTES@dst_addr_en=1,dst_addr_base=0,dst_addr_mask=0@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average read bandwidth to all PCIe BAR and CXL HDM ranges under this PCIe root complex.",
+        "PublicDescription": "Average read bandwidth of requests from any source to all PCIe BAR and CXL HDM ranges under this PCIe root complex.",
+        "Compat": "1070036b",
+        "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+    },
+    {
+        "MetricName": "pcie_tgt_avg_wr_bandwidth_to_all_dst",
+        "MetricGroup": "PCIE_TGT_Bandwidth;PCIE_TGT_BW_PCIE_BAR_CXL_HDM",
+        "MetricExpr": "PCIE_TGT_WR_BYTES@dst_addr_en=1,dst_addr_base=0,dst_addr_mask=0@ / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average write bandwidth to all PCIe BAR and CXL HDM ranges under this PCIe root complex.",
+        "PublicDescription": "Average write bandwidth of requests from any source to all PCIe BAR and CXL HDM ranges under this PCIe root complex.",
+        "Compat": "1070036b",
+        "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+    },
+    {
+        "MetricName": "pcie_tgt_avg_rd_bandwidth_to_pcie_bar",
+        "MetricGroup": "PCIE_TGT_Bandwidth;PCIE_TGT_BW_PCIE_BAR",
+        "MetricExpr": "PCIE_TGT_RD_BYTES / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average read bandwidth of PCIe BAR traffic to all root ports under this PCIe root complex.",
+        "PublicDescription": "Average read bandwidth of PCIe BAR traffic from any source to all root ports under this PCIe root complex.",
+        "Compat": "1070036b",
+        "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+    },
+    {
+        "MetricName": "pcie_tgt_avg_wr_bandwidth_to_pcie_bar",
+        "MetricGroup": "PCIE_TGT_Bandwidth;PCIE_TGT_BW_PCIE_BAR",
+        "MetricExpr": "PCIE_TGT_WR_BYTES / 1e6 / duration_time",
+        "ScaleUnit": "1MB/s",
+        "BriefDescription": "Average write bandwidth of PCIe BAR traffic to all root ports under this PCIe root complex.",
+        "PublicDescription": "Average write bandwidth of PCIe BAR traffic from any source to all root ports under this PCIe root complex.",
+        "Compat": "1070036b",
+        "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+    }
+]
-- 
2.43.0

[PATCH 5/6] perf jevents: Add support for NVIDIA Tegra410 CPU Memory Latency PMU aliasing

[Besar Wicaksono]

Add alias support for NVIDIA Tegra410 CPU Memory Latency PMU events.

Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
---
 .../arm64/nvidia/t410/sys/uncore-cpu_mem.json | 48 +++++++++++++++++++
 1 file changed, 48 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-cpu_mem.json

diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-cpu_mem.json b/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-cpu_mem.json
new file mode 100644
index 000000000000..85ebe6fa20e2
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-cpu_mem.json
@@ -0,0 +1,48 @@
+[
+    {
+        "EventCode": "0x0",
+        "EventName": "CMEM_CYCLES",
+        "BriefDescription": "Counts elapsed MSN bridge cycles for the CMEM read-latency counters.",
+        "PublicDescription": "Counts elapsed Memory Switch Node (MSN) bridge cycles for the CMEM read-latency counters. All MSN instances share this clock, so the count is read from the first instance.",
+        "Compat": "NVDA2021",
+        "Unit": "nvidia_cmem_latency_pmu_"
+    },
+    {
+        "EventCode": "0x1",
+        "EventName": "CMEM_RD_REQ",
+        "BriefDescription": "Counts local CMEM read requests at the edge of the UCF (post SLC), in 32-byte units, from all requesters.",
+        "PublicDescription": "Counts read requests at the edge of the Unified Coherence Fabric (UCF), after the System Level Cache (SLC), to local CPU DRAM (CMEM), at 32-byte granularity. A read of up to 32 bytes adds one; a 64-byte read adds two. It counts reads from all requesters, local and remote, summed over all Memory Switch Node (MSN) instances and channels. There is no requester or security-state filtering.",
+        "Compat": "NVDA2021",
+        "Unit": "nvidia_cmem_latency_pmu_"
+    },
+    {
+        "EventCode": "0x2",
+        "EventName": "CMEM_RD_CUM_OUTS",
+        "BriefDescription": "Accumulates the in-flight read requests counted by CMEM_RD_REQ each MSN bridge cycle.",
+        "PublicDescription": "Accumulates the in-flight read requests counted by CMEM_RD_REQ each Memory Switch Node (MSN) bridge cycle. Pair the two for the average read latency.",
+        "Compat": "NVDA2021",
+        "Unit": "nvidia_cmem_latency_pmu_"
+    },
+    {
+        "MetricName": "cmem_freq",
+        "MetricGroup": "CMEM_Frequency;CMEM_Read_Latency",
+        "MetricConstraint": "NO_GROUP_EVENTS",
+        "MetricExpr": "(CMEM_CYCLES / aggr_nr(CMEM_CYCLES)) / 1e9 / duration_time",
+        "ScaleUnit": "1GHz",
+        "BriefDescription": "MSN bridge clock frequency of the CMEM read-latency counters.",
+        "PublicDescription": "Average Memory Switch Node (MSN) bridge clock frequency over the measurement interval. This is the clock of the CMEM read-latency counters.",
+        "Compat": "NVDA2021",
+        "Unit": "nvidia_cmem_latency_pmu_"
+    },
+    {
+        "MetricName": "cmem_avg_rd_latency",
+        "MetricGroup": "CMEM_Read_Latency",
+        "MetricConstraint": "NO_GROUP_EVENTS",
+        "MetricExpr": "(CMEM_RD_CUM_OUTS / CMEM_RD_REQ) / cmem_freq",
+        "ScaleUnit": "1ns/request",
+        "BriefDescription": "Average local CMEM read latency from the edge of the UCF (post SLC) to CPU DRAM, for all requesters.",
+        "PublicDescription": "Average latency of the read requests counted by CMEM_RD_REQ, from the edge of the Unified Coherence Fabric (UCF), after the System Level Cache (SLC), to local CPU DRAM (CMEM).",
+        "Compat": "NVDA2021",
+        "Unit": "nvidia_cmem_latency_pmu_"
+    }
+]
-- 
2.43.0

[PATCH 6/6] perf jevents: Add support for NVIDIA Tegra410 C2C PMU aliasing

[Besar Wicaksono]

Add alias support for NVIDIA Tegra410 C2C PMU events.

Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
---
 .../arm64/nvidia/t410/sys/uncore-nvclink.json |  75 ++++++++++
 .../arm64/nvidia/t410/sys/uncore-nvdlink.json |  48 +++++++
 .../nvidia/t410/sys/uncore-nvlink_c2c.json    | 129 ++++++++++++++++++
 3 files changed, 252 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-nvclink.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-nvdlink.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-nvlink_c2c.json

diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-nvclink.json b/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-nvclink.json
new file mode 100644
index 000000000000..fe94ae121a8d
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-nvclink.json
@@ -0,0 +1,75 @@
+[
+    {
+        "EventCode": "0x0",
+        "EventName": "NVCLINK_CYCLES",
+        "BriefDescription": "Counts NV-CLink interface clock cycles.",
+        "PublicDescription": "Counts NV-CLink interface clock cycles. All NV-CLink instances share this clock, so the count is read from the first instance.",
+        "Compat": "NVDA2022",
+        "Unit": "nvidia_nvclink_pmu_"
+    },
+    {
+        "EventCode": "0x1",
+        "EventName": "NVCLINK_IN_RD_CUM_OUTS",
+        "BriefDescription": "Accumulates the outstanding incoming read requests counted by NVCLINK_IN_RD_REQ each NV-CLink interface cycle.",
+        "PublicDescription": "Accumulates the outstanding incoming read requests counted by NVCLINK_IN_RD_REQ each NV-CLink interface cycle. Pair the two for the average read latency.",
+        "Compat": "NVDA2022",
+        "Unit": "nvidia_nvclink_pmu_"
+    },
+    {
+        "EventCode": "0x2",
+        "EventName": "NVCLINK_IN_RD_REQ",
+        "BriefDescription": "Counts incoming read requests from the remote Tegra SoC at the NV-CLink interface.",
+        "PublicDescription": "Counts incoming read requests from the remote Tegra SoC at the NV-CLink interface, where local memory or a local device responds with data. Request size can be from 1 to 256 bytes. The count is summed over all NV-CLink instances.",
+        "Compat": "NVDA2022",
+        "Unit": "nvidia_nvclink_pmu_"
+    },
+    {
+        "EventCode": "0x5",
+        "EventName": "NVCLINK_OUT_RD_CUM_OUTS",
+        "BriefDescription": "Accumulates the outstanding outgoing read requests counted by NVCLINK_OUT_RD_REQ each NV-CLink interface cycle.",
+        "PublicDescription": "Accumulates the outstanding outgoing read requests counted by NVCLINK_OUT_RD_REQ each NV-CLink interface cycle. Pair the two for the average read latency.",
+        "Compat": "NVDA2022",
+        "Unit": "nvidia_nvclink_pmu_"
+    },
+    {
+        "EventCode": "0x6",
+        "EventName": "NVCLINK_OUT_RD_REQ",
+        "BriefDescription": "Counts outgoing read requests from the local Tegra SoC to the remote Tegra SoC at the NV-CLink interface.",
+        "PublicDescription": "Counts outgoing read requests from the local Tegra SoC to the remote Tegra SoC at the NV-CLink interface, where memory on the remote Tegra SoC responds with data. Request size can be from 1 to 256 bytes. The count is summed over all NV-CLink instances.",
+        "Compat": "NVDA2022",
+        "Unit": "nvidia_nvclink_pmu_"
+    },
+    {
+        "MetricName": "nvclink_freq",
+        "MetricGroup": "NVCLINK_Frequency;NVCLINK_Latency;NVCLINK_Read_Latency",
+        "MetricConstraint": "NO_GROUP_EVENTS",
+        "MetricExpr": "(NVCLINK_CYCLES / aggr_nr(NVCLINK_CYCLES)) / 1e9 / duration_time",
+        "ScaleUnit": "1GHz",
+        "BriefDescription": "NV-CLink interface clock frequency.",
+        "PublicDescription": "Average NV-CLink interface clock frequency over the measurement interval.",
+        "Compat": "NVDA2022",
+        "Unit": "nvidia_nvclink_pmu_"
+    },
+    {
+        "MetricName": "nvclink_in_avg_rd_latency",
+        "MetricGroup": "NVCLINK_Latency;NVCLINK_Read_Latency;NVCLINK_Incoming",
+        "MetricConstraint": "NO_GROUP_EVENTS",
+        "MetricExpr": "(NVCLINK_IN_RD_CUM_OUTS / NVCLINK_IN_RD_REQ) / nvclink_freq",
+        "ScaleUnit": "1ns/request",
+        "BriefDescription": "Average latency of incoming read requests from the remote Tegra SoC at the NV-CLink interface.",
+        "PublicDescription": "Average latency of the incoming read requests counted by NVCLINK_IN_RD_REQ, measured at the NV-CLink interface.",
+        "Compat": "NVDA2022",
+        "Unit": "nvidia_nvclink_pmu_"
+    },
+    {
+        "MetricName": "nvclink_out_avg_rd_latency",
+        "MetricGroup": "NVCLINK_Latency;NVCLINK_Read_Latency;NVCLINK_Outgoing",
+        "MetricConstraint": "NO_GROUP_EVENTS",
+        "MetricExpr": "(NVCLINK_OUT_RD_CUM_OUTS / NVCLINK_OUT_RD_REQ) / nvclink_freq",
+        "ScaleUnit": "1ns/request",
+        "BriefDescription": "Average latency of outgoing read requests sent by the local Tegra SoC to the remote Tegra SoC at the NV-CLink interface.",
+        "PublicDescription": "Average latency of the outgoing read requests counted by NVCLINK_OUT_RD_REQ, measured at the NV-CLink interface.",
+        "Compat": "NVDA2022",
+        "Unit": "nvidia_nvclink_pmu_"
+    }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-nvdlink.json b/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-nvdlink.json
new file mode 100644
index 000000000000..c8f5d97a0ffb
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-nvdlink.json
@@ -0,0 +1,48 @@
+[
+    {
+        "EventCode": "0x0",
+        "EventName": "NVDLINK_CYCLES",
+        "BriefDescription": "Counts NV-DLink interface clock cycles.",
+        "PublicDescription": "Counts NV-DLink interface clock cycles. All NV-DLink instances share this clock, so the count is read from the first instance.",
+        "Compat": "NVDA2020",
+        "Unit": "nvidia_nvdlink_pmu_"
+    },
+    {
+        "EventCode": "0x1",
+        "EventName": "NVDLINK_IN_RD_CUM_OUTS",
+        "BriefDescription": "Accumulates the outstanding read requests counted by NVDLINK_IN_RD_REQ each NV-DLink interface cycle.",
+        "PublicDescription": "Accumulates the outstanding read requests counted by NVDLINK_IN_RD_REQ each NV-DLink interface cycle. Pair the two for the average read latency.",
+        "Compat": "NVDA2020",
+        "Unit": "nvidia_nvdlink_pmu_"
+    },
+    {
+        "EventCode": "0x2",
+        "EventName": "NVDLINK_IN_RD_REQ",
+        "BriefDescription": "Counts read requests to local CXL memory at the NV-DLink interface.",
+        "PublicDescription": "Counts read requests to local CXL memory at the NV-DLink interface, from all requesters, local and remote. Request size can be from 1 to 256 bytes. The count is summed over all NV-DLink instances.",
+        "Compat": "NVDA2020",
+        "Unit": "nvidia_nvdlink_pmu_"
+    },
+    {
+        "MetricName": "nvdlink_freq",
+        "MetricGroup": "NVDLINK_Frequency;NVDLINK_Latency;NVDLINK_Read_Latency",
+        "MetricConstraint": "NO_GROUP_EVENTS",
+        "MetricExpr": "(NVDLINK_CYCLES / aggr_nr(NVDLINK_CYCLES)) / 1e9 / duration_time",
+        "ScaleUnit": "1GHz",
+        "BriefDescription": "NV-DLink interface clock frequency.",
+        "PublicDescription": "Average NV-DLink interface clock frequency over the measurement interval.",
+        "Compat": "NVDA2020",
+        "Unit": "nvidia_nvdlink_pmu_"
+    },
+    {
+        "MetricName": "nvdlink_in_avg_rd_latency",
+        "MetricGroup": "NVDLINK_Latency;NVDLINK_Read_Latency",
+        "MetricConstraint": "NO_GROUP_EVENTS",
+        "MetricExpr": "(NVDLINK_IN_RD_CUM_OUTS / NVDLINK_IN_RD_REQ) / nvdlink_freq",
+        "ScaleUnit": "1ns/request",
+        "BriefDescription": "Average latency of read requests to local CXL memory at the NV-DLink interface.",
+        "PublicDescription": "Average latency of the read requests counted by NVDLINK_IN_RD_REQ, measured at the NV-DLink interface.",
+        "Compat": "NVDA2020",
+        "Unit": "nvidia_nvdlink_pmu_"
+    }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-nvlink_c2c.json b/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-nvlink_c2c.json
new file mode 100644
index 000000000000..dafcf7e600b0
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-nvlink_c2c.json
@@ -0,0 +1,129 @@
+[
+    {
+        "EventCode": "0x0",
+        "EventName": "NVLINK_C2C_CYCLES",
+        "BriefDescription": "Counts NVLink-C2C interface clock cycles.",
+        "PublicDescription": "Counts NVLink-C2C interface clock cycles. All NVLink-C2C instances share this clock, so the count is read from the first instance.",
+        "Compat": "NVDA2023",
+        "Unit": "nvidia_nvlink_c2c_pmu_"
+    },
+    {
+        "EventCode": "0x1",
+        "EventName": "NVLINK_C2C_IN_RD_CUM_OUTS",
+        "BriefDescription": "Accumulates the outstanding incoming read requests counted by NVLINK_C2C_IN_RD_REQ each NVLink-C2C interface cycle.",
+        "PublicDescription": "Accumulates the outstanding incoming read requests counted by NVLINK_C2C_IN_RD_REQ each NVLink-C2C interface cycle. Pair the two for the average read latency. The gpu_mask filter works as described for NVLINK_C2C_IN_RD_REQ.",
+        "Compat": "NVDA2023",
+        "Unit": "nvidia_nvlink_c2c_pmu_"
+    },
+    {
+        "EventCode": "0x2",
+        "EventName": "NVLINK_C2C_IN_RD_REQ",
+        "BriefDescription": "Counts incoming read requests from connected GPUs or a remote Tegra SoC at the NVLink-C2C interface.",
+        "PublicDescription": "Counts incoming read requests sent by connected GPUs or a remote Tegra SoC to the local Tegra SoC at the NVLink-C2C interface, where the local Tegra SoC responds with data. Request size can be from 1 to 256 bytes. The count is summed over all NVLink-C2C instances. Filters: the gpu_mask filter selects GPUs by index, one bit per GPU. This filter is available only when GPUs are connected. An unset gpu_mask counts all GPUs.",
+        "Compat": "NVDA2023",
+        "Unit": "nvidia_nvlink_c2c_pmu_"
+    },
+    {
+        "EventCode": "0x3",
+        "EventName": "NVLINK_C2C_IN_WR_CUM_OUTS",
+        "BriefDescription": "Accumulates the outstanding incoming write requests counted by NVLINK_C2C_IN_WR_REQ each NVLink-C2C interface cycle.",
+        "PublicDescription": "Accumulates the outstanding incoming write requests counted by NVLINK_C2C_IN_WR_REQ each NVLink-C2C interface cycle. Available only when GPUs are connected. Pair the two for the average write latency. The gpu_mask filter works as described for NVLINK_C2C_IN_WR_REQ.",
+        "Compat": "NVDA2023",
+        "Unit": "nvidia_nvlink_c2c_pmu_"
+    },
+    {
+        "EventCode": "0x4",
+        "EventName": "NVLINK_C2C_IN_WR_REQ",
+        "BriefDescription": "Counts incoming write requests from connected GPUs to the local Tegra SoC at the NVLink-C2C interface.",
+        "PublicDescription": "Counts incoming write requests sent by connected GPUs to the local Tegra SoC at the NVLink-C2C interface, where the GPU sends the data. Request size can be from 1 to 256 bytes. Available only when GPUs are connected. The count is summed over all NVLink-C2C instances. Filters: the gpu_mask filter selects GPUs by index, one bit per GPU. An unset gpu_mask counts all GPUs.",
+        "Compat": "NVDA2023",
+        "Unit": "nvidia_nvlink_c2c_pmu_"
+    },
+    {
+        "EventCode": "0x5",
+        "EventName": "NVLINK_C2C_OUT_RD_CUM_OUTS",
+        "BriefDescription": "Accumulates the outstanding outgoing read requests counted by NVLINK_C2C_OUT_RD_REQ each NVLink-C2C interface cycle.",
+        "PublicDescription": "Accumulates the outstanding outgoing read requests counted by NVLINK_C2C_OUT_RD_REQ each NVLink-C2C interface cycle. Pair the two for the average read latency. The gpu_mask filter works as described for NVLINK_C2C_OUT_RD_REQ.",
+        "Compat": "NVDA2023",
+        "Unit": "nvidia_nvlink_c2c_pmu_"
+    },
+    {
+        "EventCode": "0x6",
+        "EventName": "NVLINK_C2C_OUT_RD_REQ",
+        "BriefDescription": "Counts outgoing read requests to connected GPUs or a remote Tegra SoC at the NVLink-C2C interface.",
+        "PublicDescription": "Counts outgoing read requests from all requesters to connected GPUs or a remote Tegra SoC at the NVLink-C2C interface, where the GPU or remote Tegra SoC responds with data. Request size can be from 1 to 256 bytes. The count is summed over all NVLink-C2C instances. Filters: the gpu_mask filter selects GPUs by index, one bit per GPU. This filter is available only when GPUs are connected. An unset gpu_mask counts all GPUs.",
+        "Compat": "NVDA2023",
+        "Unit": "nvidia_nvlink_c2c_pmu_"
+    },
+    {
+        "EventCode": "0x7",
+        "EventName": "NVLINK_C2C_OUT_WR_CUM_OUTS",
+        "BriefDescription": "Accumulates the outstanding outgoing write requests counted by NVLINK_C2C_OUT_WR_REQ each NVLink-C2C interface cycle.",
+        "PublicDescription": "Accumulates the outstanding outgoing write requests counted by NVLINK_C2C_OUT_WR_REQ each NVLink-C2C interface cycle. Available only when GPUs are connected. Pair the two for the average write latency. The gpu_mask filter works as described for NVLINK_C2C_OUT_WR_REQ.",
+        "Compat": "NVDA2023",
+        "Unit": "nvidia_nvlink_c2c_pmu_"
+    },
+    {
+        "EventCode": "0x8",
+        "EventName": "NVLINK_C2C_OUT_WR_REQ",
+        "BriefDescription": "Counts outgoing write requests to connected GPUs at the NVLink-C2C interface.",
+        "PublicDescription": "Counts outgoing write requests from all requesters to connected GPUs at the NVLink-C2C interface, where the requester sends the data. Request size can be from 1 to 256 bytes. Available only when GPUs are connected. The count is summed over all NVLink-C2C instances. Filters: the gpu_mask filter selects GPUs by index, one bit per GPU. An unset gpu_mask counts all GPUs.",
+        "Compat": "NVDA2023",
+        "Unit": "nvidia_nvlink_c2c_pmu_"
+    },
+    {
+        "MetricName": "nvlink_c2c_freq",
+        "MetricGroup": "NVLINK_C2C_Frequency;NVLINK_C2C_Latency;NVLINK_C2C_Read_Latency;NVLINK_C2C_Write_Latency",
+        "MetricConstraint": "NO_GROUP_EVENTS",
+        "MetricExpr": "(NVLINK_C2C_CYCLES / aggr_nr(NVLINK_C2C_CYCLES)) / 1e9 / duration_time",
+        "ScaleUnit": "1GHz",
+        "BriefDescription": "NVLink-C2C interface clock frequency.",
+        "PublicDescription": "Average NVLink-C2C interface clock frequency over the measurement interval.",
+        "Compat": "NVDA2023",
+        "Unit": "nvidia_nvlink_c2c_pmu_"
+    },
+    {
+        "MetricName": "nvlink_c2c_in_avg_rd_latency",
+        "MetricGroup": "NVLINK_C2C_Latency;NVLINK_C2C_Read_Latency;NVLINK_C2C_Incoming",
+        "MetricConstraint": "NO_GROUP_EVENTS",
+        "MetricExpr": "(NVLINK_C2C_IN_RD_CUM_OUTS / NVLINK_C2C_IN_RD_REQ) / nvlink_c2c_freq",
+        "ScaleUnit": "1ns/request",
+        "BriefDescription": "Average latency of incoming read requests at the NVLink-C2C interface.",
+        "PublicDescription": "Average latency of the incoming read requests counted by NVLINK_C2C_IN_RD_REQ, measured at the NVLink-C2C interface.",
+        "Compat": "NVDA2023",
+        "Unit": "nvidia_nvlink_c2c_pmu_"
+    },
+    {
+        "MetricName": "nvlink_c2c_in_avg_wr_latency",
+        "MetricGroup": "NVLINK_C2C_Latency;NVLINK_C2C_Write_Latency;NVLINK_C2C_Incoming",
+        "MetricConstraint": "NO_GROUP_EVENTS",
+        "MetricExpr": "(NVLINK_C2C_IN_WR_CUM_OUTS / NVLINK_C2C_IN_WR_REQ) / nvlink_c2c_freq",
+        "ScaleUnit": "1ns/request",
+        "BriefDescription": "Average latency of incoming write requests from connected GPUs at the NVLink-C2C interface.",
+        "PublicDescription": "Average latency of the incoming write requests counted by NVLINK_C2C_IN_WR_REQ, measured at the NVLink-C2C interface. Available only when GPUs are connected.",
+        "Compat": "NVDA2023",
+        "Unit": "nvidia_nvlink_c2c_pmu_"
+    },
+    {
+        "MetricName": "nvlink_c2c_out_avg_rd_latency",
+        "MetricGroup": "NVLINK_C2C_Latency;NVLINK_C2C_Read_Latency;NVLINK_C2C_Outgoing",
+        "MetricConstraint": "NO_GROUP_EVENTS",
+        "MetricExpr": "(NVLINK_C2C_OUT_RD_CUM_OUTS / NVLINK_C2C_OUT_RD_REQ) / nvlink_c2c_freq",
+        "ScaleUnit": "1ns/request",
+        "BriefDescription": "Average latency of outgoing read requests at the NVLink-C2C interface.",
+        "PublicDescription": "Average latency of the outgoing read requests counted by NVLINK_C2C_OUT_RD_REQ, measured at the NVLink-C2C interface.",
+        "Compat": "NVDA2023",
+        "Unit": "nvidia_nvlink_c2c_pmu_"
+    },
+    {
+        "MetricName": "nvlink_c2c_out_avg_wr_latency",
+        "MetricGroup": "NVLINK_C2C_Latency;NVLINK_C2C_Write_Latency;NVLINK_C2C_Outgoing",
+        "MetricConstraint": "NO_GROUP_EVENTS",
+        "MetricExpr": "(NVLINK_C2C_OUT_WR_CUM_OUTS / NVLINK_C2C_OUT_WR_REQ) / nvlink_c2c_freq",
+        "ScaleUnit": "1ns/request",
+        "BriefDescription": "Average latency of outgoing write requests to connected GPUs at the NVLink-C2C interface.",
+        "PublicDescription": "Average latency of the outgoing write requests counted by NVLINK_C2C_OUT_WR_REQ, measured at the NVLink-C2C interface. Available only when GPUs are connected.",
+        "Compat": "NVDA2023",
+        "Unit": "nvidia_nvlink_c2c_pmu_"
+    }
+]
-- 
2.43.0

Re: [PATCH 6/6] perf jevents: Add support for NVIDIA Tegra410 C2C PMU aliasing

[sashiko-bot]

> Add alias support for NVIDIA Tegra410 C2C PMU events.
> 
> Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261019164241.403644-1-bwicaksono@nvidia.com?part=6

Re: [PATCH 5/6] perf jevents: Add support for NVIDIA Tegra410 CPU Memory Latency PMU aliasing

[sashiko-bot]

> Add alias support for NVIDIA Tegra410 CPU Memory Latency PMU events.
> 
> Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261019164241.403644-1-bwicaksono@nvidia.com?part=5

Re: [PATCH 1/6] perf jevents: Process model files before sys subdirectories

[sashiko-bot]

> jevents walks each directory in name order, mixing files and
> subdirectories. When it reaches a sys/ directory inside a model
> directory, process_one_file() flushes the model's pending tables and
> switches the pending table name to the sys table. After the walk
> returns from sys/, nothing switches it back, so model JSON files whose
> names sort after "sys" (for example tlb.json) are added to the sys
> table. Sys tables are only matched by Compat against uncore PMU
> identifiers, so these core events are lost: perf list doesn't show
> them and perf stat rejects them.
> 
> Visit the files of a directory before its subdirectories, so that all
> of a model's JSON files are added to the model's table before a sys/
> subdirectory is processed. The generated pmu-events.c is unchanged for
> the existing event directories.
> 
> Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261019164241.403644-1-bwicaksono@nvidia.com?part=1

Re: [PATCH 4/6] perf jevents: Add support for NVIDIA Tegra410 PCIE-TGT PMU aliasing

[sashiko-bot]

> Add alias support for NVIDIA Tegra410 PCIE-TGT PMU events and metrics.
> 
> Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261019164241.403644-1-bwicaksono@nvidia.com?part=4

Re: [PATCH 2/6] perf jevents: Add support for NVIDIA Tegra410 UCF PMU aliasing

[sashiko-bot]

> Add alias support for NVIDIA Tegra410 UCF PMU events and metrics.
> 
> Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261019164241.403644-1-bwicaksono@nvidia.com?part=2

Re: [PATCH 3/6] perf jevents: Add support for NVIDIA Tegra410 PCIE PMU aliasing

[sashiko-bot]

> Add alias support for NVIDIA Tegra410 PCIE PMU events and metrics.
> 
> Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261019164241.403644-1-bwicaksono@nvidia.com?part=3

Re: [PATCH 0/6] perf jevents: Add NVIDIA Tegra410 uncore PMU events and metrics

[James Clark]

On 19/10/2026 17:42, Besar Wicaksono wrote:
> Add event aliases and derived metrics for the NVIDIA Tegra410 uncore
> PMUs.
> 
> The series covers the UCF, PCIe, PCIe target, CPU memory latency, and
> chip-to-chip interconnect PMUs. It provides symbolic names for the raw
> event encodings and metrics for bandwidth, frequency, and average read
> latency.
> 
> Patch 1 fixes a jevents ordering problem found with this layout: the
> uncore events live in arch/arm64/nvidia/t410/sys/, next to the T410 core
> events, and without the fix jevents puts the core tlb.json (which sorts
> after "sys") into the sys table, so its events are lost from perf list
> and perf stat.
> 
> Besar Wicaksono (6):
>    perf jevents: Process model files before sys subdirectories
>    perf jevents: Add support for NVIDIA Tegra410 UCF PMU aliasing
>    perf jevents: Add support for NVIDIA Tegra410 PCIE PMU aliasing
>    perf jevents: Add support for NVIDIA Tegra410 PCIE-TGT PMU aliasing
>    perf jevents: Add support for NVIDIA Tegra410 CPU Memory Latency PMU
>      aliasing
>    perf jevents: Add support for NVIDIA Tegra410 C2C PMU aliasing
> 
>   .../arm64/nvidia/t410/sys/uncore-cpu_mem.json |  48 ++
>   .../arm64/nvidia/t410/sys/uncore-nvclink.json |  75 ++
>   .../arm64/nvidia/t410/sys/uncore-nvdlink.json |  48 ++
>   .../nvidia/t410/sys/uncore-nvlink_c2c.json    | 129 ++++
>   .../arm64/nvidia/t410/sys/uncore-pcie.json    | 247 +++++++
>   .../nvidia/t410/sys/uncore-pcie_tgt.json      |  93 +++
>   .../arm64/nvidia/t410/sys/uncore-ucf.json     | 693 ++++++++++++++++++
>   tools/perf/pmu-events/jevents.py              |   4 +-
>   8 files changed, 1336 insertions(+), 1 deletion(-)
>   create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-cpu_mem.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-nvclink.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-nvdlink.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-nvlink_c2c.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie_tgt.json
>   create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-ucf.json
> 

Reviewed-by: James Clark <james.clark@linaro.org>

Re: [PATCH 3/6] perf jevents: Add support for NVIDIA Tegra410 PCIE PMU aliasing

[Chun-Tse Shao]

Hi Besar,

Thanks for the series. I tested this on a 2-socket Tegra410. With
--metric-only, each PCIe metric shows up once per socket, with `nan`
("none" with -j) in the other socket's column, so -j has the same key
twice in each row. "counters" is also 0 for socket 1, because it comes
from the first event, which belongs to socket 0:

```
$ perf stat -a --per-socket -M pcie_avg_wr_bandwidth_to_all_dst -j
--metric-only -- sleep 1
{"socket" : "S268435456", "counters" : 6, "MB/s
pcie_avg_wr_bandwidth_to_all_dst" : "0.1", "MB/s
pcie_avg_wr_bandwidth_to_all_dst" : "none"}
{"socket" : "S285212672", "counters" : 0, "MB/s
pcie_avg_wr_bandwidth_to_all_dst" : "none", "MB/s
pcie_avg_wr_bandwidth_to_all_dst" : "0.9"}
```

As in [1], a single PMU per RC with cpumask `0,88`, or the socket last
in the PMU name, would fix this.

[1] https://lore.kernel.org/linux-perf-users/CAJpZYjWLRiyNbzoGpA-2KE0zHgQn2gc0V943WxJEr5K5aZtRYA@mail.gmail.com/

Thanks,
CT

On Mon, Oct 19, 2026 at 9:45 AM Besar Wicaksono <bwicaksono@nvidia.com> wrote:
>
> Add alias support for NVIDIA Tegra410 PCIE PMU events and metrics.
>
> Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
> ---
>  .../arm64/nvidia/t410/sys/uncore-pcie.json    | 247 ++++++++++++++++++
>  1 file changed, 247 insertions(+)
>  create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie.json
>
> diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie.json b/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie.json
> new file mode 100644
> index 000000000000..37c3eac305e5
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie.json
> @@ -0,0 +1,247 @@
> +[
> +    {
> +        "EventCode": "0x100000000",
> +        "EventName": "PCIE_CYCLES",
> +        "BriefDescription": "Counts cycles at the PCIe interface to the Tegra SoC data fabric.",
> +        "PublicDescription": "Counts cycles at the PCIe interface to the Tegra SoC data fabric.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    },
> +    {
> +        "EventCode": "0x2",
> +        "EventName": "PCIE_RD_REQ",
> +        "BriefDescription": "Counts read requests from PCIe devices under this PCIe root complex to memory or another PCIe device.",
> +        "PublicDescription": "Counts read requests from PCIe devices under this PCIe root complex to memory or another PCIe device, where the target responds with data. Request size can be from 1 to 256 bytes. Filters: src_rp_mask selects the requesting root ports. Alternatively, src_bdf with src_bdf_en selects one requesting device (BDF); it cannot be combined with src_rp_mask and applies to all counters of this PMU. Destination filters select the memory type of the request address: dst_loc_cmem local CMEM, dst_loc_gmem local GMEM, dst_loc_pcie_p2p local PCIe peer addresses, dst_loc_pcie_cxl local CXL memory, dst_rem remote memory. This is the address's home type, not where the data currently resides; local or remote is determined by the home socket of the address. An unset source filter counts all root ports; an unset destination filter counts all destinations.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    },
> +    {
> +        "EventCode": "0x3",
> +        "EventName": "PCIE_WR_REQ",
> +        "BriefDescription": "Counts write requests from PCIe devices under this PCIe root complex to memory or another PCIe device.",
> +        "PublicDescription": "Counts write requests from PCIe devices under this PCIe root complex to memory or another PCIe device, where the PCIe device sends data. Request size can be from 1 to 256 bytes. Filters: src_rp_mask selects the requesting root ports. Alternatively, src_bdf with src_bdf_en selects one requesting device (BDF); it cannot be combined with src_rp_mask and applies to all counters of this PMU. Destination filters select the memory type of the request address: dst_loc_cmem local CMEM, dst_loc_gmem local GMEM, dst_loc_pcie_p2p local PCIe peer addresses, dst_loc_pcie_cxl local CXL memory, dst_rem remote memory. This is the address's home type, not where the data currently resides; local or remote is determined by the home socket of the address. An unset source filter counts all root ports; an unset destination filter counts all destinations.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    },
> +    {
> +        "EventCode": "0x0",
> +        "EventName": "PCIE_RD_BYTES",
> +        "BriefDescription": "Counts bytes transferred by the read requests counted by PCIE_RD_REQ.",
> +        "PublicDescription": "Counts bytes transferred by the read requests counted by PCIE_RD_REQ. Source and destination filters work as described for PCIE_RD_REQ.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    },
> +    {
> +        "EventCode": "0x1",
> +        "EventName": "PCIE_WR_BYTES",
> +        "BriefDescription": "Counts bytes transferred by the write requests counted by PCIE_WR_REQ.",
> +        "PublicDescription": "Counts bytes transferred by the write requests counted by PCIE_WR_REQ. Source and destination filters work as described for PCIE_WR_REQ.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    },
> +    {
> +        "EventCode": "0x4",
> +        "EventName": "PCIE_RD_CUM_OUTS",
> +        "BriefDescription": "Accumulates the outstanding read requests counted by PCIE_RD_REQ each cycle at the PCIe interface.",
> +        "PublicDescription": "Accumulates the outstanding read requests counted by PCIE_RD_REQ each cycle at the PCIe interface. Pair the two under the same filters for the average read latency. Source and destination filters work as described for PCIE_RD_REQ.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    },
> +    {
> +        "MetricName": "pcie_freq",
> +        "MetricGroup": "PCIE_Frequency;PCIE_Read_Latency",
> +        "MetricConstraint": "NO_GROUP_EVENTS",
> +        "MetricExpr": "(PCIE_CYCLES / aggr_nr(PCIE_CYCLES)) / 1e9 / duration_time",
> +        "ScaleUnit": "1GHz",
> +        "BriefDescription": "Frequency of the cycles at the PCIe interface to the Tegra SoC data fabric.",
> +        "PublicDescription": "Average frequency of the cycles at the PCIe interface to the Tegra SoC data fabric over the measurement interval.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    },
> +    {
> +        "MetricName": "pcie_avg_rd_bandwidth_to_all_dst",
> +        "MetricGroup": "PCIE_Bandwidth;PCIE_To_All_Destinations",
> +        "MetricExpr": "PCIE_RD_BYTES@dst_loc_cmem=1,dst_loc_gmem=1,dst_loc_pcie_p2p=1,dst_loc_pcie_cxl=1,dst_rem=1@ / 1e6 / duration_time",
> +        "ScaleUnit": "1MB/s",
> +        "BriefDescription": "Average read bandwidth from PCIe devices under this PCIe root complex to all destinations.",
> +        "PublicDescription": "Average read bandwidth of requests from all PCIe devices under this PCIe root complex to all destinations: local CMEM, local GMEM, local PCIe peer addresses, local CXL memory and remote memory.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    },
> +    {
> +        "MetricName": "pcie_avg_wr_bandwidth_to_all_dst",
> +        "MetricGroup": "PCIE_Bandwidth;PCIE_To_All_Destinations",
> +        "MetricExpr": "PCIE_WR_BYTES@dst_loc_cmem=1,dst_loc_gmem=1,dst_loc_pcie_p2p=1,dst_loc_pcie_cxl=1,dst_rem=1@ / 1e6 / duration_time",
> +        "ScaleUnit": "1MB/s",
> +        "BriefDescription": "Average write bandwidth from PCIe devices under this PCIe root complex to all destinations.",
> +        "PublicDescription": "Average write bandwidth of requests from all PCIe devices under this PCIe root complex to all destinations: local CMEM, local GMEM, local PCIe peer addresses, local CXL memory and remote memory.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    },
> +    {
> +        "MetricName": "pcie_avg_rd_latency_to_all_dst",
> +        "MetricGroup": "PCIE_Read_Latency;PCIE_To_All_Destinations",
> +        "MetricConstraint": "NO_GROUP_EVENTS",
> +        "MetricExpr": "(PCIE_RD_CUM_OUTS@dst_loc_cmem=1,dst_loc_gmem=1,dst_loc_pcie_p2p=1,dst_loc_pcie_cxl=1,dst_rem=1@ / PCIE_RD_REQ@dst_loc_cmem=1,dst_loc_gmem=1,dst_loc_pcie_p2p=1,dst_loc_pcie_cxl=1,dst_rem=1@) / pcie_freq",
> +        "ScaleUnit": "1ns/request",
> +        "BriefDescription": "Average read latency from PCIe devices under this PCIe root complex to all destinations.",
> +        "PublicDescription": "Average latency of read requests from all PCIe devices under this PCIe root complex to all destinations: local CMEM, local GMEM, local PCIe peer addresses, local CXL memory and remote memory.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    },
> +    {
> +        "MetricName": "pcie_avg_rd_bandwidth_to_local_cmem",
> +        "MetricGroup": "PCIE_Bandwidth;PCIE_Read;PCIE_To_Local_CMEM",
> +        "MetricExpr": "PCIE_RD_BYTES@dst_loc_cmem=1@ / 1e6 / duration_time",
> +        "ScaleUnit": "1MB/s",
> +        "BriefDescription": "Average read bandwidth from PCIe devices under this PCIe root complex to local CMEM.",
> +        "PublicDescription": "Average read bandwidth of requests from all PCIe devices under this PCIe root complex to local CMEM.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    },
> +    {
> +        "MetricName": "pcie_avg_wr_bandwidth_to_local_cmem",
> +        "MetricGroup": "PCIE_Bandwidth;PCIE_Write;PCIE_To_Local_CMEM",
> +        "MetricExpr": "PCIE_WR_BYTES@dst_loc_cmem=1@ / 1e6 / duration_time",
> +        "ScaleUnit": "1MB/s",
> +        "BriefDescription": "Average write bandwidth from PCIe devices under this PCIe root complex to local CMEM.",
> +        "PublicDescription": "Average write bandwidth of requests from all PCIe devices under this PCIe root complex to local CMEM.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    },
> +    {
> +        "MetricName": "pcie_avg_rd_latency_to_local_cmem",
> +        "MetricGroup": "PCIE_Read_Latency;PCIE_Read;PCIE_To_Local_CMEM",
> +        "MetricConstraint": "NO_GROUP_EVENTS",
> +        "MetricExpr": "(PCIE_RD_CUM_OUTS@dst_loc_cmem=1@ / PCIE_RD_REQ@dst_loc_cmem=1@) / pcie_freq",
> +        "ScaleUnit": "1ns/request",
> +        "BriefDescription": "Average read latency from PCIe devices under this PCIe root complex to local CMEM.",
> +        "PublicDescription": "Average latency of read requests from all PCIe devices under this PCIe root complex to local CMEM.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    },
> +    {
> +        "MetricName": "pcie_avg_rd_bandwidth_to_local_gmem",
> +        "MetricGroup": "PCIE_Bandwidth;PCIE_Read;PCIE_To_Local_GMEM",
> +        "MetricExpr": "PCIE_RD_BYTES@dst_loc_gmem=1@ / 1e6 / duration_time",
> +        "ScaleUnit": "1MB/s",
> +        "BriefDescription": "Average read bandwidth from PCIe devices under this PCIe root complex to local GMEM.",
> +        "PublicDescription": "Average read bandwidth of requests from all PCIe devices under this PCIe root complex to local GMEM.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    },
> +    {
> +        "MetricName": "pcie_avg_wr_bandwidth_to_local_gmem",
> +        "MetricGroup": "PCIE_Bandwidth;PCIE_Write;PCIE_To_Local_GMEM",
> +        "MetricExpr": "PCIE_WR_BYTES@dst_loc_gmem=1@ / 1e6 / duration_time",
> +        "ScaleUnit": "1MB/s",
> +        "BriefDescription": "Average write bandwidth from PCIe devices under this PCIe root complex to local GMEM.",
> +        "PublicDescription": "Average write bandwidth of requests from all PCIe devices under this PCIe root complex to local GMEM.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    },
> +    {
> +        "MetricName": "pcie_avg_rd_latency_to_local_gmem",
> +        "MetricGroup": "PCIE_Read_Latency;PCIE_Read;PCIE_To_Local_GMEM",
> +        "MetricConstraint": "NO_GROUP_EVENTS",
> +        "MetricExpr": "(PCIE_RD_CUM_OUTS@dst_loc_gmem=1@ / PCIE_RD_REQ@dst_loc_gmem=1@) / pcie_freq",
> +        "ScaleUnit": "1ns/request",
> +        "BriefDescription": "Average read latency from PCIe devices under this PCIe root complex to local GMEM.",
> +        "PublicDescription": "Average latency of read requests from all PCIe devices under this PCIe root complex to local GMEM.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    },
> +    {
> +        "MetricName": "pcie_avg_rd_bandwidth_to_local_cxlmem",
> +        "MetricGroup": "PCIE_Bandwidth;PCIE_Read;PCIE_To_Local_CXLMEM",
> +        "MetricExpr": "PCIE_RD_BYTES@dst_loc_pcie_cxl=1@ / 1e6 / duration_time",
> +        "ScaleUnit": "1MB/s",
> +        "BriefDescription": "Average read bandwidth from PCIe devices under this PCIe root complex to local CXL memory.",
> +        "PublicDescription": "Average read bandwidth of requests from all PCIe devices under this PCIe root complex to local CXL memory.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    },
> +    {
> +        "MetricName": "pcie_avg_wr_bandwidth_to_local_cxlmem",
> +        "MetricGroup": "PCIE_Bandwidth;PCIE_Write;PCIE_To_Local_CXLMEM",
> +        "MetricExpr": "PCIE_WR_BYTES@dst_loc_pcie_cxl=1@ / 1e6 / duration_time",
> +        "ScaleUnit": "1MB/s",
> +        "BriefDescription": "Average write bandwidth from PCIe devices under this PCIe root complex to local CXL memory.",
> +        "PublicDescription": "Average write bandwidth of requests from all PCIe devices under this PCIe root complex to local CXL memory.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    },
> +    {
> +        "MetricName": "pcie_avg_rd_latency_to_local_cxlmem",
> +        "MetricGroup": "PCIE_Read_Latency;PCIE_Read;PCIE_To_Local_CXLMEM",
> +        "MetricConstraint": "NO_GROUP_EVENTS",
> +        "MetricExpr": "(PCIE_RD_CUM_OUTS@dst_loc_pcie_cxl=1@ / PCIE_RD_REQ@dst_loc_pcie_cxl=1@) / pcie_freq",
> +        "ScaleUnit": "1ns/request",
> +        "BriefDescription": "Average read latency from PCIe devices under this PCIe root complex to local CXL memory.",
> +        "PublicDescription": "Average latency of read requests from all PCIe devices under this PCIe root complex to local CXL memory.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    },
> +    {
> +        "MetricName": "pcie_avg_rd_bandwidth_to_remote_mem",
> +        "MetricGroup": "PCIE_Bandwidth;PCIE_Read;PCIE_To_Remote_Memory",
> +        "MetricExpr": "PCIE_RD_BYTES@dst_rem=1@ / 1e6 / duration_time",
> +        "ScaleUnit": "1MB/s",
> +        "BriefDescription": "Average read bandwidth from PCIe devices under this PCIe root complex to remote memory.",
> +        "PublicDescription": "Average read bandwidth of requests from all PCIe devices under this PCIe root complex to remote memory.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    },
> +    {
> +        "MetricName": "pcie_avg_wr_bandwidth_to_remote_mem",
> +        "MetricGroup": "PCIE_Bandwidth;PCIE_Write;PCIE_To_Remote_Memory",
> +        "MetricExpr": "PCIE_WR_BYTES@dst_rem=1@ / 1e6 / duration_time",
> +        "ScaleUnit": "1MB/s",
> +        "BriefDescription": "Average write bandwidth from PCIe devices under this PCIe root complex to remote memory.",
> +        "PublicDescription": "Average write bandwidth of requests from all PCIe devices under this PCIe root complex to remote memory.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    },
> +    {
> +        "MetricName": "pcie_avg_rd_latency_to_remote_mem",
> +        "MetricGroup": "PCIE_Read_Latency;PCIE_Read;PCIE_To_Remote_Memory",
> +        "MetricConstraint": "NO_GROUP_EVENTS",
> +        "MetricExpr": "(PCIE_RD_CUM_OUTS@dst_rem=1@ / PCIE_RD_REQ@dst_rem=1@) / pcie_freq",
> +        "ScaleUnit": "1ns/request",
> +        "BriefDescription": "Average read latency from PCIe devices under this PCIe root complex to remote memory.",
> +        "PublicDescription": "Average latency of read requests from all PCIe devices under this PCIe root complex to remote memory.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    },
> +    {
> +        "MetricName": "pcie_avg_rd_bandwidth_to_local_pcie_peer",
> +        "MetricGroup": "PCIE_Bandwidth;PCIE_Read;PCIE_To_Local_PCIE_Peer",
> +        "MetricExpr": "PCIE_RD_BYTES@dst_loc_pcie_p2p=1@ / 1e6 / duration_time",
> +        "ScaleUnit": "1MB/s",
> +        "BriefDescription": "Average read bandwidth from PCIe devices under this PCIe root complex to local PCIe peer addresses.",
> +        "PublicDescription": "Average read bandwidth of requests from all PCIe devices under this PCIe root complex to local PCIe peer addresses.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    },
> +    {
> +        "MetricName": "pcie_avg_wr_bandwidth_to_local_pcie_peer",
> +        "MetricGroup": "PCIE_Bandwidth;PCIE_Write;PCIE_To_Local_PCIE_Peer",
> +        "MetricExpr": "PCIE_WR_BYTES@dst_loc_pcie_p2p=1@ / 1e6 / duration_time",
> +        "ScaleUnit": "1MB/s",
> +        "BriefDescription": "Average write bandwidth from PCIe devices under this PCIe root complex to local PCIe peer addresses.",
> +        "PublicDescription": "Average write bandwidth of requests from all PCIe devices under this PCIe root complex to local PCIe peer addresses.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    },
> +    {
> +        "MetricName": "pcie_avg_rd_latency_to_local_pcie_peer",
> +        "MetricGroup": "PCIE_Read_Latency;PCIE_Read;PCIE_To_Local_PCIE_Peer",
> +        "MetricConstraint": "NO_GROUP_EVENTS",
> +        "MetricExpr": "(PCIE_RD_CUM_OUTS@dst_loc_pcie_p2p=1@ / PCIE_RD_REQ@dst_loc_pcie_p2p=1@) / pcie_freq",
> +        "ScaleUnit": "1ns/request",
> +        "BriefDescription": "Average read latency from PCIe devices under this PCIe root complex to local PCIe peer addresses.",
> +        "PublicDescription": "Average latency of read requests from all PCIe devices under this PCIe root complex to local PCIe peer addresses.",
> +        "Compat": "1030136b",
> +        "Unit": "nvidia_pcie_pmu_,rc_"
> +    }
> +]
> --
> 2.43.0
>

Re: [PATCH 4/6] perf jevents: Add support for NVIDIA Tegra410 PCIE-TGT PMU aliasing

[Ian Rogers]

On Mon, Oct 19, 2026 at 9:45 AM Besar Wicaksono <bwicaksono@nvidia.com> wrote:
>
> Add alias support for NVIDIA Tegra410 PCIE-TGT PMU events and metrics.
>
> Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
> ---
>  .../nvidia/t410/sys/uncore-pcie_tgt.json      | 93 +++++++++++++++++++
>  1 file changed, 93 insertions(+)
>  create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie_tgt.json
>
> diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie_tgt.json b/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie_tgt.json
> new file mode 100644
> index 000000000000..74786fc3d578
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie_tgt.json
> @@ -0,0 +1,93 @@
> +[
> +    {
> +        "EventCode": "0x4",
> +        "EventName": "PCIE_TGT_CYCLES",
> +        "BriefDescription": "Counts cycles at the PCIe interface to the Tegra SoC data fabric.",
> +        "PublicDescription": "Counts cycles at the PCIe interface to the Tegra SoC data fabric.",
> +        "Compat": "1070036b",
> +        "Unit": "nvidia_pcie_tgt_pmu_,rc_"

It looks like the PMU names are broken because of the _rc_ in their names:
https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/perf/arm_cspmu/nvidia_cspmu.c#n901
```
   .name_pattern = "nvidia_pcie_pmu_%u_rc_%u",
```
The convention is for either a numeric (preferable) or hexadecimal suffix:
https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/ABI/testing/sysfs-bus-event_source-devices
Extra information about the PMU belongs in a caps file.

By definition nothing can work with wildcard matching using the
existing PMU name, so please rename it. If a new suffix convention is
necessary then  you should update the ABI and perf tool suffix
matching logic like pmu_name_len_no_suffix:
https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/perf/util/pmus.c#n65

Thanks,
Ian Rogers

>
> +    },
> +    {
> +        "EventCode": "0x2",
> +        "EventName": "PCIE_TGT_RD_REQ",
> +        "BriefDescription": "Counts read requests from any source to PCIe BAR or CXL HDM ranges under this PCIe root complex.",
> +        "PublicDescription": "Counts read requests from any source to PCIe BAR or CXL HDM ranges under this PCIe root complex, where the target responds with data. Request size can be from 1 to 256 bytes. Filters: dst_rp_mask selects PCIe BAR traffic to root ports (bit n = root port n). dst_addr_en with dst_addr_base and dst_addr_mask selects PCIe BAR or CXL HDM addresses that equal the base in the mask's set bits. If both dst_rp_mask and the address filter are set, a request matching either is counted. With no filter, PCIe BAR traffic to all root ports is counted.",
> +        "Compat": "1070036b",
> +        "Unit": "nvidia_pcie_tgt_pmu_,rc_"
> +    },
> +    {
> +        "EventCode": "0x3",
> +        "EventName": "PCIE_TGT_WR_REQ",
> +        "BriefDescription": "Counts write requests from any source to PCIe BAR or CXL HDM ranges under this PCIe root complex.",
> +        "PublicDescription": "Counts write requests from any source to PCIe BAR or CXL HDM ranges under this PCIe root complex, where the source sends data. Request size can be from 1 to 256 bytes. Filters: dst_rp_mask selects PCIe BAR traffic to root ports (bit n = root port n). dst_addr_en with dst_addr_base and dst_addr_mask selects PCIe BAR or CXL HDM addresses that equal the base in the mask's set bits. If both dst_rp_mask and the address filter are set, a request matching either is counted. With no filter, PCIe BAR traffic to all root ports is counted.",
> +        "Compat": "1070036b",
> +        "Unit": "nvidia_pcie_tgt_pmu_,rc_"
> +    },
> +    {
> +        "EventCode": "0x0",
> +        "EventName": "PCIE_TGT_RD_BYTES",
> +        "BriefDescription": "Counts bytes transferred by the read requests counted by PCIE_TGT_RD_REQ.",
> +        "PublicDescription": "Counts bytes transferred by the read requests counted by PCIE_TGT_RD_REQ. Destination filters work as described for PCIE_TGT_RD_REQ.",
> +        "Compat": "1070036b",
> +        "Unit": "nvidia_pcie_tgt_pmu_,rc_"
> +    },
> +    {
> +        "EventCode": "0x1",
> +        "EventName": "PCIE_TGT_WR_BYTES",
> +        "BriefDescription": "Counts bytes transferred by the write requests counted by PCIE_TGT_WR_REQ.",
> +        "PublicDescription": "Counts bytes transferred by the write requests counted by PCIE_TGT_WR_REQ. Destination filters work as described for PCIE_TGT_WR_REQ.",
> +        "Compat": "1070036b",
> +        "Unit": "nvidia_pcie_tgt_pmu_,rc_"
> +    },
> +    {
> +        "MetricName": "pcie_tgt_freq",
> +        "MetricGroup": "PCIE_TGT_Frequency",
> +        "MetricConstraint": "NO_GROUP_EVENTS",
> +        "MetricExpr": "(PCIE_TGT_CYCLES / aggr_nr(PCIE_TGT_CYCLES)) / 1e9 / duration_time",
> +        "ScaleUnit": "1GHz",
> +        "BriefDescription": "Frequency of the cycles at the PCIe interface to the Tegra SoC data fabric.",
> +        "PublicDescription": "Average frequency of the cycles at the PCIe interface to the Tegra SoC data fabric over the measurement interval.",
> +        "Compat": "1070036b",
> +        "Unit": "nvidia_pcie_tgt_pmu_,rc_"
> +    },
> +    {
> +        "MetricName": "pcie_tgt_avg_rd_bandwidth_to_all_dst",
> +        "MetricGroup": "PCIE_TGT_Bandwidth;PCIE_TGT_BW_PCIE_BAR_CXL_HDM",
> +        "MetricExpr": "PCIE_TGT_RD_BYTES@dst_addr_en=1,dst_addr_base=0,dst_addr_mask=0@ / 1e6 / duration_time",
> +        "ScaleUnit": "1MB/s",
> +        "BriefDescription": "Average read bandwidth to all PCIe BAR and CXL HDM ranges under this PCIe root complex.",
> +        "PublicDescription": "Average read bandwidth of requests from any source to all PCIe BAR and CXL HDM ranges under this PCIe root complex.",
> +        "Compat": "1070036b",
> +        "Unit": "nvidia_pcie_tgt_pmu_,rc_"
> +    },
> +    {
> +        "MetricName": "pcie_tgt_avg_wr_bandwidth_to_all_dst",
> +        "MetricGroup": "PCIE_TGT_Bandwidth;PCIE_TGT_BW_PCIE_BAR_CXL_HDM",
> +        "MetricExpr": "PCIE_TGT_WR_BYTES@dst_addr_en=1,dst_addr_base=0,dst_addr_mask=0@ / 1e6 / duration_time",
> +        "ScaleUnit": "1MB/s",
> +        "BriefDescription": "Average write bandwidth to all PCIe BAR and CXL HDM ranges under this PCIe root complex.",
> +        "PublicDescription": "Average write bandwidth of requests from any source to all PCIe BAR and CXL HDM ranges under this PCIe root complex.",
> +        "Compat": "1070036b",
> +        "Unit": "nvidia_pcie_tgt_pmu_,rc_"
> +    },
> +    {
> +        "MetricName": "pcie_tgt_avg_rd_bandwidth_to_pcie_bar",
> +        "MetricGroup": "PCIE_TGT_Bandwidth;PCIE_TGT_BW_PCIE_BAR",
> +        "MetricExpr": "PCIE_TGT_RD_BYTES / 1e6 / duration_time",
> +        "ScaleUnit": "1MB/s",
> +        "BriefDescription": "Average read bandwidth of PCIe BAR traffic to all root ports under this PCIe root complex.",
> +        "PublicDescription": "Average read bandwidth of PCIe BAR traffic from any source to all root ports under this PCIe root complex.",
> +        "Compat": "1070036b",
> +        "Unit": "nvidia_pcie_tgt_pmu_,rc_"
> +    },
> +    {
> +        "MetricName": "pcie_tgt_avg_wr_bandwidth_to_pcie_bar",
> +        "MetricGroup": "PCIE_TGT_Bandwidth;PCIE_TGT_BW_PCIE_BAR",
> +        "MetricExpr": "PCIE_TGT_WR_BYTES / 1e6 / duration_time",
> +        "ScaleUnit": "1MB/s",
> +        "BriefDescription": "Average write bandwidth of PCIe BAR traffic to all root ports under this PCIe root complex.",
> +        "PublicDescription": "Average write bandwidth of PCIe BAR traffic from any source to all root ports under this PCIe root complex.",
> +        "Compat": "1070036b",
> +        "Unit": "nvidia_pcie_tgt_pmu_,rc_"
> +    }
> +]
> --
> 2.43.0
>

Re: [PATCH 0/6] perf jevents: Add NVIDIA Tegra410 uncore PMU events and metrics

[Arnaldo Carvalho de Melo]

On Mon, Oct 19, 2026 at 06:23:16PM +0100, James Clark wrote:
> On 19/10/2026 17:42, Besar Wicaksono wrote:
> > Add event aliases and derived metrics for the NVIDIA Tegra410 uncore
> > PMUs.
 
> Reviewed-by: James Clark <james.clark@linaro.org>

Thanks, applied to perf-tools-next, for v7.4.

- Arnaldo

Re: [PATCH 0/6] perf jevents: Add NVIDIA Tegra410 uncore PMU events and metrics

[Ian Rogers]

On Tue, Oct 20, 2026 at 12:15 PM Arnaldo Carvalho de Melo
<acme@kernel.org> wrote:
>
> On Mon, Oct 19, 2026 at 06:23:16PM +0100, James Clark wrote:
> > On 19/10/2026 17:42, Besar Wicaksono wrote:
> > > Add event aliases and derived metrics for the NVIDIA Tegra410 uncore
> > > PMUs.
>
> > Reviewed-by: James Clark <james.clark@linaro.org>
>
> Thanks, applied to perf-tools-next, for v7.4.

Hi Arnaldo,

can we not take these in v7.4 as there is unaddressed feedback:
https://lore.kernel.org/linux-perf-users/CAP-5=fWucvdYefDOL3Vn=O=YUPEXE+tngDDfPLv-T5i3WkCJVA@mail.gmail.com/

The specific problem is that the NVidia PMUs have adopted a convention
not supported by the perf tool of 'pmu_name_<socket>_rc_<num>'. rc
stands for root complex. What ends up happening is that aggregation is
broken as the json is claiming that pmu_name is the PMU's name while
the suffix perf_pmus code thinks pmu_name_<socket>_rc is the pmu name.
They've wrangled support via the json by claiming these are sys
events.

We can either:
1) support a new suffix convention of <num>_rc_<num>
2) push back and ask the driver writers to name their PMU correctly as
defined in the ABI:
https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/ABI/testing/sysfs-bus-event_source-devices

If we do (1) then it would be nice if the support for that could be
contained in this patch series. In any case these events don't belong
in sys.

Thanks,
Ian

> - Arnaldo

Re: [PATCH 0/6] perf jevents: Add NVIDIA Tegra410 uncore PMU events and metrics

[Arnaldo Melo]

On October 20, 2026 5:32:48 PM GMT-03:00, Ian Rogers <irogers@google.com> wrote:
>On Tue, Oct 20, 2026 at 12:15 PM Arnaldo Carvalho de Melo
><acme@kernel.org> wrote:
>>
>> On Mon, Oct 19, 2026 at 06:23:16PM +0100, James Clark wrote:
>> > On 19/10/2026 17:42, Besar Wicaksono wrote:
>> > > Add event aliases and derived metrics for the NVIDIA Tegra410 uncore
>> > > PMUs.
>>
>> > Reviewed-by: James Clark <james.clark@linaro.org>
>>
>> Thanks, applied to perf-tools-next, for v7.4.
>
>Hi Arnaldo,
>
>can we not take these in v7.4 as there is unaddressed feedback:
>https://lore.kernel.org/linux-perf-users/CAP-5=fWucvdYefDOL3Vn=O=YUPEXE+tngDDfPLv-T5i3WkCJVA@mail.gmail.com

Sure, will remove until the discussion comes to a conclusion. 

- Arnaldo 

>
>The specific problem is that the NVidia PMUs have adopted a convention
>not supported by the perf tool of 'pmu_name_<socket>_rc_<num>'. rc
>stands for root complex. What ends up happening is that aggregation is
>broken as the json is claiming that pmu_name is the PMU's name while
>the suffix perf_pmus code thinks pmu_name_<socket>_rc is the pmu name.
>They've wrangled support via the json by claiming these are sys
>events.
>
>We can either:
>1) support a new suffix convention of <num>_rc_<num>
>2) push back and ask the driver writers to name their PMU correctly as
>defined in the ABI:
>https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/ABI/testing/sysfs-bus-event_source-devices
>
>If we do (1) then it would be nice if the support for that could be
>contained in this patch series. In any case these events don't belong
>in sys.
>
>Thanks,
>Ian
>
>> - Arnaldo

- Arnaldo