Re: [PATCH v2] pwm: atmel: Fix prescaler for periods of 2^32 clock cycles or more

[Karl Mehltretter <kmehltretter@gmail.com>]

Hi Uwe,

On Thu, Oct 22, 2026 at 10:29:42AM +0100, Uwe Kleine-König wrote:
> >  
> >  	if (shift > PWM_MAX_PRES) {
> >  		dev_err(pwmchip_parent(chip), "pres exceeds the maximum value\n");
> 
> just above this code snippet there is:
> 
> 	unsigned long long cycles = state->period;
> 
>         /* Calculate the period cycles and prescale value */
>         cycles *= clkrate;
>         do_div(cycles, NSEC_PER_SEC);
> 
> there is another overflow happening here if state->period * clkrate
> doesn't fit into an u64. A complete fix converts that to:
> 
> 	cycles = mul_u64_u64_div_u64(state->period, clkrate, NSEC_PER_SEC);
> 
> which prevents an overflow if clkrate ≤ NSEC_PER_SEC.
> The latter can be asserted by checking that at probe time after calling
> clk_rate_exclusive_get().
> 
> The options now are I apply your patch anyhow and the above can be
> addressed later, or you rework your patch to a complete fix. What is
> your preference?
> 

Good point. I took a look at this and will send an improved patch soon. 

Karl