Re: [PATCH v9 13/25] iommu/arm-smmu-v3-kvm: Add MMIO emulation

[Nicolin Chen <nicolinc@nvidia.com>]

On Thu, Oct 15, 2026 at 08:08:44PM +0000, Mostafa Saleh wrote:
> +static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu,
> +			     struct user_pt_regs *regs,
> +			     u64 esr, u32 off)
> +{
> +	bool is_write = esr & ESR_ELx_WNR;
> +	unsigned int len = BIT((esr & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT);
> +	int rd = (esr & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;
> +	const u64 read_write = -1ULL;
> +	const u64 no_access = 0;
> +	u64 mask = no_access;
> +	const u64 read_only = is_write ? no_access : read_write;
> +	bool is_xzr = (rd == 31);
> +	u64 val = is_xzr ? 0 : regs->regs[rd];
> +
> +	switch (off) {
> +	case ARM_SMMU_IDR0:
> +		if (len != sizeof(u32))
> +			break;

Maybe add a small helper to list all 64-bit registers:

static unsigned int smmu_reg_width(u32 off)
{
        switch (off) {
        case ARM_SMMU_CMDQ_BASE:
        case ARM_SMMU_STRTAB_BASE:
        case ARM_SMMU_EVTQ_BASE:
        case ARM_SMMU_PRIQ_BASE:
        case ARM_SMMU_EVTQ_IRQ_CFG0:
        case ARM_SMMU_PRIQ_IRQ_CFG0:
        case ARM_SMMU_GERROR_IRQ_CFG0:
                return sizeof(u64);
        default:
                return sizeof(u32);
        }
}

Then it'd be tighter by testing the width once, prior to switch (off)?

> +	/* Allowed RO 32 bit registers. */
> +	case ARM_SMMU_IIDR:
> +	case ARM_SMMU_IDR5:
> +	case ARM_SMMU_IDR3:
> +	case ARM_SMMU_IDR1:
> +	case ARM_SMMU_IRQ_CTRLACK:
> +	case ARM_SMMU_GERROR:
> +		if (len != sizeof(u32))
> +			break;
> +		mask = read_only;
> +		break;
> +	}
> +
> +	if (WARN_ON(!mask))
> +		goto out_ret;

Your cover letter mentions "WARNs are fatal in the hypervisor".

Is this WARN_ON fatal?

Nicolin