Re: [PATCH v9 17/25] iommu/arm-smmu-v3-kvm: Shadow stream table

[Nicolin Chen <nicolinc@nvidia.com>]

On Thu, Oct 15, 2026 at 08:08:48PM +0000, Mostafa Saleh wrote:
> @@ -538,6 +655,7 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu,
>  
>  		if (is_write) {
>  			bool last_cmdq_en = is_cmdq_enabled(smmu);
> +			bool last_smmu_en = is_smmu_enabled(smmu);

It'd read better with smmu_was_enabled and smmu_is_enabled.

> diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3-hyp.h b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3-hyp.h
> index 3903ae358555..31ab7a0335a8 100644
> --- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3-hyp.h
> +++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3-hyp.h
> @@ -27,6 +27,12 @@
>   * @cmdq_host:		Host view of the CMDQ, only q_base, base_dma and llq used
>   * @cmdq_max_shift:	Max shift for the CMDQ probed from HW
>   * @cr0:		Last value of CR0
> + * @host_ste_cfg:	Host stream table config
> + * @host_ste_base:	Host stream table base
> + * @strtab_cfg:		Stream table config as seen by HW
> + * @strtab_dma:		Physical address of the shadow stream table
> + * @strtab_size:	Size of the shadow stream table
> + *
>   * @mmio_addr, @mmio_size and ARM_SMMU_FEAT_COHERENCY are filled by the host
>   * before de-privilege, the rest by the hypervisor driver.
>   */
> @@ -50,6 +56,11 @@ struct hyp_arm_smmu_v3_device {
>  	struct arm_smmu_queue	cmdq_host;
>  	u32			cmdq_max_shift;
>  	u32			cr0;
> +	dma_addr_t		strtab_dma;
> +	size_t			strtab_size;
> +	u64			host_ste_cfg;
> +	u64			host_ste_base;
> +	struct arm_smmu_strtab_cfg strtab_cfg;

The order is different here than the kdocs.

Also, it might be cleaner to group host/shadow/hw stuff separately:

struct hyp_arm_smmu_v3_device {
	...
	struct hyp_arm_smmu_v3_device_host host;
	struct hyp_arm_smmu_v3_device_shadow shadow;
	struct hyp_arm_smmu_v3_device_hw hw;
	// Or
	struct {
		...
	} shadow;
	struct {
		...
	} host;
	struct {
		...
	} hw;
	...
};

Nicolin