From: Matthew Brost <matthew.brost@intel.com>
To: "Ceraolo Spurio, Daniele" <daniele.ceraolospurio@intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>,
<intel-xe@lists.freedesktop.org>
Subject: Re: [PATCH v3 3/3] drm/xe: Memset g2g buffer on resume
Date: Tue, 27 Oct 2026 16:43:32 -0700 [thread overview]
Message-ID: <auE3JKCsUzXk2Ph0@gsse-cloud1.jf.intel.com> (raw)
In-Reply-To: <482083e4-150e-4210-942d-b941e7c17b69@intel.com>
On Tue, Oct 27, 2026 at 04:19:49PM -0700, Ceraolo Spurio, Daniele wrote:
>
> On 10/23/2026 4:18 AM, Vinay Belgaumkar wrote:
> > KMD creates this buffer for use by GuC, it is also responsible for zeroing
> > it during resume. The buffer is marked as XE_BO_FLAG_PINNED_NORESTORE,
> > so we cannot trust its contents after a suspend cycle. This commit adds
> > xe_*_resume_early() functions for handling this and the C6 disable
> > during resume.
> >
> > v2: Maintain layering with _early functions for gt/uc/ct (Matt Brost)
> >
> > Cc: Matthew Brost <matthew.brost@intel.com>
> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_gt.c | 14 +++++++++++++-
> > drivers/gpu/drm/xe/xe_gt.h | 1 +
> > drivers/gpu/drm/xe/xe_guc_ct.c | 16 ++++++++++++++++
> > drivers/gpu/drm/xe/xe_guc_ct.h | 1 +
> > drivers/gpu/drm/xe/xe_pm.c | 4 ++--
> > drivers/gpu/drm/xe/xe_uc.c | 15 +++++++++++++++
> > drivers/gpu/drm/xe/xe_uc.h | 1 +
> > 7 files changed, 49 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> > index 60d35ada2853..96b5702347c1 100644
> > --- a/drivers/gpu/drm/xe/xe_gt.c
> > +++ b/drivers/gpu/drm/xe/xe_gt.c
> > @@ -50,7 +50,6 @@
> > #include "xe_lmtt.h"
> > #include "xe_log.h"
> > #include "xe_lrc.h"
> > -#include "xe_map.h"
>
> This seems unrelated to this patch
>
> > #include "xe_migrate.h"
> > #include "xe_mmio.h"
> > #include "xe_pagefault.h"
> > @@ -1093,6 +1092,19 @@ int xe_gt_sanitize_freq(struct xe_gt *gt)
> > return ret;
> > }
> > +/**
> > + * xe_gt_resume_early() - Early init for GT resume
> > + * @gt: the GT object
> > + *
> > + * Handles GT related init before GT restart after a suspend cycle.
> > + */
> > +void xe_gt_resume_early(struct xe_gt *gt)
> > +{
> > + xe_gt_idle_disable_c6(gt);
> > +
> > + xe_uc_resume_early(>->uc);
> > +}
> > +
> > int xe_gt_resume(struct xe_gt *gt)
> > {
> > int err;
> > diff --git a/drivers/gpu/drm/xe/xe_gt.h b/drivers/gpu/drm/xe/xe_gt.h
> > index 7b6952fe804c..7d292f9d0be7 100644
> > --- a/drivers/gpu/drm/xe/xe_gt.h
> > +++ b/drivers/gpu/drm/xe/xe_gt.h
> > @@ -58,6 +58,7 @@ void xe_gt_record_user_engines(struct xe_gt *gt);
> > void xe_gt_suspend_prepare(struct xe_gt *gt);
> > int xe_gt_suspend(struct xe_gt *gt);
> > void xe_gt_shutdown(struct xe_gt *gt);
> > +void xe_gt_resume_early(struct xe_gt *gt);
> > int xe_gt_resume(struct xe_gt *gt);
> > void xe_gt_reset_async(struct xe_gt *gt);
> > int xe_gt_runtime_resume(struct xe_gt *gt);
> > diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
> > index d42f0133c1eb..435b10c29e24 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_ct.c
> > +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
> > @@ -863,6 +863,22 @@ void xe_guc_ct_runtime_suspend(struct xe_guc_ct *ct)
> > xe_guc_ct_disable(ct);
> > }
> > +/**
> > + * xe_guc_ct_resume_early() - Early init for GuC CT resume
> > + * @ct: the &xe_guc_ct
> > + *
> > + * CT init before GT restart after a suspend cycle.
> > + */
> > +void xe_guc_ct_resume_early(struct xe_guc_ct *ct)
> > +{
> > + struct xe_guc *guc = ct_to_guc(ct);
> > + struct xe_device *xe = ct_to_xe(ct);
> > +
> > + /* clear the g2g buffer which is marked as NORESTORE during alloc */
> > + if (guc->g2g.bo && guc->g2g.owned)
> > + xe_map_memset(xe, &guc->g2g.bo->vmap, 0, 0, xe_bo_size(guc->g2g.bo));
>
> g2g has nothing to do with CT, so this should just be xe_guc_resume_early in
> xe_guc.c.
>
Yes, this was my bad. I though the g2g was allocated in CT and suggested
this. Daniele is right.
Matt
> Daniele
>
> > +}
> > +
> > /**
> > * xe_guc_ct_runtime_resume() - GuC CT runtime resume
> > * @ct: the &xe_guc_ct
> > diff --git a/drivers/gpu/drm/xe/xe_guc_ct.h b/drivers/gpu/drm/xe/xe_guc_ct.h
> > index f3af15c95c75..3470ced126de 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_ct.h
> > +++ b/drivers/gpu/drm/xe/xe_guc_ct.h
> > @@ -20,6 +20,7 @@ int xe_guc_ct_init_post_hwconfig(struct xe_guc_ct *ct);
> > int xe_guc_ct_enable(struct xe_guc_ct *ct);
> > int xe_guc_ct_restart(struct xe_guc_ct *ct);
> > void xe_guc_ct_disable(struct xe_guc_ct *ct);
> > +void xe_guc_ct_resume_early(struct xe_guc_ct *ct);
> > void xe_guc_ct_runtime_resume(struct xe_guc_ct *ct);
> > void xe_guc_ct_runtime_suspend(struct xe_guc_ct *ct);
> > void xe_guc_ct_stop(struct xe_guc_ct *ct);
> > diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c
> > index 1f5097875bcd..89d64aa6577d 100644
> > --- a/drivers/gpu/drm/xe/xe_pm.c
> > +++ b/drivers/gpu/drm/xe/xe_pm.c
> > @@ -249,7 +249,7 @@ int xe_pm_resume(struct xe_device *xe)
> > return err;
> > for_each_gt(gt, xe, id)
> > - xe_gt_idle_disable_c6(gt);
> > + xe_gt_resume_early(gt);
> > xe_display_pm_resume_early(xe);
> > @@ -703,7 +703,7 @@ int xe_pm_runtime_resume(struct xe_device *xe)
> > goto out;
> > for_each_gt(gt, xe, id)
> > - xe_gt_idle_disable_c6(gt);
> > + xe_gt_resume_early(gt);
> > xe_display_pm_resume_early(xe);
> > diff --git a/drivers/gpu/drm/xe/xe_uc.c b/drivers/gpu/drm/xe/xe_uc.c
> > index 686c28856014..2dfd525dce6f 100644
> > --- a/drivers/gpu/drm/xe/xe_uc.c
> > +++ b/drivers/gpu/drm/xe/xe_uc.c
> > @@ -12,6 +12,7 @@
> > #include "xe_gt_printk.h"
> > #include "xe_gt_sriov_vf.h"
> > #include "xe_guc.h"
> > +#include "xe_guc_ct.h"
> > #include "xe_guc_pc.h"
> > #include "xe_guc_rc.h"
> > #include "xe_guc_engine_activity.h"
> > @@ -297,6 +298,20 @@ int xe_uc_suspend(struct xe_uc *uc)
> > return xe_guc_suspend(&uc->guc);
> > }
> > +/**
> > + * xe_uc_resume_early() - Early init for UC resume
> > + * @uc: the UC object
> > + *
> > + * UC init before a GT restart during resume.
> > + */
> > +void xe_uc_resume_early(struct xe_uc *uc)
> > +{
> > + if (!xe_device_uc_enabled(uc_to_xe(uc)))
> > + return;
> > +
> > + xe_guc_ct_resume_early(&uc->guc.ct);
> > +}
> > +
> > /**
> > * xe_uc_runtime_suspend() - UC runtime suspend
> > * @uc: the UC object
> > diff --git a/drivers/gpu/drm/xe/xe_uc.h b/drivers/gpu/drm/xe/xe_uc.h
> > index 23bc0ce1c42f..3c56327fb3f9 100644
> > --- a/drivers/gpu/drm/xe/xe_uc.h
> > +++ b/drivers/gpu/drm/xe/xe_uc.h
> > @@ -13,6 +13,7 @@ int xe_uc_init(struct xe_uc *uc);
> > int xe_uc_init_post_hwconfig(struct xe_uc *uc);
> > int xe_uc_load_hw(struct xe_uc *uc);
> > int xe_uc_reset_prepare(struct xe_uc *uc);
> > +void xe_uc_resume_early(struct xe_uc *uc);
> > void xe_uc_runtime_resume(struct xe_uc *uc);
> > void xe_uc_runtime_suspend(struct xe_uc *uc);
> > void xe_uc_stop_prepare(struct xe_uc *uc);
next prev parent reply other threads:[~2026-10-27 23:44 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-23 11:18 [PATCH v3 0/3] drm/xe: Some d3cold related fixes Vinay Belgaumkar
2026-10-23 11:18 ` [PATCH v3 1/3] drm/xe: Toggle the D3Cold enable flag at runtime resume Vinay Belgaumkar
[not found] ` <6d32a45c-4090-442b-9162-63d285963350@intel.com>
2026-10-26 16:25 ` Fwd: " Poosa, Karthik
2026-10-23 11:18 ` [PATCH v3 2/3] drm/xe: Access GT MMIO after pcode init Vinay Belgaumkar
2026-10-26 16:06 ` Poosa, Karthik
2026-10-23 11:18 ` [PATCH v3 3/3] drm/xe: Memset g2g buffer on resume Vinay Belgaumkar
2026-10-27 23:19 ` Ceraolo Spurio, Daniele
2026-10-27 23:43 ` Matthew Brost [this message]
2026-10-23 19:01 ` ✓ CI.KUnit: success for drm/xe: Some d3cold related fixes (rev3) Patchwork
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