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From: Nicolin Chen <nicolinc@nvidia.com>
To: Jason Gunthorpe <jgg@nvidia.com>
Cc: Shameer Kolothum Thodi <skolothumtho@nvidia.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	"joro@8bytes.org" <joro@8bytes.org>,
	Robin Murphy <robin.murphy@arm.com>,
	"rafael@kernel.org" <rafael@kernel.org>,
	Danilo Krummrich <dakr@kernel.org>,
	Marek Szyprowski <m.szyprowski@samsung.com>,
	"aneesh.kumar@kernel.org" <aneesh.kumar@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Gavin Shan <gshan@redhat.com>, Vikram Sethi <vsethi@nvidia.com>,
	Anshuman Khandual <anshuman.khandual@arm.com>,
	"Shanker Donthineni" <sdonthineni@nvidia.com>,
	Mostafa Saleh <smostafa@google.com>,
	"rppt@kernel.org" <rppt@kernel.org>,
	Thomas Huth <thuth@redhat.com>, "Marc Zyngier" <maz@kernel.org>,
	Ryan Roberts <ryan.roberts@arm.com>,
	"kas@kernel.org" <kas@kernel.org>,
	Kohei Enju <enju.kohei@fujitsu.com>,
	Shaopeng Tan <tan.shaopeng@jp.fujitsu.com>,
	Ard Biesheuvel <ardb@kernel.org>,
	James Morse <james.morse@arm.com>,
	Steven Price <steven.price@arm.com>,
	Sang-Heon Jeon <ekffu200098@gmail.com>,
	Omar Sandoval <osandov@fb.com>,
	Andrew Morton <akpm@linux-foundation.org>,
	Jinjie Ruan <ruanjinjie@huawei.com>,
	Sam Edwards <cfsworks@gmail.com>,
	Douglas Anderson <dianders@chromium.org>,
	Florian Fainelli <florian.fainelli@broadcom.com>,
	Chen-Yu Tsai <wenst@chromium.org>,
	Huacai Chen <chenhuacai@kernel.org>,
	Thomas Zimmermann <tzimmermann@suse.de>,
	Pranjal Shrivastava <praan@google.com>,
	Ashish Mhetre <amhetre@nvidia.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"iommu@lists.linux.dev" <iommu@lists.linux.dev>,
	"driver-core@lists.linux.dev" <driver-core@lists.linux.dev>,
	Sonang Patel <sonangp@nvidia.com>,
	"Ankit Agrawal" <ankita@nvidia.com>
Subject: Re: [PATCH v1 7/8] iommu: Park TDISP T=0 devices in the blocking domain
Date: Wed, 28 Oct 2026 11:51:38 -0700	[thread overview]
Message-ID: <auJEOpTq6EbMZUuv@nvidia.com> (raw)
In-Reply-To: <20261028150909.GC3040767@nvidia.com>

On Wed, Oct 28, 2026 at 12:09:09PM -0300, Jason Gunthorpe wrote:
> On Wed, Oct 28, 2026 at 02:19:17PM +0000, Shameer Kolothum Thodi wrote:
> > > +	/*
> > > +	 * When in T=0 mode the T=1 vIOMMU must always be set to
> > > BLOCKED to
> > > +	 * release control of ATS.
> > > +	 */
> > > +	if (iommu_using_t0_stream(first)) {
> > > +		if (!ops->blocked_domain)
> > > +			return ERR_PTR(-EINVAL);
> > > +		return ops->blocked_domain;
> > 
> > How is MSI allocation handled for T=0 devices? The ITS calls
> > iommu_dma_prepare_msi(), which appears to return -EOPNOTSUPP
> > for the blocked domain. Is that intentional?
> 
> For a TDISP capable devince MSI is always issued using T=0, meaning it
> does not go through the SMMU. It should be wired to defeat
> iommu_dma_prepare_msi() and use an identity IOVA as though there is no
> iommu present..

I'll fold this in:

------------------------------------------------------------
diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
index d6b00e0373f5c..1474224c2565f 100644
--- a/drivers/iommu/iommu.c
+++ b/drivers/iommu/iommu.c
@@ -4324,8 +4324,9 @@ int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr)
 		return 0;
 
 	mutex_lock(&group->mutex);
-	/* An IDENTITY domain must pass through */
-	if (group->domain && group->domain->type != IOMMU_DOMAIN_IDENTITY) {
+	/* An IDENTITY domain or a T=0 device must pass through */
+	if (group->domain && group->domain->type != IOMMU_DOMAIN_IDENTITY &&
+	    !iommu_using_t0_stream(dev)) {
 		switch (group->domain->cookie_type) {
 		case IOMMU_COOKIE_DMA_MSI:
 		case IOMMU_COOKIE_DMA_IOVA:
------------------------------------------------------------

Thanks
Nicolin

  reply	other threads:[~2026-10-28 18:52 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-10  3:32 [PATCH v1 0/8] iommu/arm-smmu-v3: Support guest-level Realm VSMMU (Part-1) Nicolin Chen
2026-09-10  3:32 ` [PATCH v1 1/8] firmware: arm_rmm: Move RSI support out of arch/arm64 Nicolin Chen
2026-09-10  3:32 ` [PATCH v1 2/8] firmware: arm_rmm: Add VSMMU commands and fields Nicolin Chen
2026-10-28  9:49   ` Shameer Kolothum Thodi
2026-10-28 12:35     ` Jason Gunthorpe
2026-10-28 18:38       ` Nicolin Chen
2026-10-29 10:05         ` Shameer Kolothum Thodi
2026-10-29 12:28           ` Jason Gunthorpe
2026-09-10  3:32 ` [PATCH v1 3/8] dma-mapping: Let a device declare that it reaches private memory Nicolin Chen
2026-09-10  3:32 ` [PATCH v1 4/8] dma-mapping: Keep DMA memory private for capable devices Nicolin Chen
2026-10-28 10:42   ` Shameer Kolothum Thodi
2026-10-28 12:38     ` Jason Gunthorpe
2026-09-10  3:32 ` [PATCH v1 5/8] iommu: Let a driver mark an IOMMU as confidential Nicolin Chen
2026-09-10  3:32 ` [PATCH v1 6/8] iommu: Introduce TDISP T=0 state for confidential IOMMUs Nicolin Chen
2026-09-17 10:48   ` sonang patel
2026-09-17 13:34     ` Jason Gunthorpe
2026-09-10  3:32 ` [PATCH v1 7/8] iommu: Park TDISP T=0 devices in the blocking domain Nicolin Chen
2026-10-28 14:19   ` Shameer Kolothum Thodi
2026-10-28 15:09     ` Jason Gunthorpe
2026-10-28 18:51       ` Nicolin Chen [this message]
2026-09-10  3:32 ` [PATCH v1 8/8] iommu/arm-smmu-v3: Probe a guest-level Realm VSMMU via RSI commands Nicolin Chen
2026-09-10  4:23   ` Nicolin Chen
2026-10-28 15:41   ` Shameer Kolothum Thodi
2026-10-28 18:08     ` Nicolin Chen
2026-10-29  7:58       ` Shameer Kolothum Thodi

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